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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / neterion / vxge / vxge-config.c
blob5162b938a1ac0bde5a85083d701fa36b18c26104
1 /******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
10 * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2010 Exar Corp.
13 ******************************************************************************/
14 #include <linux/vmalloc.h>
15 #include <linux/etherdevice.h>
16 #include <linux/io-64-nonatomic-lo-hi.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19
20 #include "vxge-traffic.h"
21 #include "vxge-config.h"
22 #include "vxge-main.h"
23
24 #define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \
25 status = __vxge_hw_vpath_stats_access(vpath, \
26 VXGE_HW_STATS_OP_READ, \
27 offset, \
28 &val64); \
29 if (status != VXGE_HW_OK) \
30 return status; \
31 }
32
33 static void
34 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
35 {
36 u64 val64;
37
38 val64 = readq(&vp_reg->rxmac_vcfg0);
39 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
40 writeq(val64, &vp_reg->rxmac_vcfg0);
41 val64 = readq(&vp_reg->rxmac_vcfg0);
42 }
43
44 /*
45 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
46 */
47 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
48 {
49 struct vxge_hw_vpath_reg __iomem *vp_reg;
50 struct __vxge_hw_virtualpath *vpath;
51 u64 val64, rxd_count, rxd_spat;
52 int count = 0, total_count = 0;
53
54 vpath = &hldev->virtual_paths[vp_id];
55 vp_reg = vpath->vp_reg;
56
57 vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
58
59 /* Check that the ring controller for this vpath has enough free RxDs
60 * to send frames to the host. This is done by reading the
61 * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
62 * RXD_SPAT value for the vpath.
63 */
64 val64 = readq(&vp_reg->prc_cfg6);
65 rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
66 /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
67 * leg room.
68 */
69 rxd_spat *= 2;
70
71 do {
72 mdelay(1);
73
74 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
75
76 /* Check that the ring controller for this vpath does
77 * not have any frame in its pipeline.
78 */
79 val64 = readq(&vp_reg->frm_in_progress_cnt);
80 if ((rxd_count <= rxd_spat) || (val64 > 0))
81 count = 0;
82 else
83 count++;
84 total_count++;
85 } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
86 (total_count < VXGE_HW_MAX_POLLING_COUNT));
87
88 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
89 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
90 __func__);
91
92 return total_count;
93 }
94
95 /* vxge_hw_device_wait_receive_idle - This function waits until all frames
96 * stored in the frame buffer for each vpath assigned to the given
97 * function (hldev) have been sent to the host.
98 */
99 void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
100 {
101 int i, total_count = 0;
102
103 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
104 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
105 continue;
106
107 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
108 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
109 break;
110 }
111 }
112
113 /*
114 * __vxge_hw_device_register_poll
115 * Will poll certain register for specified amount of time.
116 * Will poll until masked bit is not cleared.
117 */
118 static enum vxge_hw_status
119 __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
120 {
121 u64 val64;
122 u32 i = 0;
123
124 udelay(10);
125
126 do {
127 val64 = readq(reg);
128 if (!(val64 & mask))
129 return VXGE_HW_OK;
130 udelay(100);
131 } while (++i <= 9);
132
133 i = 0;
134 do {
135 val64 = readq(reg);
136 if (!(val64 & mask))
137 return VXGE_HW_OK;
138 mdelay(1);
139 } while (++i <= max_millis);
140
141 return VXGE_HW_FAIL;
142 }
143
144 static inline enum vxge_hw_status
145 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
146 u64 mask, u32 max_millis)
147 {
148 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
149 wmb();
150 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
151 wmb();
152
153 return __vxge_hw_device_register_poll(addr, mask, max_millis);
154 }
155
156 static enum vxge_hw_status
157 vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
158 u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
159 u64 *steer_ctrl)
160 {
161 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
162 enum vxge_hw_status status;
163 u64 val64;
164 u32 retry = 0, max_retry = 3;
165
166 spin_lock(&vpath->lock);
167 if (!vpath->vp_open) {
168 spin_unlock(&vpath->lock);
169 max_retry = 100;
170 }
171
172 writeq(*data0, &vp_reg->rts_access_steer_data0);
173 writeq(*data1, &vp_reg->rts_access_steer_data1);
174 wmb();
175
176 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
177 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
178 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
179 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
180 *steer_ctrl;
181
182 status = __vxge_hw_pio_mem_write64(val64,
183 &vp_reg->rts_access_steer_ctrl,
184 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
185 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
186
187 /* The __vxge_hw_device_register_poll can udelay for a significant
188 * amount of time, blocking other process from the CPU. If it delays
189 * for ~5secs, a NMI error can occur. A way around this is to give up
190 * the processor via msleep, but this is not allowed is under lock.
191 * So, only allow it to sleep for ~4secs if open. Otherwise, delay for
192 * 1sec and sleep for 10ms until the firmware operation has completed
193 * or timed-out.
194 */
195 while ((status != VXGE_HW_OK) && retry++ < max_retry) {
196 if (!vpath->vp_open)
197 msleep(20);
198 status = __vxge_hw_device_register_poll(
199 &vp_reg->rts_access_steer_ctrl,
200 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
201 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
202 }
203
204 if (status != VXGE_HW_OK)
205 goto out;
206
207 val64 = readq(&vp_reg->rts_access_steer_ctrl);
208 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
209 *data0 = readq(&vp_reg->rts_access_steer_data0);
210 *data1 = readq(&vp_reg->rts_access_steer_data1);
211 *steer_ctrl = val64;
212 } else
213 status = VXGE_HW_FAIL;
214
215 out:
216 if (vpath->vp_open)
217 spin_unlock(&vpath->lock);
218 return status;
219 }
220
221 enum vxge_hw_status
222 vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
223 u32 *minor, u32 *build)
224 {
225 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
226 struct __vxge_hw_virtualpath *vpath;
227 enum vxge_hw_status status;
228
229 vpath = &hldev->virtual_paths[hldev->first_vp_id];
230
231 status = vxge_hw_vpath_fw_api(vpath,
232 VXGE_HW_FW_UPGRADE_ACTION,
233 VXGE_HW_FW_UPGRADE_MEMO,
234 VXGE_HW_FW_UPGRADE_OFFSET_READ,
235 &data0, &data1, &steer_ctrl);
236 if (status != VXGE_HW_OK)
237 return status;
238
239 *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
240 *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
241 *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
242
243 return status;
244 }
245
246 enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
247 {
248 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
249 struct __vxge_hw_virtualpath *vpath;
250 enum vxge_hw_status status;
251 u32 ret;
252
253 vpath = &hldev->virtual_paths[hldev->first_vp_id];
254
255 status = vxge_hw_vpath_fw_api(vpath,
256 VXGE_HW_FW_UPGRADE_ACTION,
257 VXGE_HW_FW_UPGRADE_MEMO,
258 VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
259 &data0, &data1, &steer_ctrl);
260 if (status != VXGE_HW_OK) {
261 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
262 goto exit;
263 }
264
265 ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
266 if (ret != 1) {
267 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
268 __func__, ret);
269 status = VXGE_HW_FAIL;
270 }
271
272 exit:
273 return status;
274 }
275
276 enum vxge_hw_status
277 vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
278 {
279 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
280 struct __vxge_hw_virtualpath *vpath;
281 enum vxge_hw_status status;
282 int ret_code, sec_code;
283
284 vpath = &hldev->virtual_paths[hldev->first_vp_id];
285
286 /* send upgrade start command */
287 status = vxge_hw_vpath_fw_api(vpath,
288 VXGE_HW_FW_UPGRADE_ACTION,
289 VXGE_HW_FW_UPGRADE_MEMO,
290 VXGE_HW_FW_UPGRADE_OFFSET_START,
291 &data0, &data1, &steer_ctrl);
292 if (status != VXGE_HW_OK) {
293 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
294 __func__);
295 return status;
296 }
297
298 /* Transfer fw image to adapter 16 bytes at a time */
299 for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
300 steer_ctrl = 0;
301
302 /* The next 128bits of fwdata to be loaded onto the adapter */
303 data0 = *((u64 *)fwdata);
304 data1 = *((u64 *)fwdata + 1);
305
306 status = vxge_hw_vpath_fw_api(vpath,
307 VXGE_HW_FW_UPGRADE_ACTION,
308 VXGE_HW_FW_UPGRADE_MEMO,
309 VXGE_HW_FW_UPGRADE_OFFSET_SEND,
310 &data0, &data1, &steer_ctrl);
311 if (status != VXGE_HW_OK) {
312 vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
313 __func__);
314 goto out;
315 }
316
317 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
318 switch (ret_code) {
319 case VXGE_HW_FW_UPGRADE_OK:
320 /* All OK, send next 16 bytes. */
321 break;
322 case VXGE_FW_UPGRADE_BYTES2SKIP:
323 /* skip bytes in the stream */
324 fwdata += (data0 >> 8) & 0xFFFFFFFF;
325 break;
326 case VXGE_HW_FW_UPGRADE_DONE:
327 goto out;
328 case VXGE_HW_FW_UPGRADE_ERR:
329 sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
330 switch (sec_code) {
331 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
332 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
333 printk(KERN_ERR
334 "corrupted data from .ncf file\n");
335 break;
336 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
337 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
338 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
339 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
340 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
341 printk(KERN_ERR "invalid .ncf file\n");
342 break;
343 case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
344 printk(KERN_ERR "buffer overflow\n");
345 break;
346 case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
347 printk(KERN_ERR "failed to flash the image\n");
348 break;
349 case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
350 printk(KERN_ERR
351 "generic error. Unknown error type\n");
352 break;
353 default:
354 printk(KERN_ERR "Unknown error of type %d\n",
355 sec_code);
356 break;
357 }
358 status = VXGE_HW_FAIL;
359 goto out;
360 default:
361 printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
362 status = VXGE_HW_FAIL;
363 goto out;
364 }
365 /* point to next 16 bytes */
366 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
367 }
368 out:
369 return status;
370 }
371
372 enum vxge_hw_status
373 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
374 struct eprom_image *img)
375 {
376 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
377 struct __vxge_hw_virtualpath *vpath;
378 enum vxge_hw_status status;
379 int i;
380
381 vpath = &hldev->virtual_paths[hldev->first_vp_id];
382
383 for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
384 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
385 data1 = steer_ctrl = 0;
386
387 status = vxge_hw_vpath_fw_api(vpath,
388 VXGE_HW_FW_API_GET_EPROM_REV,
389 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
390 0, &data0, &data1, &steer_ctrl);
391 if (status != VXGE_HW_OK)
392 break;
393
394 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
395 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
396 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
397 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
398 }
399
400 return status;
401 }
402
403 /*
404 * __vxge_hw_channel_free - Free memory allocated for channel
405 * This function deallocates memory from the channel and various arrays
406 * in the channel
407 */
408 static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
409 {
410 kfree(channel->work_arr);
411 kfree(channel->free_arr);
412 kfree(channel->reserve_arr);
413 kfree(channel->orig_arr);
414 kfree(channel);
415 }
416
417 /*
418 * __vxge_hw_channel_initialize - Initialize a channel
419 * This function initializes a channel by properly setting the
420 * various references
421 */
422 static enum vxge_hw_status
423 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
424 {
425 u32 i;
426 struct __vxge_hw_virtualpath *vpath;
427
428 vpath = channel->vph->vpath;
429
430 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
431 for (i = 0; i < channel->length; i++)
432 channel->orig_arr[i] = channel->reserve_arr[i];
433 }
434
435 switch (channel->type) {
436 case VXGE_HW_CHANNEL_TYPE_FIFO:
437 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
438 channel->stats = &((struct __vxge_hw_fifo *)
439 channel)->stats->common_stats;
440 break;
441 case VXGE_HW_CHANNEL_TYPE_RING:
442 vpath->ringh = (struct __vxge_hw_ring *)channel;
443 channel->stats = &((struct __vxge_hw_ring *)
444 channel)->stats->common_stats;
445 break;
446 default:
447 break;
448 }
449
450 return VXGE_HW_OK;
451 }
452
453 /*
454 * __vxge_hw_channel_reset - Resets a channel
455 * This function resets a channel by properly setting the various references
456 */
457 static enum vxge_hw_status
458 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
459 {
460 u32 i;
461
462 for (i = 0; i < channel->length; i++) {
463 if (channel->reserve_arr != NULL)
464 channel->reserve_arr[i] = channel->orig_arr[i];
465 if (channel->free_arr != NULL)
466 channel->free_arr[i] = NULL;
467 if (channel->work_arr != NULL)
468 channel->work_arr[i] = NULL;
469 }
470 channel->free_ptr = channel->length;
471 channel->reserve_ptr = channel->length;
472 channel->reserve_top = 0;
473 channel->post_index = 0;
474 channel->compl_index = 0;
475
476 return VXGE_HW_OK;
477 }
478
479 /*
480 * __vxge_hw_device_pci_e_init
481 * Initialize certain PCI/PCI-X configuration registers
482 * with recommended values. Save config space for future hw resets.
483 */
484 static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
485 {
486 u16 cmd = 0;
487
488 /* Set the PErr Repconse bit and SERR in PCI command register. */
489 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
490 cmd |= 0x140;
491 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
492
493 pci_save_state(hldev->pdev);
494 }
495
496 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
497 * in progress
498 * This routine checks the vpath reset in progress register is turned zero
499 */
500 static enum vxge_hw_status
501 __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
502 {
503 enum vxge_hw_status status;
504 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
505 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
506 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
507 return status;
508 }
509
510 /*
511 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
512 * Set the swapper bits appropriately for the lagacy section.
513 */
514 static enum vxge_hw_status
515 __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
516 {
517 u64 val64;
518 enum vxge_hw_status status = VXGE_HW_OK;
519
520 val64 = readq(&legacy_reg->toc_swapper_fb);
521
522 wmb();
523
524 switch (val64) {
525 case VXGE_HW_SWAPPER_INITIAL_VALUE:
526 return status;
527
528 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
529 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
530 &legacy_reg->pifm_rd_swap_en);
531 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
532 &legacy_reg->pifm_rd_flip_en);
533 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
534 &legacy_reg->pifm_wr_swap_en);
535 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
536 &legacy_reg->pifm_wr_flip_en);
537 break;
538
539 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
540 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
541 &legacy_reg->pifm_rd_swap_en);
542 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
543 &legacy_reg->pifm_wr_swap_en);
544 break;
545
546 case VXGE_HW_SWAPPER_BIT_FLIPPED:
547 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
548 &legacy_reg->pifm_rd_flip_en);
549 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
550 &legacy_reg->pifm_wr_flip_en);
551 break;
552 }
553
554 wmb();
555
556 val64 = readq(&legacy_reg->toc_swapper_fb);
557
558 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
559 status = VXGE_HW_ERR_SWAPPER_CTRL;
560
561 return status;
562 }
563
564 /*
565 * __vxge_hw_device_toc_get
566 * This routine sets the swapper and reads the toc pointer and returns the
567 * memory mapped address of the toc
568 */
569 static struct vxge_hw_toc_reg __iomem *
570 __vxge_hw_device_toc_get(void __iomem *bar0)
571 {
572 u64 val64;
573 struct vxge_hw_toc_reg __iomem *toc = NULL;
574 enum vxge_hw_status status;
575
576 struct vxge_hw_legacy_reg __iomem *legacy_reg =
577 (struct vxge_hw_legacy_reg __iomem *)bar0;
578
579 status = __vxge_hw_legacy_swapper_set(legacy_reg);
580 if (status != VXGE_HW_OK)
581 goto exit;
582
583 val64 = readq(&legacy_reg->toc_first_pointer);
584 toc = bar0 + val64;
585 exit:
586 return toc;
587 }
588
589 /*
590 * __vxge_hw_device_reg_addr_get
591 * This routine sets the swapper and reads the toc pointer and initializes the
592 * register location pointers in the device object. It waits until the ric is
593 * completed initializing registers.
594 */
595 static enum vxge_hw_status
596 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
597 {
598 u64 val64;
599 u32 i;
600 enum vxge_hw_status status = VXGE_HW_OK;
601
602 hldev->legacy_reg = hldev->bar0;
603
604 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
605 if (hldev->toc_reg == NULL) {
606 status = VXGE_HW_FAIL;
607 goto exit;
608 }
609
610 val64 = readq(&hldev->toc_reg->toc_common_pointer);
611 hldev->common_reg = hldev->bar0 + val64;
612
613 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
614 hldev->mrpcim_reg = hldev->bar0 + val64;
615
616 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
617 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
618 hldev->srpcim_reg[i] = hldev->bar0 + val64;
619 }
620
621 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
622 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
623 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
624 }
625
626 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
627 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
628 hldev->vpath_reg[i] = hldev->bar0 + val64;
629 }
630
631 val64 = readq(&hldev->toc_reg->toc_kdfc);
632
633 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
634 case 0:
635 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
636 break;
637 default:
638 break;
639 }
640
641 status = __vxge_hw_device_vpath_reset_in_prog_check(
642 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
643 exit:
644 return status;
645 }
646
647 /*
648 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
649 * This routine returns the Access Rights of the driver
650 */
651 static u32
652 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
653 {
654 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
655
656 switch (host_type) {
657 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
658 if (func_id == 0) {
659 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
660 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
661 }
662 break;
663 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
664 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
665 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
666 break;
667 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
668 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
669 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
670 break;
671 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
672 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
673 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
674 break;
675 case VXGE_HW_SR_VH_FUNCTION0:
676 case VXGE_HW_VH_NORMAL_FUNCTION:
677 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
678 break;
679 }
680
681 return access_rights;
682 }
683 /*
684 * __vxge_hw_device_is_privilaged
685 * This routine checks if the device function is privilaged or not
686 */
687
688 enum vxge_hw_status
689 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
690 {
691 if (__vxge_hw_device_access_rights_get(host_type,
692 func_id) &
693 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
694 return VXGE_HW_OK;
695 else
696 return VXGE_HW_ERR_PRIVILEGED_OPERATION;
697 }
698
699 /*
700 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
701 * Returns the function number of the vpath.
702 */
703 static u32
704 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
705 {
706 u64 val64;
707
708 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
709
710 return
711 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
712 }
713
714 /*
715 * __vxge_hw_device_host_info_get
716 * This routine returns the host type assignments
717 */
718 static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
719 {
720 u64 val64;
721 u32 i;
722
723 val64 = readq(&hldev->common_reg->host_type_assignments);
724
725 hldev->host_type =
726 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
727
728 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
729
730 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
731 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
732 continue;
733
734 hldev->func_id =
735 __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
736
737 hldev->access_rights = __vxge_hw_device_access_rights_get(
738 hldev->host_type, hldev->func_id);
739
740 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
741 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
742
743 hldev->first_vp_id = i;
744 break;
745 }
746 }
747
748 /*
749 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
750 * link width and signalling rate.
751 */
752 static enum vxge_hw_status
753 __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
754 {
755 struct pci_dev *dev = hldev->pdev;
756 u16 lnk;
757
758 /* Get the negotiated link width and speed from PCI config space */
759 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
760
761 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
762 return VXGE_HW_ERR_INVALID_PCI_INFO;
763
764 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
765 case PCIE_LNK_WIDTH_RESRV:
766 case PCIE_LNK_X1:
767 case PCIE_LNK_X2:
768 case PCIE_LNK_X4:
769 case PCIE_LNK_X8:
770 break;
771 default:
772 return VXGE_HW_ERR_INVALID_PCI_INFO;
773 }
774
775 return VXGE_HW_OK;
776 }
777
778 /*
779 * __vxge_hw_device_initialize
780 * Initialize Titan-V hardware.
781 */
782 static enum vxge_hw_status
783 __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
784 {
785 enum vxge_hw_status status = VXGE_HW_OK;
786
787 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
788 hldev->func_id)) {
789 /* Validate the pci-e link width and speed */
790 status = __vxge_hw_verify_pci_e_info(hldev);
791 if (status != VXGE_HW_OK)
792 goto exit;
793 }
794
795 exit:
796 return status;
797 }
798
799 /*
800 * __vxge_hw_vpath_fw_ver_get - Get the fw version
801 * Returns FW Version
802 */
803 static enum vxge_hw_status
804 __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
805 struct vxge_hw_device_hw_info *hw_info)
806 {
807 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
808 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
809 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
810 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
811 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
812 enum vxge_hw_status status;
813
814 status = vxge_hw_vpath_fw_api(vpath,
815 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
816 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
817 0, &data0, &data1, &steer_ctrl);
818 if (status != VXGE_HW_OK)
819 goto exit;
820
821 fw_date->day =
822 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
823 fw_date->month =
824 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
825 fw_date->year =
826 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
827
828 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
829 fw_date->month, fw_date->day, fw_date->year);
830
831 fw_version->major =
832 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
833 fw_version->minor =
834 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
835 fw_version->build =
836 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
837
838 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
839 fw_version->major, fw_version->minor, fw_version->build);
840
841 flash_date->day =
842 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
843 flash_date->month =
844 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
845 flash_date->year =
846 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
847
848 snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
849 flash_date->month, flash_date->day, flash_date->year);
850
851 flash_version->major =
852 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
853 flash_version->minor =
854 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
855 flash_version->build =
856 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
857
858 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
859 flash_version->major, flash_version->minor,
860 flash_version->build);
861
862 exit:
863 return status;
864 }
865
866 /*
867 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
868 * part number and product description.
869 */
870 static enum vxge_hw_status
871 __vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
872 struct vxge_hw_device_hw_info *hw_info)
873 {
874 __be64 *serial_number = (void *)hw_info->serial_number;
875 __be64 *product_desc = (void *)hw_info->product_desc;
876 __be64 *part_number = (void *)hw_info->part_number;
877 enum vxge_hw_status status;
878 u64 data0, data1 = 0, steer_ctrl = 0;
879 u32 i, j = 0;
880
881 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
882
883 status = vxge_hw_vpath_fw_api(vpath,
884 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
885 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
886 0, &data0, &data1, &steer_ctrl);
887 if (status != VXGE_HW_OK)
888 return status;
889
890 serial_number[0] = cpu_to_be64(data0);
891 serial_number[1] = cpu_to_be64(data1);
892
893 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
894 data1 = steer_ctrl = 0;
895
896 status = vxge_hw_vpath_fw_api(vpath,
897 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
898 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
899 0, &data0, &data1, &steer_ctrl);
900 if (status != VXGE_HW_OK)
901 return status;
902
903 part_number[0] = cpu_to_be64(data0);
904 part_number[1] = cpu_to_be64(data1);
905
906 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
907 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
908 data0 = i;
909 data1 = steer_ctrl = 0;
910
911 status = vxge_hw_vpath_fw_api(vpath,
912 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
913 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
914 0, &data0, &data1, &steer_ctrl);
915 if (status != VXGE_HW_OK)
916 return status;
917
918 product_desc[j++] = cpu_to_be64(data0);
919 product_desc[j++] = cpu_to_be64(data1);
920 }
921
922 return status;
923 }
924
925 /*
926 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
927 * Returns pci function mode
928 */
929 static enum vxge_hw_status
930 __vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
931 struct vxge_hw_device_hw_info *hw_info)
932 {
933 u64 data0, data1 = 0, steer_ctrl = 0;
934 enum vxge_hw_status status;
935
936 data0 = 0;
937
938 status = vxge_hw_vpath_fw_api(vpath,
939 VXGE_HW_FW_API_GET_FUNC_MODE,
940 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
941 0, &data0, &data1, &steer_ctrl);
942 if (status != VXGE_HW_OK)
943 return status;
944
945 hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
946 return status;
947 }
948
949 /*
950 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
951 * from MAC address table.
952 */
953 static enum vxge_hw_status
954 __vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
955 u8 *macaddr, u8 *macaddr_mask)
956 {
957 u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
958 data0 = 0, data1 = 0, steer_ctrl = 0;
959 enum vxge_hw_status status;
960 int i;
961
962 do {
963 status = vxge_hw_vpath_fw_api(vpath, action,
964 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
965 0, &data0, &data1, &steer_ctrl);
966 if (status != VXGE_HW_OK)
967 goto exit;
968
969 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
970 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
971 data1);
972
973 for (i = ETH_ALEN; i > 0; i--) {
974 macaddr[i - 1] = (u8) (data0 & 0xFF);
975 data0 >>= 8;
976
977 macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
978 data1 >>= 8;
979 }
980
981 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
982 data0 = 0, data1 = 0, steer_ctrl = 0;
983
984 } while (!is_valid_ether_addr(macaddr));
985 exit:
986 return status;
987 }
988
989 /**
990 * vxge_hw_device_hw_info_get - Get the hw information
991 * @bar0: the bar
992 * @hw_info: the hw_info struct
993 *
994 * Returns the vpath mask that has the bits set for each vpath allocated
995 * for the driver, FW version information, and the first mac address for
996 * each vpath
997 */
998 enum vxge_hw_status
999 vxge_hw_device_hw_info_get(void __iomem *bar0,
1000 struct vxge_hw_device_hw_info *hw_info)
1001 {
1002 u32 i;
1003 u64 val64;
1004 struct vxge_hw_toc_reg __iomem *toc;
1005 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1006 struct vxge_hw_common_reg __iomem *common_reg;
1007 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1008 enum vxge_hw_status status;
1009 struct __vxge_hw_virtualpath vpath;
1010
1011 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1012
1013 toc = __vxge_hw_device_toc_get(bar0);
1014 if (toc == NULL) {
1015 status = VXGE_HW_ERR_CRITICAL;
1016 goto exit;
1017 }
1018
1019 val64 = readq(&toc->toc_common_pointer);
1020 common_reg = bar0 + val64;
1021
1022 status = __vxge_hw_device_vpath_reset_in_prog_check(
1023 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1024 if (status != VXGE_HW_OK)
1025 goto exit;
1026
1027 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1028
1029 val64 = readq(&common_reg->host_type_assignments);
1030
1031 hw_info->host_type =
1032 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1033
1034 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1035 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1036 continue;
1037
1038 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1039
1040 vpmgmt_reg = bar0 + val64;
1041
1042 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
1043 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1044 hw_info->func_id) &
1045 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1046
1047 val64 = readq(&toc->toc_mrpcim_pointer);
1048
1049 mrpcim_reg = bar0 + val64;
1050
1051 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1052 wmb();
1053 }
1054
1055 val64 = readq(&toc->toc_vpath_pointer[i]);
1056
1057 spin_lock_init(&vpath.lock);
1058 vpath.vp_reg = bar0 + val64;
1059 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1060
1061 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1062 if (status != VXGE_HW_OK)
1063 goto exit;
1064
1065 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
1066 if (status != VXGE_HW_OK)
1067 goto exit;
1068
1069 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
1070 if (status != VXGE_HW_OK)
1071 goto exit;
1072
1073 break;
1074 }
1075
1076 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1077 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1078 continue;
1079
1080 val64 = readq(&toc->toc_vpath_pointer[i]);
1081 vpath.vp_reg = bar0 + val64;
1082 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1083
1084 status = __vxge_hw_vpath_addr_get(&vpath,
1085 hw_info->mac_addrs[i],
1086 hw_info->mac_addr_masks[i]);
1087 if (status != VXGE_HW_OK)
1088 goto exit;
1089 }
1090 exit:
1091 return status;
1092 }
1093
1094 /*
1095 * __vxge_hw_blockpool_destroy - Deallocates the block pool
1096 */
1097 static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1098 {
1099 struct __vxge_hw_device *hldev;
1100 struct list_head *p, *n;
1101
1102 if (!blockpool)
1103 return;
1104
1105 hldev = blockpool->hldev;
1106
1107 list_for_each_safe(p, n, &blockpool->free_block_list) {
1108 dma_unmap_single(&hldev->pdev->dev,
1109 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1110 ((struct __vxge_hw_blockpool_entry *)p)->length,
1111 DMA_BIDIRECTIONAL);
1112
1113 vxge_os_dma_free(hldev->pdev,
1114 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1115 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1116
1117 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1118 kfree(p);
1119 blockpool->pool_size--;
1120 }
1121
1122 list_for_each_safe(p, n, &blockpool->free_entry_list) {
1123 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1124 kfree(p);
1125 }
1126
1127 return;
1128 }
1129
1130 /*
1131 * __vxge_hw_blockpool_create - Create block pool
1132 */
1133 static enum vxge_hw_status
1134 __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1135 struct __vxge_hw_blockpool *blockpool,
1136 u32 pool_size,
1137 u32 pool_max)
1138 {
1139 u32 i;
1140 struct __vxge_hw_blockpool_entry *entry = NULL;
1141 void *memblock;
1142 dma_addr_t dma_addr;
1143 struct pci_dev *dma_handle;
1144 struct pci_dev *acc_handle;
1145 enum vxge_hw_status status = VXGE_HW_OK;
1146
1147 if (blockpool == NULL) {
1148 status = VXGE_HW_FAIL;
1149 goto blockpool_create_exit;
1150 }
1151
1152 blockpool->hldev = hldev;
1153 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1154 blockpool->pool_size = 0;
1155 blockpool->pool_max = pool_max;
1156 blockpool->req_out = 0;
1157
1158 INIT_LIST_HEAD(&blockpool->free_block_list);
1159 INIT_LIST_HEAD(&blockpool->free_entry_list);
1160
1161 for (i = 0; i < pool_size + pool_max; i++) {
1162 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1163 GFP_KERNEL);
1164 if (entry == NULL) {
1165 __vxge_hw_blockpool_destroy(blockpool);
1166 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1167 goto blockpool_create_exit;
1168 }
1169 list_add(&entry->item, &blockpool->free_entry_list);
1170 }
1171
1172 for (i = 0; i < pool_size; i++) {
1173 memblock = vxge_os_dma_malloc(
1174 hldev->pdev,
1175 VXGE_HW_BLOCK_SIZE,
1176 &dma_handle,
1177 &acc_handle);
1178 if (memblock == NULL) {
1179 __vxge_hw_blockpool_destroy(blockpool);
1180 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1181 goto blockpool_create_exit;
1182 }
1183
1184 dma_addr = dma_map_single(&hldev->pdev->dev, memblock,
1185 VXGE_HW_BLOCK_SIZE,
1186 DMA_BIDIRECTIONAL);
1187 if (unlikely(dma_mapping_error(&hldev->pdev->dev, dma_addr))) {
1188 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1189 __vxge_hw_blockpool_destroy(blockpool);
1190 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1191 goto blockpool_create_exit;
1192 }
1193
1194 if (!list_empty(&blockpool->free_entry_list))
1195 entry = (struct __vxge_hw_blockpool_entry *)
1196 list_first_entry(&blockpool->free_entry_list,
1197 struct __vxge_hw_blockpool_entry,
1198 item);
1199
1200 if (entry == NULL)
1201 entry =
1202 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1203 GFP_KERNEL);
1204 if (entry != NULL) {
1205 list_del(&entry->item);
1206 entry->length = VXGE_HW_BLOCK_SIZE;
1207 entry->memblock = memblock;
1208 entry->dma_addr = dma_addr;
1209 entry->acc_handle = acc_handle;
1210 entry->dma_handle = dma_handle;
1211 list_add(&entry->item,
1212 &blockpool->free_block_list);
1213 blockpool->pool_size++;
1214 } else {
1215 __vxge_hw_blockpool_destroy(blockpool);
1216 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1217 goto blockpool_create_exit;
1218 }
1219 }
1220
1221 blockpool_create_exit:
1222 return status;
1223 }
1224
1225 /*
1226 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1227 * Check the fifo configuration
1228 */
1229 static enum vxge_hw_status
1230 __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1231 {
1232 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1233 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1234 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1235
1236 return VXGE_HW_OK;
1237 }
1238
1239 /*
1240 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1241 * Check the vpath configuration
1242 */
1243 static enum vxge_hw_status
1244 __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1245 {
1246 enum vxge_hw_status status;
1247
1248 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1249 (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1250 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1251
1252 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1253 if (status != VXGE_HW_OK)
1254 return status;
1255
1256 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1257 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1258 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1259 return VXGE_HW_BADCFG_VPATH_MTU;
1260
1261 if ((vp_config->rpa_strip_vlan_tag !=
1262 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1263 (vp_config->rpa_strip_vlan_tag !=
1264 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1265 (vp_config->rpa_strip_vlan_tag !=
1266 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1267 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1268
1269 return VXGE_HW_OK;
1270 }
1271
1272 /*
1273 * __vxge_hw_device_config_check - Check device configuration.
1274 * Check the device configuration
1275 */
1276 static enum vxge_hw_status
1277 __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1278 {
1279 u32 i;
1280 enum vxge_hw_status status;
1281
1282 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1283 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1284 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1285 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1286 return VXGE_HW_BADCFG_INTR_MODE;
1287
1288 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1289 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1290 return VXGE_HW_BADCFG_RTS_MAC_EN;
1291
1292 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1293 status = __vxge_hw_device_vpath_config_check(
1294 &new_config->vp_config[i]);
1295 if (status != VXGE_HW_OK)
1296 return status;
1297 }
1298
1299 return VXGE_HW_OK;
1300 }
1301
1302 /*
1303 * vxge_hw_device_initialize - Initialize Titan device.
1304 * Initialize Titan device. Note that all the arguments of this public API
1305 * are 'IN', including @hldev. Driver cooperates with
1306 * OS to find new Titan device, locate its PCI and memory spaces.
1307 *
1308 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1309 * to enable the latter to perform Titan hardware initialization.
1310 */
1311 enum vxge_hw_status
1312 vxge_hw_device_initialize(
1313 struct __vxge_hw_device **devh,
1314 struct vxge_hw_device_attr *attr,
1315 struct vxge_hw_device_config *device_config)
1316 {
1317 u32 i;
1318 u32 nblocks = 0;
1319 struct __vxge_hw_device *hldev = NULL;
1320 enum vxge_hw_status status = VXGE_HW_OK;
1321
1322 status = __vxge_hw_device_config_check(device_config);
1323 if (status != VXGE_HW_OK)
1324 goto exit;
1325
1326 hldev = vzalloc(sizeof(struct __vxge_hw_device));
1327 if (hldev == NULL) {
1328 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1329 goto exit;
1330 }
1331
1332 hldev->magic = VXGE_HW_DEVICE_MAGIC;
1333
1334 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1335
1336 /* apply config */
1337 memcpy(&hldev->config, device_config,
1338 sizeof(struct vxge_hw_device_config));
1339
1340 hldev->bar0 = attr->bar0;
1341 hldev->pdev = attr->pdev;
1342
1343 hldev->uld_callbacks = attr->uld_callbacks;
1344
1345 __vxge_hw_device_pci_e_init(hldev);
1346
1347 status = __vxge_hw_device_reg_addr_get(hldev);
1348 if (status != VXGE_HW_OK) {
1349 vfree(hldev);
1350 goto exit;
1351 }
1352
1353 __vxge_hw_device_host_info_get(hldev);
1354
1355 /* Incrementing for stats blocks */
1356 nblocks++;
1357
1358 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1359 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1360 continue;
1361
1362 if (device_config->vp_config[i].ring.enable ==
1363 VXGE_HW_RING_ENABLE)
1364 nblocks += device_config->vp_config[i].ring.ring_blocks;
1365
1366 if (device_config->vp_config[i].fifo.enable ==
1367 VXGE_HW_FIFO_ENABLE)
1368 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1369 nblocks++;
1370 }
1371
1372 if (__vxge_hw_blockpool_create(hldev,
1373 &hldev->block_pool,
1374 device_config->dma_blockpool_initial + nblocks,
1375 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1376
1377 vxge_hw_device_terminate(hldev);
1378 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1379 goto exit;
1380 }
1381
1382 status = __vxge_hw_device_initialize(hldev);
1383 if (status != VXGE_HW_OK) {
1384 vxge_hw_device_terminate(hldev);
1385 goto exit;
1386 }
1387
1388 *devh = hldev;
1389 exit:
1390 return status;
1391 }
1392
1393 /*
1394 * vxge_hw_device_terminate - Terminate Titan device.
1395 * Terminate HW device.
1396 */
1397 void
1398 vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1399 {
1400 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1401
1402 hldev->magic = VXGE_HW_DEVICE_DEAD;
1403 __vxge_hw_blockpool_destroy(&hldev->block_pool);
1404 vfree(hldev);
1405 }
1406
1407 /*
1408 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1409 * and offset and perform an operation
1410 */
1411 static enum vxge_hw_status
1412 __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1413 u32 operation, u32 offset, u64 *stat)
1414 {
1415 u64 val64;
1416 enum vxge_hw_status status = VXGE_HW_OK;
1417 struct vxge_hw_vpath_reg __iomem *vp_reg;
1418
1419 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1420 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1421 goto vpath_stats_access_exit;
1422 }
1423
1424 vp_reg = vpath->vp_reg;
1425
1426 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1427 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1428 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
1429
1430 status = __vxge_hw_pio_mem_write64(val64,
1431 &vp_reg->xmac_stats_access_cmd,
1432 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1433 vpath->hldev->config.device_poll_millis);
1434 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1435 *stat = readq(&vp_reg->xmac_stats_access_data);
1436 else
1437 *stat = 0;
1438
1439 vpath_stats_access_exit:
1440 return status;
1441 }
1442
1443 /*
1444 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1445 */
1446 static enum vxge_hw_status
1447 __vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1448 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1449 {
1450 u64 *val64;
1451 int i;
1452 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1453 enum vxge_hw_status status = VXGE_HW_OK;
1454
1455 val64 = (u64 *)vpath_tx_stats;
1456
1457 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1458 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1459 goto exit;
1460 }
1461
1462 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1463 status = __vxge_hw_vpath_stats_access(vpath,
1464 VXGE_HW_STATS_OP_READ,
1465 offset, val64);
1466 if (status != VXGE_HW_OK)
1467 goto exit;
1468 offset++;
1469 val64++;
1470 }
1471 exit:
1472 return status;
1473 }
1474
1475 /*
1476 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1477 */
1478 static enum vxge_hw_status
1479 __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1480 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1481 {
1482 u64 *val64;
1483 enum vxge_hw_status status = VXGE_HW_OK;
1484 int i;
1485 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1486 val64 = (u64 *) vpath_rx_stats;
1487
1488 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1489 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1490 goto exit;
1491 }
1492 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1493 status = __vxge_hw_vpath_stats_access(vpath,
1494 VXGE_HW_STATS_OP_READ,
1495 offset >> 3, val64);
1496 if (status != VXGE_HW_OK)
1497 goto exit;
1498
1499 offset += 8;
1500 val64++;
1501 }
1502 exit:
1503 return status;
1504 }
1505
1506 /*
1507 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1508 */
1509 static enum vxge_hw_status
1510 __vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1511 struct vxge_hw_vpath_stats_hw_info *hw_stats)
1512 {
1513 u64 val64;
1514 enum vxge_hw_status status = VXGE_HW_OK;
1515 struct vxge_hw_vpath_reg __iomem *vp_reg;
1516
1517 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1518 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1519 goto exit;
1520 }
1521 vp_reg = vpath->vp_reg;
1522
1523 val64 = readq(&vp_reg->vpath_debug_stats0);
1524 hw_stats->ini_num_mwr_sent =
1525 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1526
1527 val64 = readq(&vp_reg->vpath_debug_stats1);
1528 hw_stats->ini_num_mrd_sent =
1529 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1530
1531 val64 = readq(&vp_reg->vpath_debug_stats2);
1532 hw_stats->ini_num_cpl_rcvd =
1533 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1534
1535 val64 = readq(&vp_reg->vpath_debug_stats3);
1536 hw_stats->ini_num_mwr_byte_sent =
1537 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1538
1539 val64 = readq(&vp_reg->vpath_debug_stats4);
1540 hw_stats->ini_num_cpl_byte_rcvd =
1541 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1542
1543 val64 = readq(&vp_reg->vpath_debug_stats5);
1544 hw_stats->wrcrdtarb_xoff =
1545 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1546
1547 val64 = readq(&vp_reg->vpath_debug_stats6);
1548 hw_stats->rdcrdtarb_xoff =
1549 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1550
1551 val64 = readq(&vp_reg->vpath_genstats_count01);
1552 hw_stats->vpath_genstats_count0 =
1553 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1554 val64);
1555
1556 val64 = readq(&vp_reg->vpath_genstats_count01);
1557 hw_stats->vpath_genstats_count1 =
1558 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1559 val64);
1560
1561 val64 = readq(&vp_reg->vpath_genstats_count23);
1562 hw_stats->vpath_genstats_count2 =
1563 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1564 val64);
1565
1566 val64 = readq(&vp_reg->vpath_genstats_count01);
1567 hw_stats->vpath_genstats_count3 =
1568 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1569 val64);
1570
1571 val64 = readq(&vp_reg->vpath_genstats_count4);
1572 hw_stats->vpath_genstats_count4 =
1573 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1574 val64);
1575
1576 val64 = readq(&vp_reg->vpath_genstats_count5);
1577 hw_stats->vpath_genstats_count5 =
1578 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1579 val64);
1580
1581 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1582 if (status != VXGE_HW_OK)
1583 goto exit;
1584
1585 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1586 if (status != VXGE_HW_OK)
1587 goto exit;
1588
1589 VXGE_HW_VPATH_STATS_PIO_READ(
1590 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1591
1592 hw_stats->prog_event_vnum0 =
1593 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1594
1595 hw_stats->prog_event_vnum1 =
1596 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1597
1598 VXGE_HW_VPATH_STATS_PIO_READ(
1599 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1600
1601 hw_stats->prog_event_vnum2 =
1602 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1603
1604 hw_stats->prog_event_vnum3 =
1605 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1606
1607 val64 = readq(&vp_reg->rx_multi_cast_stats);
1608 hw_stats->rx_multi_cast_frame_discard =
1609 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1610
1611 val64 = readq(&vp_reg->rx_frm_transferred);
1612 hw_stats->rx_frm_transferred =
1613 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1614
1615 val64 = readq(&vp_reg->rxd_returned);
1616 hw_stats->rxd_returned =
1617 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1618
1619 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1620 hw_stats->rx_mpa_len_fail_frms =
1621 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1622 hw_stats->rx_mpa_mrk_fail_frms =
1623 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1624 hw_stats->rx_mpa_crc_fail_frms =
1625 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1626
1627 val64 = readq(&vp_reg->dbg_stats_rx_fau);
1628 hw_stats->rx_permitted_frms =
1629 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1630 hw_stats->rx_vp_reset_discarded_frms =
1631 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1632 hw_stats->rx_wol_frms =
1633 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1634
1635 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1636 hw_stats->tx_vp_reset_discarded_frms =
1637 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1638 val64);
1639 exit:
1640 return status;
1641 }
1642
1643 /*
1644 * vxge_hw_device_stats_get - Get the device hw statistics.
1645 * Returns the vpath h/w stats for the device.
1646 */
1647 enum vxge_hw_status
1648 vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1649 struct vxge_hw_device_stats_hw_info *hw_stats)
1650 {
1651 u32 i;
1652 enum vxge_hw_status status = VXGE_HW_OK;
1653
1654 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1655 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1656 (hldev->virtual_paths[i].vp_open ==
1657 VXGE_HW_VP_NOT_OPEN))
1658 continue;
1659
1660 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1661 hldev->virtual_paths[i].hw_stats,
1662 sizeof(struct vxge_hw_vpath_stats_hw_info));
1663
1664 status = __vxge_hw_vpath_stats_get(
1665 &hldev->virtual_paths[i],
1666 hldev->virtual_paths[i].hw_stats);
1667 }
1668
1669 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1670 sizeof(struct vxge_hw_device_stats_hw_info));
1671
1672 return status;
1673 }
1674
1675 /*
1676 * vxge_hw_driver_stats_get - Get the device sw statistics.
1677 * Returns the vpath s/w stats for the device.
1678 */
1679 enum vxge_hw_status vxge_hw_driver_stats_get(
1680 struct __vxge_hw_device *hldev,
1681 struct vxge_hw_device_stats_sw_info *sw_stats)
1682 {
1683 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1684 sizeof(struct vxge_hw_device_stats_sw_info));
1685
1686 return VXGE_HW_OK;
1687 }
1688
1689 /*
1690 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1691 * and offset and perform an operation
1692 * Get the statistics from the given location and offset.
1693 */
1694 enum vxge_hw_status
1695 vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1696 u32 operation, u32 location, u32 offset, u64 *stat)
1697 {
1698 u64 val64;
1699 enum vxge_hw_status status = VXGE_HW_OK;
1700
1701 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1702 hldev->func_id);
1703 if (status != VXGE_HW_OK)
1704 goto exit;
1705
1706 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1707 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1708 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1709 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1710
1711 status = __vxge_hw_pio_mem_write64(val64,
1712 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1713 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1714 hldev->config.device_poll_millis);
1715
1716 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1717 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1718 else
1719 *stat = 0;
1720 exit:
1721 return status;
1722 }
1723
1724 /*
1725 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1726 * Get the Statistics on aggregate port
1727 */
1728 static enum vxge_hw_status
1729 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1730 struct vxge_hw_xmac_aggr_stats *aggr_stats)
1731 {
1732 u64 *val64;
1733 int i;
1734 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1735 enum vxge_hw_status status = VXGE_HW_OK;
1736
1737 val64 = (u64 *)aggr_stats;
1738
1739 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1740 hldev->func_id);
1741 if (status != VXGE_HW_OK)
1742 goto exit;
1743
1744 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1745 status = vxge_hw_mrpcim_stats_access(hldev,
1746 VXGE_HW_STATS_OP_READ,
1747 VXGE_HW_STATS_LOC_AGGR,
1748 ((offset + (104 * port)) >> 3), val64);
1749 if (status != VXGE_HW_OK)
1750 goto exit;
1751
1752 offset += 8;
1753 val64++;
1754 }
1755 exit:
1756 return status;
1757 }
1758
1759 /*
1760 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1761 * Get the Statistics on port
1762 */
1763 static enum vxge_hw_status
1764 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1765 struct vxge_hw_xmac_port_stats *port_stats)
1766 {
1767 u64 *val64;
1768 enum vxge_hw_status status = VXGE_HW_OK;
1769 int i;
1770 u32 offset = 0x0;
1771 val64 = (u64 *) port_stats;
1772
1773 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1774 hldev->func_id);
1775 if (status != VXGE_HW_OK)
1776 goto exit;
1777
1778 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1779 status = vxge_hw_mrpcim_stats_access(hldev,
1780 VXGE_HW_STATS_OP_READ,
1781 VXGE_HW_STATS_LOC_AGGR,
1782 ((offset + (608 * port)) >> 3), val64);
1783 if (status != VXGE_HW_OK)
1784 goto exit;
1785
1786 offset += 8;
1787 val64++;
1788 }
1789
1790 exit:
1791 return status;
1792 }
1793
1794 /*
1795 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1796 * Get the XMAC Statistics
1797 */
1798 enum vxge_hw_status
1799 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1800 struct vxge_hw_xmac_stats *xmac_stats)
1801 {
1802 enum vxge_hw_status status = VXGE_HW_OK;
1803 u32 i;
1804
1805 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1806 0, &xmac_stats->aggr_stats[0]);
1807 if (status != VXGE_HW_OK)
1808 goto exit;
1809
1810 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1811 1, &xmac_stats->aggr_stats[1]);
1812 if (status != VXGE_HW_OK)
1813 goto exit;
1814
1815 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1816
1817 status = vxge_hw_device_xmac_port_stats_get(hldev,
1818 i, &xmac_stats->port_stats[i]);
1819 if (status != VXGE_HW_OK)
1820 goto exit;
1821 }
1822
1823 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1824
1825 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1826 continue;
1827
1828 status = __vxge_hw_vpath_xmac_tx_stats_get(
1829 &hldev->virtual_paths[i],
1830 &xmac_stats->vpath_tx_stats[i]);
1831 if (status != VXGE_HW_OK)
1832 goto exit;
1833
1834 status = __vxge_hw_vpath_xmac_rx_stats_get(
1835 &hldev->virtual_paths[i],
1836 &xmac_stats->vpath_rx_stats[i]);
1837 if (status != VXGE_HW_OK)
1838 goto exit;
1839 }
1840 exit:
1841 return status;
1842 }
1843
1844 /*
1845 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1846 * This routine is used to dynamically change the debug output
1847 */
1848 void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1849 enum vxge_debug_level level, u32 mask)
1850 {
1851 if (hldev == NULL)
1852 return;
1853
1854 #if defined(VXGE_DEBUG_TRACE_MASK) || \
1855 defined(VXGE_DEBUG_ERR_MASK)
1856 hldev->debug_module_mask = mask;
1857 hldev->debug_level = level;
1858 #endif
1859
1860 #if defined(VXGE_DEBUG_ERR_MASK)
1861 hldev->level_err = level & VXGE_ERR;
1862 #endif
1863
1864 #if defined(VXGE_DEBUG_TRACE_MASK)
1865 hldev->level_trace = level & VXGE_TRACE;
1866 #endif
1867 }
1868
1869 /*
1870 * vxge_hw_device_error_level_get - Get the error level
1871 * This routine returns the current error level set
1872 */
1873 u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1874 {
1875 #if defined(VXGE_DEBUG_ERR_MASK)
1876 if (hldev == NULL)
1877 return VXGE_ERR;
1878 else
1879 return hldev->level_err;
1880 #else
1881 return 0;
1882 #endif
1883 }
1884
1885 /*
1886 * vxge_hw_device_trace_level_get - Get the trace level
1887 * This routine returns the current trace level set
1888 */
1889 u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1890 {
1891 #if defined(VXGE_DEBUG_TRACE_MASK)
1892 if (hldev == NULL)
1893 return VXGE_TRACE;
1894 else
1895 return hldev->level_trace;
1896 #else
1897 return 0;
1898 #endif
1899 }
1900
1901 /*
1902 * vxge_hw_getpause_data -Pause frame frame generation and reception.
1903 * Returns the Pause frame generation and reception capability of the NIC.
1904 */
1905 enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1906 u32 port, u32 *tx, u32 *rx)
1907 {
1908 u64 val64;
1909 enum vxge_hw_status status = VXGE_HW_OK;
1910
1911 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1912 status = VXGE_HW_ERR_INVALID_DEVICE;
1913 goto exit;
1914 }
1915
1916 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1917 status = VXGE_HW_ERR_INVALID_PORT;
1918 goto exit;
1919 }
1920
1921 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1922 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
1923 goto exit;
1924 }
1925
1926 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1927 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1928 *tx = 1;
1929 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1930 *rx = 1;
1931 exit:
1932 return status;
1933 }
1934
1935 /*
1936 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1937 * It can be used to set or reset Pause frame generation or reception
1938 * support of the NIC.
1939 */
1940 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1941 u32 port, u32 tx, u32 rx)
1942 {
1943 u64 val64;
1944 enum vxge_hw_status status = VXGE_HW_OK;
1945
1946 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1947 status = VXGE_HW_ERR_INVALID_DEVICE;
1948 goto exit;
1949 }
1950
1951 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1952 status = VXGE_HW_ERR_INVALID_PORT;
1953 goto exit;
1954 }
1955
1956 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1957 hldev->func_id);
1958 if (status != VXGE_HW_OK)
1959 goto exit;
1960
1961 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1962 if (tx)
1963 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1964 else
1965 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1966 if (rx)
1967 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1968 else
1969 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1970
1971 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1972 exit:
1973 return status;
1974 }
1975
1976 u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1977 {
1978 struct pci_dev *dev = hldev->pdev;
1979 u16 lnk;
1980
1981 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
1982 return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1983 }
1984
1985 /*
1986 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1987 * This function returns the index of memory block
1988 */
1989 static inline u32
1990 __vxge_hw_ring_block_memblock_idx(u8 *block)
1991 {
1992 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1993 }
1994
1995 /*
1996 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1997 * This function sets index to a memory block
1998 */
1999 static inline void
2000 __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
2001 {
2002 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
2003 }
2004
2005 /*
2006 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2007 * in RxD block
2008 * Sets the next block pointer in RxD block
2009 */
2010 static inline void
2011 __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2012 {
2013 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2014 }
2015
2016 /*
2017 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2018 * first block
2019 * Returns the dma address of the first RxD block
2020 */
2021 static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
2022 {
2023 struct vxge_hw_mempool_dma *dma_object;
2024
2025 dma_object = ring->mempool->memblocks_dma_arr;
2026 vxge_assert(dma_object != NULL);
2027
2028 return dma_object->addr;
2029 }
2030
2031 /*
2032 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2033 * This function returns the dma address of a given item
2034 */
2035 static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2036 void *item)
2037 {
2038 u32 memblock_idx;
2039 void *memblock;
2040 struct vxge_hw_mempool_dma *memblock_dma_object;
2041 ptrdiff_t dma_item_offset;
2042
2043 /* get owner memblock index */
2044 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2045
2046 /* get owner memblock by memblock index */
2047 memblock = mempoolh->memblocks_arr[memblock_idx];
2048
2049 /* get memblock DMA object by memblock index */
2050 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2051
2052 /* calculate offset in the memblock of this item */
2053 dma_item_offset = (u8 *)item - (u8 *)memblock;
2054
2055 return memblock_dma_object->addr + dma_item_offset;
2056 }
2057
2058 /*
2059 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2060 * This function returns the dma address of a given item
2061 */
2062 static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2063 struct __vxge_hw_ring *ring, u32 from,
2064 u32 to)
2065 {
2066 u8 *to_item , *from_item;
2067 dma_addr_t to_dma;
2068
2069 /* get "from" RxD block */
2070 from_item = mempoolh->items_arr[from];
2071 vxge_assert(from_item);
2072
2073 /* get "to" RxD block */
2074 to_item = mempoolh->items_arr[to];
2075 vxge_assert(to_item);
2076
2077 /* return address of the beginning of previous RxD block */
2078 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2079
2080 /* set next pointer for this RxD block to point on
2081 * previous item's DMA start address */
2082 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2083 }
2084
2085 /*
2086 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2087 * block callback
2088 * This function is callback passed to __vxge_hw_mempool_create to create memory
2089 * pool for RxD block
2090 */
2091 static void
2092 __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2093 u32 memblock_index,
2094 struct vxge_hw_mempool_dma *dma_object,
2095 u32 index, u32 is_last)
2096 {
2097 u32 i;
2098 void *item = mempoolh->items_arr[index];
2099 struct __vxge_hw_ring *ring =
2100 (struct __vxge_hw_ring *)mempoolh->userdata;
2101
2102 /* format rxds array */
2103 for (i = 0; i < ring->rxds_per_block; i++) {
2104 void *rxdblock_priv;
2105 void *uld_priv;
2106 struct vxge_hw_ring_rxd_1 *rxdp;
2107
2108 u32 reserve_index = ring->channel.reserve_ptr -
2109 (index * ring->rxds_per_block + i + 1);
2110 u32 memblock_item_idx;
2111
2112 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2113 i * ring->rxd_size;
2114
2115 /* Note: memblock_item_idx is index of the item within
2116 * the memblock. For instance, in case of three RxD-blocks
2117 * per memblock this value can be 0, 1 or 2. */
2118 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2119 memblock_index, item,
2120 &memblock_item_idx);
2121
2122 rxdp = ring->channel.reserve_arr[reserve_index];
2123
2124 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2125
2126 /* pre-format Host_Control */
2127 rxdp->host_control = (u64)(size_t)uld_priv;
2128 }
2129
2130 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2131
2132 if (is_last) {
2133 /* link last one with first one */
2134 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2135 }
2136
2137 if (index > 0) {
2138 /* link this RxD block with previous one */
2139 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2140 }
2141 }
2142
2143 /*
2144 * __vxge_hw_ring_replenish - Initial replenish of RxDs
2145 * This function replenishes the RxDs from reserve array to work array
2146 */
2147 static enum vxge_hw_status
2148 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
2149 {
2150 void *rxd;
2151 struct __vxge_hw_channel *channel;
2152 enum vxge_hw_status status = VXGE_HW_OK;
2153
2154 channel = &ring->channel;
2155
2156 while (vxge_hw_channel_dtr_count(channel) > 0) {
2157
2158 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2159
2160 vxge_assert(status == VXGE_HW_OK);
2161
2162 if (ring->rxd_init) {
2163 status = ring->rxd_init(rxd, channel->userdata);
2164 if (status != VXGE_HW_OK) {
2165 vxge_hw_ring_rxd_free(ring, rxd);
2166 goto exit;
2167 }
2168 }
2169
2170 vxge_hw_ring_rxd_post(ring, rxd);
2171 }
2172 status = VXGE_HW_OK;
2173 exit:
2174 return status;
2175 }
2176
2177 /*
2178 * __vxge_hw_channel_allocate - Allocate memory for channel
2179 * This function allocates required memory for the channel and various arrays
2180 * in the channel
2181 */
2182 static struct __vxge_hw_channel *
2183 __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2184 enum __vxge_hw_channel_type type,
2185 u32 length, u32 per_dtr_space,
2186 void *userdata)
2187 {
2188 struct __vxge_hw_channel *channel;
2189 struct __vxge_hw_device *hldev;
2190 int size = 0;
2191 u32 vp_id;
2192
2193 hldev = vph->vpath->hldev;
2194 vp_id = vph->vpath->vp_id;
2195
2196 switch (type) {
2197 case VXGE_HW_CHANNEL_TYPE_FIFO:
2198 size = sizeof(struct __vxge_hw_fifo);
2199 break;
2200 case VXGE_HW_CHANNEL_TYPE_RING:
2201 size = sizeof(struct __vxge_hw_ring);
2202 break;
2203 default:
2204 break;
2205 }
2206
2207 channel = kzalloc(size, GFP_KERNEL);
2208 if (channel == NULL)
2209 goto exit0;
2210 INIT_LIST_HEAD(&channel->item);
2211
2212 channel->common_reg = hldev->common_reg;
2213 channel->first_vp_id = hldev->first_vp_id;
2214 channel->type = type;
2215 channel->devh = hldev;
2216 channel->vph = vph;
2217 channel->userdata = userdata;
2218 channel->per_dtr_space = per_dtr_space;
2219 channel->length = length;
2220 channel->vp_id = vp_id;
2221
2222 channel->work_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2223 if (channel->work_arr == NULL)
2224 goto exit1;
2225
2226 channel->free_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2227 if (channel->free_arr == NULL)
2228 goto exit1;
2229 channel->free_ptr = length;
2230
2231 channel->reserve_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2232 if (channel->reserve_arr == NULL)
2233 goto exit1;
2234 channel->reserve_ptr = length;
2235 channel->reserve_top = 0;
2236
2237 channel->orig_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2238 if (channel->orig_arr == NULL)
2239 goto exit1;
2240
2241 return channel;
2242 exit1:
2243 __vxge_hw_channel_free(channel);
2244
2245 exit0:
2246 return NULL;
2247 }
2248
2249 /*
2250 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2251 * Adds a block to block pool
2252 */
2253 static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2254 void *block_addr,
2255 u32 length,
2256 struct pci_dev *dma_h,
2257 struct pci_dev *acc_handle)
2258 {
2259 struct __vxge_hw_blockpool *blockpool;
2260 struct __vxge_hw_blockpool_entry *entry = NULL;
2261 dma_addr_t dma_addr;
2262
2263 blockpool = &devh->block_pool;
2264
2265 if (block_addr == NULL) {
2266 blockpool->req_out--;
2267 goto exit;
2268 }
2269
2270 dma_addr = dma_map_single(&devh->pdev->dev, block_addr, length,
2271 DMA_BIDIRECTIONAL);
2272
2273 if (unlikely(dma_mapping_error(&devh->pdev->dev, dma_addr))) {
2274 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2275 blockpool->req_out--;
2276 goto exit;
2277 }
2278
2279 if (!list_empty(&blockpool->free_entry_list))
2280 entry = (struct __vxge_hw_blockpool_entry *)
2281 list_first_entry(&blockpool->free_entry_list,
2282 struct __vxge_hw_blockpool_entry,
2283 item);
2284
2285 if (entry == NULL)
2286 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2287 else
2288 list_del(&entry->item);
2289
2290 if (entry) {
2291 entry->length = length;
2292 entry->memblock = block_addr;
2293 entry->dma_addr = dma_addr;
2294 entry->acc_handle = acc_handle;
2295 entry->dma_handle = dma_h;
2296 list_add(&entry->item, &blockpool->free_block_list);
2297 blockpool->pool_size++;
2298 }
2299
2300 blockpool->req_out--;
2301
2302 exit:
2303 return;
2304 }
2305
2306 static inline void
2307 vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2308 {
2309 void *vaddr;
2310
2311 vaddr = kmalloc(size, GFP_KERNEL | GFP_DMA);
2312 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
2313 }
2314
2315 /*
2316 * __vxge_hw_blockpool_blocks_add - Request additional blocks
2317 */
2318 static
2319 void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
2320 {
2321 u32 nreq = 0, i;
2322
2323 if ((blockpool->pool_size + blockpool->req_out) <
2324 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2325 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2326 blockpool->req_out += nreq;
2327 }
2328
2329 for (i = 0; i < nreq; i++)
2330 vxge_os_dma_malloc_async(
2331 (blockpool->hldev)->pdev,
2332 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
2333 }
2334
2335 /*
2336 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2337 * Allocates a block of memory of given size, either from block pool
2338 * or by calling vxge_os_dma_malloc()
2339 */
2340 static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2341 struct vxge_hw_mempool_dma *dma_object)
2342 {
2343 struct __vxge_hw_blockpool_entry *entry = NULL;
2344 struct __vxge_hw_blockpool *blockpool;
2345 void *memblock = NULL;
2346
2347 blockpool = &devh->block_pool;
2348
2349 if (size != blockpool->block_size) {
2350
2351 memblock = vxge_os_dma_malloc(devh->pdev, size,
2352 &dma_object->handle,
2353 &dma_object->acc_handle);
2354
2355 if (!memblock)
2356 goto exit;
2357
2358 dma_object->addr = dma_map_single(&devh->pdev->dev, memblock,
2359 size, DMA_BIDIRECTIONAL);
2360
2361 if (unlikely(dma_mapping_error(&devh->pdev->dev, dma_object->addr))) {
2362 vxge_os_dma_free(devh->pdev, memblock,
2363 &dma_object->acc_handle);
2364 memblock = NULL;
2365 goto exit;
2366 }
2367
2368 } else {
2369
2370 if (!list_empty(&blockpool->free_block_list))
2371 entry = (struct __vxge_hw_blockpool_entry *)
2372 list_first_entry(&blockpool->free_block_list,
2373 struct __vxge_hw_blockpool_entry,
2374 item);
2375
2376 if (entry != NULL) {
2377 list_del(&entry->item);
2378 dma_object->addr = entry->dma_addr;
2379 dma_object->handle = entry->dma_handle;
2380 dma_object->acc_handle = entry->acc_handle;
2381 memblock = entry->memblock;
2382
2383 list_add(&entry->item,
2384 &blockpool->free_entry_list);
2385 blockpool->pool_size--;
2386 }
2387
2388 if (memblock != NULL)
2389 __vxge_hw_blockpool_blocks_add(blockpool);
2390 }
2391 exit:
2392 return memblock;
2393 }
2394
2395 /*
2396 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2397 */
2398 static void
2399 __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2400 {
2401 struct list_head *p, *n;
2402
2403 list_for_each_safe(p, n, &blockpool->free_block_list) {
2404
2405 if (blockpool->pool_size < blockpool->pool_max)
2406 break;
2407
2408 dma_unmap_single(&(blockpool->hldev)->pdev->dev,
2409 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2410 ((struct __vxge_hw_blockpool_entry *)p)->length,
2411 DMA_BIDIRECTIONAL);
2412
2413 vxge_os_dma_free(
2414 (blockpool->hldev)->pdev,
2415 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2416 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2417
2418 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2419
2420 list_add(p, &blockpool->free_entry_list);
2421
2422 blockpool->pool_size--;
2423
2424 }
2425 }
2426
2427 /*
2428 * __vxge_hw_blockpool_free - Frees the memory allcoated with
2429 * __vxge_hw_blockpool_malloc
2430 */
2431 static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2432 void *memblock, u32 size,
2433 struct vxge_hw_mempool_dma *dma_object)
2434 {
2435 struct __vxge_hw_blockpool_entry *entry = NULL;
2436 struct __vxge_hw_blockpool *blockpool;
2437 enum vxge_hw_status status = VXGE_HW_OK;
2438
2439 blockpool = &devh->block_pool;
2440
2441 if (size != blockpool->block_size) {
2442 dma_unmap_single(&devh->pdev->dev, dma_object->addr, size,
2443 DMA_BIDIRECTIONAL);
2444 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2445 } else {
2446
2447 if (!list_empty(&blockpool->free_entry_list))
2448 entry = (struct __vxge_hw_blockpool_entry *)
2449 list_first_entry(&blockpool->free_entry_list,
2450 struct __vxge_hw_blockpool_entry,
2451 item);
2452
2453 if (entry == NULL)
2454 entry = vmalloc(sizeof(
2455 struct __vxge_hw_blockpool_entry));
2456 else
2457 list_del(&entry->item);
2458
2459 if (entry != NULL) {
2460 entry->length = size;
2461 entry->memblock = memblock;
2462 entry->dma_addr = dma_object->addr;
2463 entry->acc_handle = dma_object->acc_handle;
2464 entry->dma_handle = dma_object->handle;
2465 list_add(&entry->item,
2466 &blockpool->free_block_list);
2467 blockpool->pool_size++;
2468 status = VXGE_HW_OK;
2469 } else
2470 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2471
2472 if (status == VXGE_HW_OK)
2473 __vxge_hw_blockpool_blocks_remove(blockpool);
2474 }
2475 }
2476
2477 /*
2478 * vxge_hw_mempool_destroy
2479 */
2480 static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2481 {
2482 u32 i, j;
2483 struct __vxge_hw_device *devh = mempool->devh;
2484
2485 for (i = 0; i < mempool->memblocks_allocated; i++) {
2486 struct vxge_hw_mempool_dma *dma_object;
2487
2488 vxge_assert(mempool->memblocks_arr[i]);
2489 vxge_assert(mempool->memblocks_dma_arr + i);
2490
2491 dma_object = mempool->memblocks_dma_arr + i;
2492
2493 for (j = 0; j < mempool->items_per_memblock; j++) {
2494 u32 index = i * mempool->items_per_memblock + j;
2495
2496 /* to skip last partially filled(if any) memblock */
2497 if (index >= mempool->items_current)
2498 break;
2499 }
2500
2501 vfree(mempool->memblocks_priv_arr[i]);
2502
2503 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2504 mempool->memblock_size, dma_object);
2505 }
2506
2507 vfree(mempool->items_arr);
2508 vfree(mempool->memblocks_dma_arr);
2509 vfree(mempool->memblocks_priv_arr);
2510 vfree(mempool->memblocks_arr);
2511 vfree(mempool);
2512 }
2513
2514 /*
2515 * __vxge_hw_mempool_grow
2516 * Will resize mempool up to %num_allocate value.
2517 */
2518 static enum vxge_hw_status
2519 __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2520 u32 *num_allocated)
2521 {
2522 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2523 u32 n_items = mempool->items_per_memblock;
2524 u32 start_block_idx = mempool->memblocks_allocated;
2525 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2526 enum vxge_hw_status status = VXGE_HW_OK;
2527
2528 *num_allocated = 0;
2529
2530 if (end_block_idx > mempool->memblocks_max) {
2531 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2532 goto exit;
2533 }
2534
2535 for (i = start_block_idx; i < end_block_idx; i++) {
2536 u32 j;
2537 u32 is_last = ((end_block_idx - 1) == i);
2538 struct vxge_hw_mempool_dma *dma_object =
2539 mempool->memblocks_dma_arr + i;
2540 void *the_memblock;
2541
2542 /* allocate memblock's private part. Each DMA memblock
2543 * has a space allocated for item's private usage upon
2544 * mempool's user request. Each time mempool grows, it will
2545 * allocate new memblock and its private part at once.
2546 * This helps to minimize memory usage a lot. */
2547 mempool->memblocks_priv_arr[i] =
2548 vzalloc(array_size(mempool->items_priv_size, n_items));
2549 if (mempool->memblocks_priv_arr[i] == NULL) {
2550 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2551 goto exit;
2552 }
2553
2554 /* allocate DMA-capable memblock */
2555 mempool->memblocks_arr[i] =
2556 __vxge_hw_blockpool_malloc(mempool->devh,
2557 mempool->memblock_size, dma_object);
2558 if (mempool->memblocks_arr[i] == NULL) {
2559 vfree(mempool->memblocks_priv_arr[i]);
2560 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2561 goto exit;
2562 }
2563
2564 (*num_allocated)++;
2565 mempool->memblocks_allocated++;
2566
2567 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2568
2569 the_memblock = mempool->memblocks_arr[i];
2570
2571 /* fill the items hash array */
2572 for (j = 0; j < n_items; j++) {
2573 u32 index = i * n_items + j;
2574
2575 if (first_time && index >= mempool->items_initial)
2576 break;
2577
2578 mempool->items_arr[index] =
2579 ((char *)the_memblock + j*mempool->item_size);
2580
2581 /* let caller to do more job on each item */
2582 if (mempool->item_func_alloc != NULL)
2583 mempool->item_func_alloc(mempool, i,
2584 dma_object, index, is_last);
2585
2586 mempool->items_current = index + 1;
2587 }
2588
2589 if (first_time && mempool->items_current ==
2590 mempool->items_initial)
2591 break;
2592 }
2593 exit:
2594 return status;
2595 }
2596
2597 /*
2598 * vxge_hw_mempool_create
2599 * This function will create memory pool object. Pool may grow but will
2600 * never shrink. Pool consists of number of dynamically allocated blocks
2601 * with size enough to hold %items_initial number of items. Memory is
2602 * DMA-able but client must map/unmap before interoperating with the device.
2603 */
2604 static struct vxge_hw_mempool *
2605 __vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2606 u32 memblock_size,
2607 u32 item_size,
2608 u32 items_priv_size,
2609 u32 items_initial,
2610 u32 items_max,
2611 const struct vxge_hw_mempool_cbs *mp_callback,
2612 void *userdata)
2613 {
2614 enum vxge_hw_status status = VXGE_HW_OK;
2615 u32 memblocks_to_allocate;
2616 struct vxge_hw_mempool *mempool = NULL;
2617 u32 allocated;
2618
2619 if (memblock_size < item_size) {
2620 status = VXGE_HW_FAIL;
2621 goto exit;
2622 }
2623
2624 mempool = vzalloc(sizeof(struct vxge_hw_mempool));
2625 if (mempool == NULL) {
2626 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2627 goto exit;
2628 }
2629
2630 mempool->devh = devh;
2631 mempool->memblock_size = memblock_size;
2632 mempool->items_max = items_max;
2633 mempool->items_initial = items_initial;
2634 mempool->item_size = item_size;
2635 mempool->items_priv_size = items_priv_size;
2636 mempool->item_func_alloc = mp_callback->item_func_alloc;
2637 mempool->userdata = userdata;
2638
2639 mempool->memblocks_allocated = 0;
2640
2641 mempool->items_per_memblock = memblock_size / item_size;
2642
2643 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2644 mempool->items_per_memblock;
2645
2646 /* allocate array of memblocks */
2647 mempool->memblocks_arr =
2648 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2649 if (mempool->memblocks_arr == NULL) {
2650 __vxge_hw_mempool_destroy(mempool);
2651 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2652 mempool = NULL;
2653 goto exit;
2654 }
2655
2656 /* allocate array of private parts of items per memblocks */
2657 mempool->memblocks_priv_arr =
2658 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2659 if (mempool->memblocks_priv_arr == NULL) {
2660 __vxge_hw_mempool_destroy(mempool);
2661 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2662 mempool = NULL;
2663 goto exit;
2664 }
2665
2666 /* allocate array of memblocks DMA objects */
2667 mempool->memblocks_dma_arr =
2668 vzalloc(array_size(sizeof(struct vxge_hw_mempool_dma),
2669 mempool->memblocks_max));
2670 if (mempool->memblocks_dma_arr == NULL) {
2671 __vxge_hw_mempool_destroy(mempool);
2672 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2673 mempool = NULL;
2674 goto exit;
2675 }
2676
2677 /* allocate hash array of items */
2678 mempool->items_arr = vzalloc(array_size(sizeof(void *),
2679 mempool->items_max));
2680 if (mempool->items_arr == NULL) {
2681 __vxge_hw_mempool_destroy(mempool);
2682 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2683 mempool = NULL;
2684 goto exit;
2685 }
2686
2687 /* calculate initial number of memblocks */
2688 memblocks_to_allocate = (mempool->items_initial +
2689 mempool->items_per_memblock - 1) /
2690 mempool->items_per_memblock;
2691
2692 /* pre-allocate the mempool */
2693 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2694 &allocated);
2695 if (status != VXGE_HW_OK) {
2696 __vxge_hw_mempool_destroy(mempool);
2697 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2698 mempool = NULL;
2699 goto exit;
2700 }
2701
2702 exit:
2703 return mempool;
2704 }
2705
2706 /*
2707 * __vxge_hw_ring_abort - Returns the RxD
2708 * This function terminates the RxDs of ring
2709 */
2710 static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
2711 {
2712 void *rxdh;
2713 struct __vxge_hw_channel *channel;
2714
2715 channel = &ring->channel;
2716
2717 for (;;) {
2718 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
2719
2720 if (rxdh == NULL)
2721 break;
2722
2723 vxge_hw_channel_dtr_complete(channel);
2724
2725 if (ring->rxd_term)
2726 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2727 channel->userdata);
2728
2729 vxge_hw_channel_dtr_free(channel, rxdh);
2730 }
2731
2732 return VXGE_HW_OK;
2733 }
2734
2735 /*
2736 * __vxge_hw_ring_reset - Resets the ring
2737 * This function resets the ring during vpath reset operation
2738 */
2739 static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2740 {
2741 enum vxge_hw_status status = VXGE_HW_OK;
2742 struct __vxge_hw_channel *channel;
2743
2744 channel = &ring->channel;
2745
2746 __vxge_hw_ring_abort(ring);
2747
2748 status = __vxge_hw_channel_reset(channel);
2749
2750 if (status != VXGE_HW_OK)
2751 goto exit;
2752
2753 if (ring->rxd_init) {
2754 status = vxge_hw_ring_replenish(ring);
2755 if (status != VXGE_HW_OK)
2756 goto exit;
2757 }
2758 exit:
2759 return status;
2760 }
2761
2762 /*
2763 * __vxge_hw_ring_delete - Removes the ring
2764 * This function freeup the memory pool and removes the ring
2765 */
2766 static enum vxge_hw_status
2767 __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
2768 {
2769 struct __vxge_hw_ring *ring = vp->vpath->ringh;
2770
2771 __vxge_hw_ring_abort(ring);
2772
2773 if (ring->mempool)
2774 __vxge_hw_mempool_destroy(ring->mempool);
2775
2776 vp->vpath->ringh = NULL;
2777 __vxge_hw_channel_free(&ring->channel);
2778
2779 return VXGE_HW_OK;
2780 }
2781
2782 /*
2783 * __vxge_hw_ring_create - Create a Ring
2784 * This function creates Ring and initializes it.
2785 */
2786 static enum vxge_hw_status
2787 __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2788 struct vxge_hw_ring_attr *attr)
2789 {
2790 enum vxge_hw_status status = VXGE_HW_OK;
2791 struct __vxge_hw_ring *ring;
2792 u32 ring_length;
2793 struct vxge_hw_ring_config *config;
2794 struct __vxge_hw_device *hldev;
2795 u32 vp_id;
2796 static const struct vxge_hw_mempool_cbs ring_mp_callback = {
2797 .item_func_alloc = __vxge_hw_ring_mempool_item_alloc,
2798 };
2799
2800 if ((vp == NULL) || (attr == NULL)) {
2801 status = VXGE_HW_FAIL;
2802 goto exit;
2803 }
2804
2805 hldev = vp->vpath->hldev;
2806 vp_id = vp->vpath->vp_id;
2807
2808 config = &hldev->config.vp_config[vp_id].ring;
2809
2810 ring_length = config->ring_blocks *
2811 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2812
2813 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2814 VXGE_HW_CHANNEL_TYPE_RING,
2815 ring_length,
2816 attr->per_rxd_space,
2817 attr->userdata);
2818 if (ring == NULL) {
2819 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2820 goto exit;
2821 }
2822
2823 vp->vpath->ringh = ring;
2824 ring->vp_id = vp_id;
2825 ring->vp_reg = vp->vpath->vp_reg;
2826 ring->common_reg = hldev->common_reg;
2827 ring->stats = &vp->vpath->sw_stats->ring_stats;
2828 ring->config = config;
2829 ring->callback = attr->callback;
2830 ring->rxd_init = attr->rxd_init;
2831 ring->rxd_term = attr->rxd_term;
2832 ring->buffer_mode = config->buffer_mode;
2833 ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2834 ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
2835 ring->rxds_limit = config->rxds_limit;
2836
2837 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2838 ring->rxd_priv_size =
2839 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2840 ring->per_rxd_space = attr->per_rxd_space;
2841
2842 ring->rxd_priv_size =
2843 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2844 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2845
2846 /* how many RxDs can fit into one block. Depends on configured
2847 * buffer_mode. */
2848 ring->rxds_per_block =
2849 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2850
2851 /* calculate actual RxD block private size */
2852 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
2853 ring->mempool = __vxge_hw_mempool_create(hldev,
2854 VXGE_HW_BLOCK_SIZE,
2855 VXGE_HW_BLOCK_SIZE,
2856 ring->rxdblock_priv_size,
2857 ring->config->ring_blocks,
2858 ring->config->ring_blocks,
2859 &ring_mp_callback,
2860 ring);
2861 if (ring->mempool == NULL) {
2862 __vxge_hw_ring_delete(vp);
2863 return VXGE_HW_ERR_OUT_OF_MEMORY;
2864 }
2865
2866 status = __vxge_hw_channel_initialize(&ring->channel);
2867 if (status != VXGE_HW_OK) {
2868 __vxge_hw_ring_delete(vp);
2869 goto exit;
2870 }
2871
2872 /* Note:
2873 * Specifying rxd_init callback means two things:
2874 * 1) rxds need to be initialized by driver at channel-open time;
2875 * 2) rxds need to be posted at channel-open time
2876 * (that's what the initial_replenish() below does)
2877 * Currently we don't have a case when the 1) is done without the 2).
2878 */
2879 if (ring->rxd_init) {
2880 status = vxge_hw_ring_replenish(ring);
2881 if (status != VXGE_HW_OK) {
2882 __vxge_hw_ring_delete(vp);
2883 goto exit;
2884 }
2885 }
2886
2887 /* initial replenish will increment the counter in its post() routine,
2888 * we have to reset it */
2889 ring->stats->common_stats.usage_cnt = 0;
2890 exit:
2891 return status;
2892 }
2893
2894 /*
2895 * vxge_hw_device_config_default_get - Initialize device config with defaults.
2896 * Initialize Titan device config with default values.
2897 */
2898 enum vxge_hw_status
2899 vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2900 {
2901 u32 i;
2902
2903 device_config->dma_blockpool_initial =
2904 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2905 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2906 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2907 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2908 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2909 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2910 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
2911
2912 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2913 device_config->vp_config[i].vp_id = i;
2914
2915 device_config->vp_config[i].min_bandwidth =
2916 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2917
2918 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2919
2920 device_config->vp_config[i].ring.ring_blocks =
2921 VXGE_HW_DEF_RING_BLOCKS;
2922
2923 device_config->vp_config[i].ring.buffer_mode =
2924 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2925
2926 device_config->vp_config[i].ring.scatter_mode =
2927 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2928
2929 device_config->vp_config[i].ring.rxds_limit =
2930 VXGE_HW_DEF_RING_RXDS_LIMIT;
2931
2932 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2933
2934 device_config->vp_config[i].fifo.fifo_blocks =
2935 VXGE_HW_MIN_FIFO_BLOCKS;
2936
2937 device_config->vp_config[i].fifo.max_frags =
2938 VXGE_HW_MAX_FIFO_FRAGS;
2939
2940 device_config->vp_config[i].fifo.memblock_size =
2941 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2942
2943 device_config->vp_config[i].fifo.alignment_size =
2944 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2945
2946 device_config->vp_config[i].fifo.intr =
2947 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2948
2949 device_config->vp_config[i].fifo.no_snoop_bits =
2950 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2951 device_config->vp_config[i].tti.intr_enable =
2952 VXGE_HW_TIM_INTR_DEFAULT;
2953
2954 device_config->vp_config[i].tti.btimer_val =
2955 VXGE_HW_USE_FLASH_DEFAULT;
2956
2957 device_config->vp_config[i].tti.timer_ac_en =
2958 VXGE_HW_USE_FLASH_DEFAULT;
2959
2960 device_config->vp_config[i].tti.timer_ci_en =
2961 VXGE_HW_USE_FLASH_DEFAULT;
2962
2963 device_config->vp_config[i].tti.timer_ri_en =
2964 VXGE_HW_USE_FLASH_DEFAULT;
2965
2966 device_config->vp_config[i].tti.rtimer_val =
2967 VXGE_HW_USE_FLASH_DEFAULT;
2968
2969 device_config->vp_config[i].tti.util_sel =
2970 VXGE_HW_USE_FLASH_DEFAULT;
2971
2972 device_config->vp_config[i].tti.ltimer_val =
2973 VXGE_HW_USE_FLASH_DEFAULT;
2974
2975 device_config->vp_config[i].tti.urange_a =
2976 VXGE_HW_USE_FLASH_DEFAULT;
2977
2978 device_config->vp_config[i].tti.uec_a =
2979 VXGE_HW_USE_FLASH_DEFAULT;
2980
2981 device_config->vp_config[i].tti.urange_b =
2982 VXGE_HW_USE_FLASH_DEFAULT;
2983
2984 device_config->vp_config[i].tti.uec_b =
2985 VXGE_HW_USE_FLASH_DEFAULT;
2986
2987 device_config->vp_config[i].tti.urange_c =
2988 VXGE_HW_USE_FLASH_DEFAULT;
2989
2990 device_config->vp_config[i].tti.uec_c =
2991 VXGE_HW_USE_FLASH_DEFAULT;
2992
2993 device_config->vp_config[i].tti.uec_d =
2994 VXGE_HW_USE_FLASH_DEFAULT;
2995
2996 device_config->vp_config[i].rti.intr_enable =
2997 VXGE_HW_TIM_INTR_DEFAULT;
2998
2999 device_config->vp_config[i].rti.btimer_val =
3000 VXGE_HW_USE_FLASH_DEFAULT;
3001
3002 device_config->vp_config[i].rti.timer_ac_en =
3003 VXGE_HW_USE_FLASH_DEFAULT;
3004
3005 device_config->vp_config[i].rti.timer_ci_en =
3006 VXGE_HW_USE_FLASH_DEFAULT;
3007
3008 device_config->vp_config[i].rti.timer_ri_en =
3009 VXGE_HW_USE_FLASH_DEFAULT;
3010
3011 device_config->vp_config[i].rti.rtimer_val =
3012 VXGE_HW_USE_FLASH_DEFAULT;
3013
3014 device_config->vp_config[i].rti.util_sel =
3015 VXGE_HW_USE_FLASH_DEFAULT;
3016
3017 device_config->vp_config[i].rti.ltimer_val =
3018 VXGE_HW_USE_FLASH_DEFAULT;
3019
3020 device_config->vp_config[i].rti.urange_a =
3021 VXGE_HW_USE_FLASH_DEFAULT;
3022
3023 device_config->vp_config[i].rti.uec_a =
3024 VXGE_HW_USE_FLASH_DEFAULT;
3025
3026 device_config->vp_config[i].rti.urange_b =
3027 VXGE_HW_USE_FLASH_DEFAULT;
3028
3029 device_config->vp_config[i].rti.uec_b =
3030 VXGE_HW_USE_FLASH_DEFAULT;
3031
3032 device_config->vp_config[i].rti.urange_c =
3033 VXGE_HW_USE_FLASH_DEFAULT;
3034
3035 device_config->vp_config[i].rti.uec_c =
3036 VXGE_HW_USE_FLASH_DEFAULT;
3037
3038 device_config->vp_config[i].rti.uec_d =
3039 VXGE_HW_USE_FLASH_DEFAULT;
3040
3041 device_config->vp_config[i].mtu =
3042 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3043
3044 device_config->vp_config[i].rpa_strip_vlan_tag =
3045 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3046 }
3047
3048 return VXGE_HW_OK;
3049 }
3050
3051 /*
3052 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3053 * Set the swapper bits appropriately for the vpath.
3054 */
3055 static enum vxge_hw_status
3056 __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3057 {
3058 #ifndef __BIG_ENDIAN
3059 u64 val64;
3060
3061 val64 = readq(&vpath_reg->vpath_general_cfg1);
3062 wmb();
3063 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3064 writeq(val64, &vpath_reg->vpath_general_cfg1);
3065 wmb();
3066 #endif
3067 return VXGE_HW_OK;
3068 }
3069
3070 /*
3071 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3072 * Set the swapper bits appropriately for the vpath.
3073 */
3074 static enum vxge_hw_status
3075 __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3076 struct vxge_hw_vpath_reg __iomem *vpath_reg)
3077 {
3078 u64 val64;
3079
3080 val64 = readq(&legacy_reg->pifm_wr_swap_en);
3081
3082 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3083 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3084 wmb();
3085
3086 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3087 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
3088 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3089
3090 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3091 wmb();
3092 }
3093
3094 return VXGE_HW_OK;
3095 }
3096
3097 /*
3098 * vxge_hw_mgmt_reg_read - Read Titan register.
3099 */
3100 enum vxge_hw_status
3101 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3102 enum vxge_hw_mgmt_reg_type type,
3103 u32 index, u32 offset, u64 *value)
3104 {
3105 enum vxge_hw_status status = VXGE_HW_OK;
3106
3107 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3108 status = VXGE_HW_ERR_INVALID_DEVICE;
3109 goto exit;
3110 }
3111
3112 switch (type) {
3113 case vxge_hw_mgmt_reg_type_legacy:
3114 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3115 status = VXGE_HW_ERR_INVALID_OFFSET;
3116 break;
3117 }
3118 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3119 break;
3120 case vxge_hw_mgmt_reg_type_toc:
3121 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3122 status = VXGE_HW_ERR_INVALID_OFFSET;
3123 break;
3124 }
3125 *value = readq((void __iomem *)hldev->toc_reg + offset);
3126 break;
3127 case vxge_hw_mgmt_reg_type_common:
3128 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3129 status = VXGE_HW_ERR_INVALID_OFFSET;
3130 break;
3131 }
3132 *value = readq((void __iomem *)hldev->common_reg + offset);
3133 break;
3134 case vxge_hw_mgmt_reg_type_mrpcim:
3135 if (!(hldev->access_rights &
3136 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3137 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3138 break;
3139 }
3140 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3141 status = VXGE_HW_ERR_INVALID_OFFSET;
3142 break;
3143 }
3144 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3145 break;
3146 case vxge_hw_mgmt_reg_type_srpcim:
3147 if (!(hldev->access_rights &
3148 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3149 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3150 break;
3151 }
3152 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3153 status = VXGE_HW_ERR_INVALID_INDEX;
3154 break;
3155 }
3156 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3157 status = VXGE_HW_ERR_INVALID_OFFSET;
3158 break;
3159 }
3160 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3161 offset);
3162 break;
3163 case vxge_hw_mgmt_reg_type_vpmgmt:
3164 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3165 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3166 status = VXGE_HW_ERR_INVALID_INDEX;
3167 break;
3168 }
3169 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3170 status = VXGE_HW_ERR_INVALID_OFFSET;
3171 break;
3172 }
3173 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3174 offset);
3175 break;
3176 case vxge_hw_mgmt_reg_type_vpath:
3177 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3178 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3179 status = VXGE_HW_ERR_INVALID_INDEX;
3180 break;
3181 }
3182 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3183 status = VXGE_HW_ERR_INVALID_INDEX;
3184 break;
3185 }
3186 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3187 status = VXGE_HW_ERR_INVALID_OFFSET;
3188 break;
3189 }
3190 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3191 offset);
3192 break;
3193 default:
3194 status = VXGE_HW_ERR_INVALID_TYPE;
3195 break;
3196 }
3197
3198 exit:
3199 return status;
3200 }
3201
3202 /*
3203 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3204 */
3205 enum vxge_hw_status
3206 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3207 {
3208 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
3209 int i = 0, j = 0;
3210
3211 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3212 if (!((vpath_mask) & vxge_mBIT(i)))
3213 continue;
3214 vpmgmt_reg = hldev->vpmgmt_reg[i];
3215 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3216 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3217 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3218 return VXGE_HW_FAIL;
3219 }
3220 }
3221 return VXGE_HW_OK;
3222 }
3223 /*
3224 * vxge_hw_mgmt_reg_Write - Write Titan register.
3225 */
3226 enum vxge_hw_status
3227 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3228 enum vxge_hw_mgmt_reg_type type,
3229 u32 index, u32 offset, u64 value)
3230 {
3231 enum vxge_hw_status status = VXGE_HW_OK;
3232
3233 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3234 status = VXGE_HW_ERR_INVALID_DEVICE;
3235 goto exit;
3236 }
3237
3238 switch (type) {
3239 case vxge_hw_mgmt_reg_type_legacy:
3240 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3241 status = VXGE_HW_ERR_INVALID_OFFSET;
3242 break;
3243 }
3244 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3245 break;
3246 case vxge_hw_mgmt_reg_type_toc:
3247 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3248 status = VXGE_HW_ERR_INVALID_OFFSET;
3249 break;
3250 }
3251 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3252 break;
3253 case vxge_hw_mgmt_reg_type_common:
3254 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3255 status = VXGE_HW_ERR_INVALID_OFFSET;
3256 break;
3257 }
3258 writeq(value, (void __iomem *)hldev->common_reg + offset);
3259 break;
3260 case vxge_hw_mgmt_reg_type_mrpcim:
3261 if (!(hldev->access_rights &
3262 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3263 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3264 break;
3265 }
3266 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3267 status = VXGE_HW_ERR_INVALID_OFFSET;
3268 break;
3269 }
3270 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3271 break;
3272 case vxge_hw_mgmt_reg_type_srpcim:
3273 if (!(hldev->access_rights &
3274 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3275 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3276 break;
3277 }
3278 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3279 status = VXGE_HW_ERR_INVALID_INDEX;
3280 break;
3281 }
3282 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3283 status = VXGE_HW_ERR_INVALID_OFFSET;
3284 break;
3285 }
3286 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3287 offset);
3288
3289 break;
3290 case vxge_hw_mgmt_reg_type_vpmgmt:
3291 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3292 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3293 status = VXGE_HW_ERR_INVALID_INDEX;
3294 break;
3295 }
3296 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3297 status = VXGE_HW_ERR_INVALID_OFFSET;
3298 break;
3299 }
3300 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3301 offset);
3302 break;
3303 case vxge_hw_mgmt_reg_type_vpath:
3304 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3305 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3306 status = VXGE_HW_ERR_INVALID_INDEX;
3307 break;
3308 }
3309 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3310 status = VXGE_HW_ERR_INVALID_OFFSET;
3311 break;
3312 }
3313 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3314 offset);
3315 break;
3316 default:
3317 status = VXGE_HW_ERR_INVALID_TYPE;
3318 break;
3319 }
3320 exit:
3321 return status;
3322 }
3323
3324 /*
3325 * __vxge_hw_fifo_abort - Returns the TxD
3326 * This function terminates the TxDs of fifo
3327 */
3328 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3329 {
3330 void *txdlh;
3331
3332 for (;;) {
3333 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3334
3335 if (txdlh == NULL)
3336 break;
3337
3338 vxge_hw_channel_dtr_complete(&fifo->channel);
3339
3340 if (fifo->txdl_term) {
3341 fifo->txdl_term(txdlh,
3342 VXGE_HW_TXDL_STATE_POSTED,
3343 fifo->channel.userdata);
3344 }
3345
3346 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3347 }
3348
3349 return VXGE_HW_OK;
3350 }
3351
3352 /*
3353 * __vxge_hw_fifo_reset - Resets the fifo
3354 * This function resets the fifo during vpath reset operation
3355 */
3356 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3357 {
3358 enum vxge_hw_status status = VXGE_HW_OK;
3359
3360 __vxge_hw_fifo_abort(fifo);
3361 status = __vxge_hw_channel_reset(&fifo->channel);
3362
3363 return status;
3364 }
3365
3366 /*
3367 * __vxge_hw_fifo_delete - Removes the FIFO
3368 * This function freeup the memory pool and removes the FIFO
3369 */
3370 static enum vxge_hw_status
3371 __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3372 {
3373 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3374
3375 __vxge_hw_fifo_abort(fifo);
3376
3377 if (fifo->mempool)
3378 __vxge_hw_mempool_destroy(fifo->mempool);
3379
3380 vp->vpath->fifoh = NULL;
3381
3382 __vxge_hw_channel_free(&fifo->channel);
3383
3384 return VXGE_HW_OK;
3385 }
3386
3387 /*
3388 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3389 * list callback
3390 * This function is callback passed to __vxge_hw_mempool_create to create memory
3391 * pool for TxD list
3392 */
3393 static void
3394 __vxge_hw_fifo_mempool_item_alloc(
3395 struct vxge_hw_mempool *mempoolh,
3396 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3397 u32 index, u32 is_last)
3398 {
3399 u32 memblock_item_idx;
3400 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3401 struct vxge_hw_fifo_txd *txdp =
3402 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3403 struct __vxge_hw_fifo *fifo =
3404 (struct __vxge_hw_fifo *)mempoolh->userdata;
3405 void *memblock = mempoolh->memblocks_arr[memblock_index];
3406
3407 vxge_assert(txdp);
3408
3409 txdp->host_control = (u64) (size_t)
3410 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3411 &memblock_item_idx);
3412
3413 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3414
3415 vxge_assert(txdl_priv);
3416
3417 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3418
3419 /* pre-format HW's TxDL's private */
3420 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3421 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3422 txdl_priv->dma_handle = dma_object->handle;
3423 txdl_priv->memblock = memblock;
3424 txdl_priv->first_txdp = txdp;
3425 txdl_priv->next_txdl_priv = NULL;
3426 txdl_priv->alloc_frags = 0;
3427 }
3428
3429 /*
3430 * __vxge_hw_fifo_create - Create a FIFO
3431 * This function creates FIFO and initializes it.
3432 */
3433 static enum vxge_hw_status
3434 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3435 struct vxge_hw_fifo_attr *attr)
3436 {
3437 enum vxge_hw_status status = VXGE_HW_OK;
3438 struct __vxge_hw_fifo *fifo;
3439 struct vxge_hw_fifo_config *config;
3440 u32 txdl_size, txdl_per_memblock;
3441 struct vxge_hw_mempool_cbs fifo_mp_callback;
3442 struct __vxge_hw_virtualpath *vpath;
3443
3444 if ((vp == NULL) || (attr == NULL)) {
3445 status = VXGE_HW_ERR_INVALID_HANDLE;
3446 goto exit;
3447 }
3448 vpath = vp->vpath;
3449 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3450
3451 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3452
3453 txdl_per_memblock = config->memblock_size / txdl_size;
3454
3455 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3456 VXGE_HW_CHANNEL_TYPE_FIFO,
3457 config->fifo_blocks * txdl_per_memblock,
3458 attr->per_txdl_space, attr->userdata);
3459
3460 if (fifo == NULL) {
3461 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3462 goto exit;
3463 }
3464
3465 vpath->fifoh = fifo;
3466 fifo->nofl_db = vpath->nofl_db;
3467
3468 fifo->vp_id = vpath->vp_id;
3469 fifo->vp_reg = vpath->vp_reg;
3470 fifo->stats = &vpath->sw_stats->fifo_stats;
3471
3472 fifo->config = config;
3473
3474 /* apply "interrupts per txdl" attribute */
3475 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3476 fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3477 fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3478
3479 if (fifo->config->intr)
3480 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3481
3482 fifo->no_snoop_bits = config->no_snoop_bits;
3483
3484 /*
3485 * FIFO memory management strategy:
3486 *
3487 * TxDL split into three independent parts:
3488 * - set of TxD's
3489 * - TxD HW private part
3490 * - driver private part
3491 *
3492 * Adaptative memory allocation used. i.e. Memory allocated on
3493 * demand with the size which will fit into one memory block.
3494 * One memory block may contain more than one TxDL.
3495 *
3496 * During "reserve" operations more memory can be allocated on demand
3497 * for example due to FIFO full condition.
3498 *
3499 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3500 * routine which will essentially stop the channel and free resources.
3501 */
3502
3503 /* TxDL common private size == TxDL private + driver private */
3504 fifo->priv_size =
3505 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3506 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
3507 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3508
3509 fifo->per_txdl_space = attr->per_txdl_space;
3510
3511 /* recompute txdl size to be cacheline aligned */
3512 fifo->txdl_size = txdl_size;
3513 fifo->txdl_per_memblock = txdl_per_memblock;
3514
3515 fifo->txdl_term = attr->txdl_term;
3516 fifo->callback = attr->callback;
3517
3518 if (fifo->txdl_per_memblock == 0) {
3519 __vxge_hw_fifo_delete(vp);
3520 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3521 goto exit;
3522 }
3523
3524 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3525
3526 fifo->mempool =
3527 __vxge_hw_mempool_create(vpath->hldev,
3528 fifo->config->memblock_size,
3529 fifo->txdl_size,
3530 fifo->priv_size,
3531 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3532 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3533 &fifo_mp_callback,
3534 fifo);
3535
3536 if (fifo->mempool == NULL) {
3537 __vxge_hw_fifo_delete(vp);
3538 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3539 goto exit;
3540 }
3541
3542 status = __vxge_hw_channel_initialize(&fifo->channel);
3543 if (status != VXGE_HW_OK) {
3544 __vxge_hw_fifo_delete(vp);
3545 goto exit;
3546 }
3547
3548 vxge_assert(fifo->channel.reserve_ptr);
3549 exit:
3550 return status;
3551 }
3552
3553 /*
3554 * __vxge_hw_vpath_pci_read - Read the content of given address
3555 * in pci config space.
3556 * Read from the vpath pci config space.
3557 */
3558 static enum vxge_hw_status
3559 __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3560 u32 phy_func_0, u32 offset, u32 *val)
3561 {
3562 u64 val64;
3563 enum vxge_hw_status status = VXGE_HW_OK;
3564 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3565
3566 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3567
3568 if (phy_func_0)
3569 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3570
3571 writeq(val64, &vp_reg->pci_config_access_cfg1);
3572 wmb();
3573 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3574 &vp_reg->pci_config_access_cfg2);
3575 wmb();
3576
3577 status = __vxge_hw_device_register_poll(
3578 &vp_reg->pci_config_access_cfg2,
3579 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3580
3581 if (status != VXGE_HW_OK)
3582 goto exit;
3583
3584 val64 = readq(&vp_reg->pci_config_access_status);
3585
3586 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3587 status = VXGE_HW_FAIL;
3588 *val = 0;
3589 } else
3590 *val = (u32)vxge_bVALn(val64, 32, 32);
3591 exit:
3592 return status;
3593 }
3594
3595 /**
3596 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3597 * @hldev: HW device.
3598 * @on_off: TRUE if flickering to be on, FALSE to be off
3599 *
3600 * Flicker the link LED.
3601 */
3602 enum vxge_hw_status
3603 vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
3604 {
3605 struct __vxge_hw_virtualpath *vpath;
3606 u64 data0, data1 = 0, steer_ctrl = 0;
3607 enum vxge_hw_status status;
3608
3609 if (hldev == NULL) {
3610 status = VXGE_HW_ERR_INVALID_DEVICE;
3611 goto exit;
3612 }
3613
3614 vpath = &hldev->virtual_paths[hldev->first_vp_id];
3615
3616 data0 = on_off;
3617 status = vxge_hw_vpath_fw_api(vpath,
3618 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3619 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3620 0, &data0, &data1, &steer_ctrl);
3621 exit:
3622 return status;
3623 }
3624
3625 /*
3626 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3627 */
3628 enum vxge_hw_status
3629 __vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3630 u32 action, u32 rts_table, u32 offset,
3631 u64 *data0, u64 *data1)
3632 {
3633 enum vxge_hw_status status;
3634 u64 steer_ctrl = 0;
3635
3636 if (vp == NULL) {
3637 status = VXGE_HW_ERR_INVALID_HANDLE;
3638 goto exit;
3639 }
3640
3641 if ((rts_table ==
3642 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
3643 (rts_table ==
3644 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
3645 (rts_table ==
3646 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
3647 (rts_table ==
3648 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3649 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
3650 }
3651
3652 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3653 data0, data1, &steer_ctrl);
3654 if (status != VXGE_HW_OK)
3655 goto exit;
3656
3657 if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
3658 (rts_table !=
3659 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3660 *data1 = 0;
3661 exit:
3662 return status;
3663 }
3664
3665 /*
3666 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3667 */
3668 enum vxge_hw_status
3669 __vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3670 u32 rts_table, u32 offset, u64 steer_data0,
3671 u64 steer_data1)
3672 {
3673 u64 data0, data1 = 0, steer_ctrl = 0;
3674 enum vxge_hw_status status;
3675
3676 if (vp == NULL) {
3677 status = VXGE_HW_ERR_INVALID_HANDLE;
3678 goto exit;
3679 }
3680
3681 data0 = steer_data0;
3682
3683 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3684 (rts_table ==
3685 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3686 data1 = steer_data1;
3687
3688 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3689 &data0, &data1, &steer_ctrl);
3690 exit:
3691 return status;
3692 }
3693
3694 /*
3695 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3696 */
3697 enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3698 struct __vxge_hw_vpath_handle *vp,
3699 enum vxge_hw_rth_algoritms algorithm,
3700 struct vxge_hw_rth_hash_types *hash_type,
3701 u16 bucket_size)
3702 {
3703 u64 data0, data1;
3704 enum vxge_hw_status status = VXGE_HW_OK;
3705
3706 if (vp == NULL) {
3707 status = VXGE_HW_ERR_INVALID_HANDLE;
3708 goto exit;
3709 }
3710
3711 status = __vxge_hw_vpath_rts_table_get(vp,
3712 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3713 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3714 0, &data0, &data1);
3715 if (status != VXGE_HW_OK)
3716 goto exit;
3717
3718 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3719 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3720
3721 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3722 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3723 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3724
3725 if (hash_type->hash_type_tcpipv4_en)
3726 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3727
3728 if (hash_type->hash_type_ipv4_en)
3729 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3730
3731 if (hash_type->hash_type_tcpipv6_en)
3732 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3733
3734 if (hash_type->hash_type_ipv6_en)
3735 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3736
3737 if (hash_type->hash_type_tcpipv6ex_en)
3738 data0 |=
3739 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3740
3741 if (hash_type->hash_type_ipv6ex_en)
3742 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3743
3744 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3745 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3746 else
3747 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3748
3749 status = __vxge_hw_vpath_rts_table_set(vp,
3750 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3751 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3752 0, data0, 0);
3753 exit:
3754 return status;
3755 }
3756
3757 static void
3758 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3759 u16 flag, u8 *itable)
3760 {
3761 switch (flag) {
3762 case 1:
3763 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3764 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3765 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3766 itable[j]);
3767 fallthrough;
3768 case 2:
3769 *data0 |=
3770 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3771 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3772 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3773 itable[j]);
3774 fallthrough;
3775 case 3:
3776 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3777 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3778 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3779 itable[j]);
3780 fallthrough;
3781 case 4:
3782 *data1 |=
3783 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3784 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3785 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3786 itable[j]);
3787 default:
3788 return;
3789 }
3790 }
3791 /*
3792 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3793 */
3794 enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3795 struct __vxge_hw_vpath_handle **vpath_handles,
3796 u32 vpath_count,
3797 u8 *mtable,
3798 u8 *itable,
3799 u32 itable_size)
3800 {
3801 u32 i, j, action, rts_table;
3802 u64 data0;
3803 u64 data1;
3804 u32 max_entries;
3805 enum vxge_hw_status status = VXGE_HW_OK;
3806 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3807
3808 if (vp == NULL) {
3809 status = VXGE_HW_ERR_INVALID_HANDLE;
3810 goto exit;
3811 }
3812
3813 max_entries = (((u32)1) << itable_size);
3814
3815 if (vp->vpath->hldev->config.rth_it_type
3816 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3817 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3818 rts_table =
3819 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3820
3821 for (j = 0; j < max_entries; j++) {
3822
3823 data1 = 0;
3824
3825 data0 =
3826 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3827 itable[j]);
3828
3829 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3830 action, rts_table, j, data0, data1);
3831
3832 if (status != VXGE_HW_OK)
3833 goto exit;
3834 }
3835
3836 for (j = 0; j < max_entries; j++) {
3837
3838 data1 = 0;
3839
3840 data0 =
3841 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3842 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3843 itable[j]);
3844
3845 status = __vxge_hw_vpath_rts_table_set(
3846 vpath_handles[mtable[itable[j]]], action,
3847 rts_table, j, data0, data1);
3848
3849 if (status != VXGE_HW_OK)
3850 goto exit;
3851 }
3852 } else {
3853 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3854 rts_table =
3855 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3856 for (i = 0; i < vpath_count; i++) {
3857
3858 for (j = 0; j < max_entries;) {
3859
3860 data0 = 0;
3861 data1 = 0;
3862
3863 while (j < max_entries) {
3864 if (mtable[itable[j]] != i) {
3865 j++;
3866 continue;
3867 }
3868 vxge_hw_rts_rth_data0_data1_get(j,
3869 &data0, &data1, 1, itable);
3870 j++;
3871 break;
3872 }
3873
3874 while (j < max_entries) {
3875 if (mtable[itable[j]] != i) {
3876 j++;
3877 continue;
3878 }
3879 vxge_hw_rts_rth_data0_data1_get(j,
3880 &data0, &data1, 2, itable);
3881 j++;
3882 break;
3883 }
3884
3885 while (j < max_entries) {
3886 if (mtable[itable[j]] != i) {
3887 j++;
3888 continue;
3889 }
3890 vxge_hw_rts_rth_data0_data1_get(j,
3891 &data0, &data1, 3, itable);
3892 j++;
3893 break;
3894 }
3895
3896 while (j < max_entries) {
3897 if (mtable[itable[j]] != i) {
3898 j++;
3899 continue;
3900 }
3901 vxge_hw_rts_rth_data0_data1_get(j,
3902 &data0, &data1, 4, itable);
3903 j++;
3904 break;
3905 }
3906
3907 if (data0 != 0) {
3908 status = __vxge_hw_vpath_rts_table_set(
3909 vpath_handles[i],
3910 action, rts_table,
3911 0, data0, data1);
3912
3913 if (status != VXGE_HW_OK)
3914 goto exit;
3915 }
3916 }
3917 }
3918 }
3919 exit:
3920 return status;
3921 }
3922
3923 /**
3924 * vxge_hw_vpath_check_leak - Check for memory leak
3925 * @ring: Handle to the ring object used for receive
3926 *
3927 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3928 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3929 * Returns: VXGE_HW_FAIL, if leak has occurred.
3930 *
3931 */
3932 enum vxge_hw_status
3933 vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3934 {
3935 enum vxge_hw_status status = VXGE_HW_OK;
3936 u64 rxd_new_count, rxd_spat;
3937
3938 if (ring == NULL)
3939 return status;
3940
3941 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3942 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3943 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3944
3945 if (rxd_new_count >= rxd_spat)
3946 status = VXGE_HW_FAIL;
3947
3948 return status;
3949 }
3950
3951 /*
3952 * __vxge_hw_vpath_mgmt_read
3953 * This routine reads the vpath_mgmt registers
3954 */
3955 static enum vxge_hw_status
3956 __vxge_hw_vpath_mgmt_read(
3957 struct __vxge_hw_device *hldev,
3958 struct __vxge_hw_virtualpath *vpath)
3959 {
3960 u32 i, mtu = 0, max_pyld = 0;
3961 u64 val64;
3962
3963 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3964
3965 val64 = readq(&vpath->vpmgmt_reg->
3966 rxmac_cfg0_port_vpmgmt_clone[i]);
3967 max_pyld =
3968 (u32)
3969 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3970 (val64);
3971 if (mtu < max_pyld)
3972 mtu = max_pyld;
3973 }
3974
3975 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3976
3977 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3978
3979 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3980 if (val64 & vxge_mBIT(i))
3981 vpath->vsport_number = i;
3982 }
3983
3984 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3985
3986 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3987 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3988 else
3989 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3990
3991 return VXGE_HW_OK;
3992 }
3993
3994 /*
3995 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
3996 * This routine checks the vpath_rst_in_prog register to see if
3997 * adapter completed the reset process for the vpath
3998 */
3999 static enum vxge_hw_status
4000 __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4001 {
4002 enum vxge_hw_status status;
4003
4004 status = __vxge_hw_device_register_poll(
4005 &vpath->hldev->common_reg->vpath_rst_in_prog,
4006 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4007 1 << (16 - vpath->vp_id)),
4008 vpath->hldev->config.device_poll_millis);
4009
4010 return status;
4011 }
4012
4013 /*
4014 * __vxge_hw_vpath_reset
4015 * This routine resets the vpath on the device
4016 */
4017 static enum vxge_hw_status
4018 __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4019 {
4020 u64 val64;
4021
4022 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4023
4024 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4025 &hldev->common_reg->cmn_rsthdlr_cfg0);
4026
4027 return VXGE_HW_OK;
4028 }
4029
4030 /*
4031 * __vxge_hw_vpath_sw_reset
4032 * This routine resets the vpath structures
4033 */
4034 static enum vxge_hw_status
4035 __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4036 {
4037 enum vxge_hw_status status = VXGE_HW_OK;
4038 struct __vxge_hw_virtualpath *vpath;
4039
4040 vpath = &hldev->virtual_paths[vp_id];
4041
4042 if (vpath->ringh) {
4043 status = __vxge_hw_ring_reset(vpath->ringh);
4044 if (status != VXGE_HW_OK)
4045 goto exit;
4046 }
4047
4048 if (vpath->fifoh)
4049 status = __vxge_hw_fifo_reset(vpath->fifoh);
4050 exit:
4051 return status;
4052 }
4053
4054 /*
4055 * __vxge_hw_vpath_prc_configure
4056 * This routine configures the prc registers of virtual path using the config
4057 * passed
4058 */
4059 static void
4060 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4061 {
4062 u64 val64;
4063 struct __vxge_hw_virtualpath *vpath;
4064 struct vxge_hw_vp_config *vp_config;
4065 struct vxge_hw_vpath_reg __iomem *vp_reg;
4066
4067 vpath = &hldev->virtual_paths[vp_id];
4068 vp_reg = vpath->vp_reg;
4069 vp_config = vpath->vp_config;
4070
4071 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4072 return;
4073
4074 val64 = readq(&vp_reg->prc_cfg1);
4075 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4076 writeq(val64, &vp_reg->prc_cfg1);
4077
4078 val64 = readq(&vpath->vp_reg->prc_cfg6);
4079 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4080 writeq(val64, &vpath->vp_reg->prc_cfg6);
4081
4082 val64 = readq(&vp_reg->prc_cfg7);
4083
4084 if (vpath->vp_config->ring.scatter_mode !=
4085 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4086
4087 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4088
4089 switch (vpath->vp_config->ring.scatter_mode) {
4090 case VXGE_HW_RING_SCATTER_MODE_A:
4091 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4092 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4093 break;
4094 case VXGE_HW_RING_SCATTER_MODE_B:
4095 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4096 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4097 break;
4098 case VXGE_HW_RING_SCATTER_MODE_C:
4099 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4100 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4101 break;
4102 }
4103 }
4104
4105 writeq(val64, &vp_reg->prc_cfg7);
4106
4107 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4108 __vxge_hw_ring_first_block_address_get(
4109 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4110
4111 val64 = readq(&vp_reg->prc_cfg4);
4112 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4113 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4114
4115 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4116 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4117
4118 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4119 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4120 else
4121 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4122
4123 writeq(val64, &vp_reg->prc_cfg4);
4124 }
4125
4126 /*
4127 * __vxge_hw_vpath_kdfc_configure
4128 * This routine configures the kdfc registers of virtual path using the
4129 * config passed
4130 */
4131 static enum vxge_hw_status
4132 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4133 {
4134 u64 val64;
4135 u64 vpath_stride;
4136 enum vxge_hw_status status = VXGE_HW_OK;
4137 struct __vxge_hw_virtualpath *vpath;
4138 struct vxge_hw_vpath_reg __iomem *vp_reg;
4139
4140 vpath = &hldev->virtual_paths[vp_id];
4141 vp_reg = vpath->vp_reg;
4142 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4143
4144 if (status != VXGE_HW_OK)
4145 goto exit;
4146
4147 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4148
4149 vpath->max_kdfc_db =
4150 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4151 val64+1)/2;
4152
4153 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4154
4155 vpath->max_nofl_db = vpath->max_kdfc_db;
4156
4157 if (vpath->max_nofl_db <
4158 ((vpath->vp_config->fifo.memblock_size /
4159 (vpath->vp_config->fifo.max_frags *
4160 sizeof(struct vxge_hw_fifo_txd))) *
4161 vpath->vp_config->fifo.fifo_blocks)) {
4162
4163 return VXGE_HW_BADCFG_FIFO_BLOCKS;
4164 }
4165 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4166 (vpath->max_nofl_db*2)-1);
4167 }
4168
4169 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4170
4171 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4172 &vp_reg->kdfc_fifo_trpl_ctrl);
4173
4174 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4175
4176 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4177 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4178
4179 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4180 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4181 #ifndef __BIG_ENDIAN
4182 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4183 #endif
4184 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4185
4186 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4187 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4188 wmb();
4189 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4190
4191 vpath->nofl_db =
4192 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4193 (hldev->kdfc + (vp_id *
4194 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4195 vpath_stride)));
4196 exit:
4197 return status;
4198 }
4199
4200 /*
4201 * __vxge_hw_vpath_mac_configure
4202 * This routine configures the mac of virtual path using the config passed
4203 */
4204 static enum vxge_hw_status
4205 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4206 {
4207 u64 val64;
4208 struct __vxge_hw_virtualpath *vpath;
4209 struct vxge_hw_vp_config *vp_config;
4210 struct vxge_hw_vpath_reg __iomem *vp_reg;
4211
4212 vpath = &hldev->virtual_paths[vp_id];
4213 vp_reg = vpath->vp_reg;
4214 vp_config = vpath->vp_config;
4215
4216 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4217 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4218
4219 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4220
4221 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4222
4223 if (vp_config->rpa_strip_vlan_tag !=
4224 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4225 if (vp_config->rpa_strip_vlan_tag)
4226 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4227 else
4228 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4229 }
4230
4231 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4232 val64 = readq(&vp_reg->rxmac_vcfg0);
4233
4234 if (vp_config->mtu !=
4235 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4236 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4237 if ((vp_config->mtu +
4238 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4239 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4240 vp_config->mtu +
4241 VXGE_HW_MAC_HEADER_MAX_SIZE);
4242 else
4243 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4244 vpath->max_mtu);
4245 }
4246
4247 writeq(val64, &vp_reg->rxmac_vcfg0);
4248
4249 val64 = readq(&vp_reg->rxmac_vcfg1);
4250
4251 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4252 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4253
4254 if (hldev->config.rth_it_type ==
4255 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4256 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4257 0x2) |
4258 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4259 }
4260
4261 writeq(val64, &vp_reg->rxmac_vcfg1);
4262 }
4263 return VXGE_HW_OK;
4264 }
4265
4266 /*
4267 * __vxge_hw_vpath_tim_configure
4268 * This routine configures the tim registers of virtual path using the config
4269 * passed
4270 */
4271 static enum vxge_hw_status
4272 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4273 {
4274 u64 val64;
4275 struct __vxge_hw_virtualpath *vpath;
4276 struct vxge_hw_vpath_reg __iomem *vp_reg;
4277 struct vxge_hw_vp_config *config;
4278
4279 vpath = &hldev->virtual_paths[vp_id];
4280 vp_reg = vpath->vp_reg;
4281 config = vpath->vp_config;
4282
4283 writeq(0, &vp_reg->tim_dest_addr);
4284 writeq(0, &vp_reg->tim_vpath_map);
4285 writeq(0, &vp_reg->tim_bitmap);
4286 writeq(0, &vp_reg->tim_remap);
4287
4288 if (config->ring.enable == VXGE_HW_RING_ENABLE)
4289 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4290 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4291 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4292
4293 val64 = readq(&vp_reg->tim_pci_cfg);
4294 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4295 writeq(val64, &vp_reg->tim_pci_cfg);
4296
4297 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4298
4299 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4300
4301 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4302 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4303 0x3ffffff);
4304 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4305 config->tti.btimer_val);
4306 }
4307
4308 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4309
4310 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4311 if (config->tti.timer_ac_en)
4312 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4313 else
4314 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4315 }
4316
4317 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4318 if (config->tti.timer_ci_en)
4319 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4320 else
4321 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4322 }
4323
4324 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4325 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4326 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4327 config->tti.urange_a);
4328 }
4329
4330 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4331 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4332 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4333 config->tti.urange_b);
4334 }
4335
4336 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4337 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4338 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4339 config->tti.urange_c);
4340 }
4341
4342 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4343 vpath->tim_tti_cfg1_saved = val64;
4344
4345 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4346
4347 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4348 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4349 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4350 config->tti.uec_a);
4351 }
4352
4353 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4354 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4355 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4356 config->tti.uec_b);
4357 }
4358
4359 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4360 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4361 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4362 config->tti.uec_c);
4363 }
4364
4365 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4366 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4367 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4368 config->tti.uec_d);
4369 }
4370
4371 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4372 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4373
4374 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4375 if (config->tti.timer_ri_en)
4376 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4377 else
4378 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4379 }
4380
4381 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4382 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4383 0x3ffffff);
4384 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4385 config->tti.rtimer_val);
4386 }
4387
4388 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4389 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4390 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4391 }
4392
4393 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4394 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4395 0x3ffffff);
4396 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4397 config->tti.ltimer_val);
4398 }
4399
4400 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4401 vpath->tim_tti_cfg3_saved = val64;
4402 }
4403
4404 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
4405
4406 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4407
4408 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4409 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4410 0x3ffffff);
4411 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4412 config->rti.btimer_val);
4413 }
4414
4415 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4416
4417 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4418 if (config->rti.timer_ac_en)
4419 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4420 else
4421 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4422 }
4423
4424 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4425 if (config->rti.timer_ci_en)
4426 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4427 else
4428 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4429 }
4430
4431 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4432 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4433 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4434 config->rti.urange_a);
4435 }
4436
4437 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4438 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4439 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4440 config->rti.urange_b);
4441 }
4442
4443 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4444 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4445 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4446 config->rti.urange_c);
4447 }
4448
4449 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4450 vpath->tim_rti_cfg1_saved = val64;
4451
4452 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4453
4454 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4455 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4456 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4457 config->rti.uec_a);
4458 }
4459
4460 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4461 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4462 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4463 config->rti.uec_b);
4464 }
4465
4466 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4467 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4468 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4469 config->rti.uec_c);
4470 }
4471
4472 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4473 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4474 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4475 config->rti.uec_d);
4476 }
4477
4478 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4479 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4480
4481 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4482 if (config->rti.timer_ri_en)
4483 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4484 else
4485 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4486 }
4487
4488 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4489 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4490 0x3ffffff);
4491 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4492 config->rti.rtimer_val);
4493 }
4494
4495 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4496 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4497 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4498 }
4499
4500 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4501 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4502 0x3ffffff);
4503 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4504 config->rti.ltimer_val);
4505 }
4506
4507 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4508 vpath->tim_rti_cfg3_saved = val64;
4509 }
4510
4511 val64 = 0;
4512 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4513 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4514 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4515 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4516 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4517 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4518
4519 val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4520 val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4521 val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4522 writeq(val64, &vp_reg->tim_wrkld_clc);
4523
4524 return VXGE_HW_OK;
4525 }
4526
4527 /*
4528 * __vxge_hw_vpath_initialize
4529 * This routine is the final phase of init which initializes the
4530 * registers of the vpath using the configuration passed.
4531 */
4532 static enum vxge_hw_status
4533 __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4534 {
4535 u64 val64;
4536 u32 val32;
4537 enum vxge_hw_status status = VXGE_HW_OK;
4538 struct __vxge_hw_virtualpath *vpath;
4539 struct vxge_hw_vpath_reg __iomem *vp_reg;
4540
4541 vpath = &hldev->virtual_paths[vp_id];
4542
4543 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4544 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4545 goto exit;
4546 }
4547 vp_reg = vpath->vp_reg;
4548
4549 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4550 if (status != VXGE_HW_OK)
4551 goto exit;
4552
4553 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
4554 if (status != VXGE_HW_OK)
4555 goto exit;
4556
4557 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4558 if (status != VXGE_HW_OK)
4559 goto exit;
4560
4561 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4562 if (status != VXGE_HW_OK)
4563 goto exit;
4564
4565 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4566
4567 /* Get MRRS value from device control */
4568 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4569 if (status == VXGE_HW_OK) {
4570 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4571 val64 &=
4572 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4573 val64 |=
4574 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4575
4576 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4577 }
4578
4579 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4580 val64 |=
4581 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4582 VXGE_HW_MAX_PAYLOAD_SIZE_512);
4583
4584 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4585 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4586
4587 exit:
4588 return status;
4589 }
4590
4591 /*
4592 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4593 * This routine closes all channels it opened and freeup memory
4594 */
4595 static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4596 {
4597 struct __vxge_hw_virtualpath *vpath;
4598
4599 vpath = &hldev->virtual_paths[vp_id];
4600
4601 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4602 goto exit;
4603
4604 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4605 vpath->hldev->tim_int_mask1, vpath->vp_id);
4606 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4607
4608 /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4609 * work after the interface is brought down.
4610 */
4611 spin_lock(&vpath->lock);
4612 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4613 spin_unlock(&vpath->lock);
4614
4615 vpath->vpmgmt_reg = NULL;
4616 vpath->nofl_db = NULL;
4617 vpath->max_mtu = 0;
4618 vpath->vsport_number = 0;
4619 vpath->max_kdfc_db = 0;
4620 vpath->max_nofl_db = 0;
4621 vpath->ringh = NULL;
4622 vpath->fifoh = NULL;
4623 memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
4624 vpath->stats_block = NULL;
4625 vpath->hw_stats = NULL;
4626 vpath->hw_stats_sav = NULL;
4627 vpath->sw_stats = NULL;
4628
4629 exit:
4630 return;
4631 }
4632
4633 /*
4634 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4635 * This routine is the initial phase of init which resets the vpath and
4636 * initializes the software support structures.
4637 */
4638 static enum vxge_hw_status
4639 __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4640 struct vxge_hw_vp_config *config)
4641 {
4642 struct __vxge_hw_virtualpath *vpath;
4643 enum vxge_hw_status status = VXGE_HW_OK;
4644
4645 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4646 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4647 goto exit;
4648 }
4649
4650 vpath = &hldev->virtual_paths[vp_id];
4651
4652 spin_lock_init(&vpath->lock);
4653 vpath->vp_id = vp_id;
4654 vpath->vp_open = VXGE_HW_VP_OPEN;
4655 vpath->hldev = hldev;
4656 vpath->vp_config = config;
4657 vpath->vp_reg = hldev->vpath_reg[vp_id];
4658 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4659
4660 __vxge_hw_vpath_reset(hldev, vp_id);
4661
4662 status = __vxge_hw_vpath_reset_check(vpath);
4663 if (status != VXGE_HW_OK) {
4664 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4665 goto exit;
4666 }
4667
4668 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4669 if (status != VXGE_HW_OK) {
4670 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4671 goto exit;
4672 }
4673
4674 INIT_LIST_HEAD(&vpath->vpath_handles);
4675
4676 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4677
4678 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4679 hldev->tim_int_mask1, vp_id);
4680
4681 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4682 if (status != VXGE_HW_OK)
4683 __vxge_hw_vp_terminate(hldev, vp_id);
4684 exit:
4685 return status;
4686 }
4687
4688 /*
4689 * vxge_hw_vpath_mtu_set - Set MTU.
4690 * Set new MTU value. Example, to use jumbo frames:
4691 * vxge_hw_vpath_mtu_set(my_device, 9600);
4692 */
4693 enum vxge_hw_status
4694 vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4695 {
4696 u64 val64;
4697 enum vxge_hw_status status = VXGE_HW_OK;
4698 struct __vxge_hw_virtualpath *vpath;
4699
4700 if (vp == NULL) {
4701 status = VXGE_HW_ERR_INVALID_HANDLE;
4702 goto exit;
4703 }
4704 vpath = vp->vpath;
4705
4706 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4707
4708 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4709 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4710
4711 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4712
4713 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4714 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4715
4716 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4717
4718 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4719
4720 exit:
4721 return status;
4722 }
4723
4724 /*
4725 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4726 * Enable the DMA vpath statistics. The function is to be called to re-enable
4727 * the adapter to update stats into the host memory
4728 */
4729 static enum vxge_hw_status
4730 vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4731 {
4732 enum vxge_hw_status status = VXGE_HW_OK;
4733 struct __vxge_hw_virtualpath *vpath;
4734
4735 vpath = vp->vpath;
4736
4737 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4738 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4739 goto exit;
4740 }
4741
4742 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4743 sizeof(struct vxge_hw_vpath_stats_hw_info));
4744
4745 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4746 exit:
4747 return status;
4748 }
4749
4750 /*
4751 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4752 * This function allocates a block from block pool or from the system
4753 */
4754 static struct __vxge_hw_blockpool_entry *
4755 __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4756 {
4757 struct __vxge_hw_blockpool_entry *entry = NULL;
4758 struct __vxge_hw_blockpool *blockpool;
4759
4760 blockpool = &devh->block_pool;
4761
4762 if (size == blockpool->block_size) {
4763
4764 if (!list_empty(&blockpool->free_block_list))
4765 entry = (struct __vxge_hw_blockpool_entry *)
4766 list_first_entry(&blockpool->free_block_list,
4767 struct __vxge_hw_blockpool_entry,
4768 item);
4769
4770 if (entry != NULL) {
4771 list_del(&entry->item);
4772 blockpool->pool_size--;
4773 }
4774 }
4775
4776 if (entry != NULL)
4777 __vxge_hw_blockpool_blocks_add(blockpool);
4778
4779 return entry;
4780 }
4781
4782 /*
4783 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4784 * This function is used to open access to virtual path of an
4785 * adapter for offload, GRO operations. This function returns
4786 * synchronously.
4787 */
4788 enum vxge_hw_status
4789 vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4790 struct vxge_hw_vpath_attr *attr,
4791 struct __vxge_hw_vpath_handle **vpath_handle)
4792 {
4793 struct __vxge_hw_virtualpath *vpath;
4794 struct __vxge_hw_vpath_handle *vp;
4795 enum vxge_hw_status status;
4796
4797 vpath = &hldev->virtual_paths[attr->vp_id];
4798
4799 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4800 status = VXGE_HW_ERR_INVALID_STATE;
4801 goto vpath_open_exit1;
4802 }
4803
4804 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4805 &hldev->config.vp_config[attr->vp_id]);
4806 if (status != VXGE_HW_OK)
4807 goto vpath_open_exit1;
4808
4809 vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4810 if (vp == NULL) {
4811 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4812 goto vpath_open_exit2;
4813 }
4814
4815 vp->vpath = vpath;
4816
4817 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4818 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4819 if (status != VXGE_HW_OK)
4820 goto vpath_open_exit6;
4821 }
4822
4823 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4824 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4825 if (status != VXGE_HW_OK)
4826 goto vpath_open_exit7;
4827
4828 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4829 }
4830
4831 vpath->fifoh->tx_intr_num =
4832 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4833 VXGE_HW_VPATH_INTR_TX;
4834
4835 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4836 VXGE_HW_BLOCK_SIZE);
4837 if (vpath->stats_block == NULL) {
4838 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4839 goto vpath_open_exit8;
4840 }
4841
4842 vpath->hw_stats = vpath->stats_block->memblock;
4843 memset(vpath->hw_stats, 0,
4844 sizeof(struct vxge_hw_vpath_stats_hw_info));
4845
4846 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4847 vpath->hw_stats;
4848
4849 vpath->hw_stats_sav =
4850 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4851 memset(vpath->hw_stats_sav, 0,
4852 sizeof(struct vxge_hw_vpath_stats_hw_info));
4853
4854 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4855
4856 status = vxge_hw_vpath_stats_enable(vp);
4857 if (status != VXGE_HW_OK)
4858 goto vpath_open_exit8;
4859
4860 list_add(&vp->item, &vpath->vpath_handles);
4861
4862 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4863
4864 *vpath_handle = vp;
4865
4866 attr->fifo_attr.userdata = vpath->fifoh;
4867 attr->ring_attr.userdata = vpath->ringh;
4868
4869 return VXGE_HW_OK;
4870
4871 vpath_open_exit8:
4872 if (vpath->ringh != NULL)
4873 __vxge_hw_ring_delete(vp);
4874 vpath_open_exit7:
4875 if (vpath->fifoh != NULL)
4876 __vxge_hw_fifo_delete(vp);
4877 vpath_open_exit6:
4878 vfree(vp);
4879 vpath_open_exit2:
4880 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4881 vpath_open_exit1:
4882
4883 return status;
4884 }
4885
4886 /**
4887 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4888 * (vpath) open
4889 * @vp: Handle got from previous vpath open
4890 *
4891 * This function is used to close access to virtual path opened
4892 * earlier.
4893 */
4894 void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4895 {
4896 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4897 struct __vxge_hw_ring *ring = vpath->ringh;
4898 struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4899 u64 new_count, val64, val164;
4900
4901 if (vdev->titan1) {
4902 new_count = readq(&vpath->vp_reg->rxdmem_size);
4903 new_count &= 0x1fff;
4904 } else
4905 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
4906
4907 val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
4908
4909 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4910 &vpath->vp_reg->prc_rxd_doorbell);
4911 readl(&vpath->vp_reg->prc_rxd_doorbell);
4912
4913 val164 /= 2;
4914 val64 = readq(&vpath->vp_reg->prc_cfg6);
4915 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4916 val64 &= 0x1ff;
4917
4918 /*
4919 * Each RxD is of 4 qwords
4920 */
4921 new_count -= (val64 + 1);
4922 val64 = min(val164, new_count) / 4;
4923
4924 ring->rxds_limit = min(ring->rxds_limit, val64);
4925 if (ring->rxds_limit < 4)
4926 ring->rxds_limit = 4;
4927 }
4928
4929 /*
4930 * __vxge_hw_blockpool_block_free - Frees a block from block pool
4931 * @devh: Hal device
4932 * @entry: Entry of block to be freed
4933 *
4934 * This function frees a block from block pool
4935 */
4936 static void
4937 __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4938 struct __vxge_hw_blockpool_entry *entry)
4939 {
4940 struct __vxge_hw_blockpool *blockpool;
4941
4942 blockpool = &devh->block_pool;
4943
4944 if (entry->length == blockpool->block_size) {
4945 list_add(&entry->item, &blockpool->free_block_list);
4946 blockpool->pool_size++;
4947 }
4948
4949 __vxge_hw_blockpool_blocks_remove(blockpool);
4950 }
4951
4952 /*
4953 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4954 * This function is used to close access to virtual path opened
4955 * earlier.
4956 */
4957 enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4958 {
4959 struct __vxge_hw_virtualpath *vpath = NULL;
4960 struct __vxge_hw_device *devh = NULL;
4961 u32 vp_id = vp->vpath->vp_id;
4962 u32 is_empty = TRUE;
4963 enum vxge_hw_status status = VXGE_HW_OK;
4964
4965 vpath = vp->vpath;
4966 devh = vpath->hldev;
4967
4968 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4969 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4970 goto vpath_close_exit;
4971 }
4972
4973 list_del(&vp->item);
4974
4975 if (!list_empty(&vpath->vpath_handles)) {
4976 list_add(&vp->item, &vpath->vpath_handles);
4977 is_empty = FALSE;
4978 }
4979
4980 if (!is_empty) {
4981 status = VXGE_HW_FAIL;
4982 goto vpath_close_exit;
4983 }
4984
4985 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4986
4987 if (vpath->ringh != NULL)
4988 __vxge_hw_ring_delete(vp);
4989
4990 if (vpath->fifoh != NULL)
4991 __vxge_hw_fifo_delete(vp);
4992
4993 if (vpath->stats_block != NULL)
4994 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
4995
4996 vfree(vp);
4997
4998 __vxge_hw_vp_terminate(devh, vp_id);
4999
5000 vpath_close_exit:
5001 return status;
5002 }
5003
5004 /*
5005 * vxge_hw_vpath_reset - Resets vpath
5006 * This function is used to request a reset of vpath
5007 */
5008 enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
5009 {
5010 enum vxge_hw_status status;
5011 u32 vp_id;
5012 struct __vxge_hw_virtualpath *vpath = vp->vpath;
5013
5014 vp_id = vpath->vp_id;
5015
5016 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5017 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5018 goto exit;
5019 }
5020
5021 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5022 if (status == VXGE_HW_OK)
5023 vpath->sw_stats->soft_reset_cnt++;
5024 exit:
5025 return status;
5026 }
5027
5028 /*
5029 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5030 * This function poll's for the vpath reset completion and re initializes
5031 * the vpath.
5032 */
5033 enum vxge_hw_status
5034 vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
5035 {
5036 struct __vxge_hw_virtualpath *vpath = NULL;
5037 enum vxge_hw_status status;
5038 struct __vxge_hw_device *hldev;
5039 u32 vp_id;
5040
5041 vp_id = vp->vpath->vp_id;
5042 vpath = vp->vpath;
5043 hldev = vpath->hldev;
5044
5045 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5046 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5047 goto exit;
5048 }
5049
5050 status = __vxge_hw_vpath_reset_check(vpath);
5051 if (status != VXGE_HW_OK)
5052 goto exit;
5053
5054 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5055 if (status != VXGE_HW_OK)
5056 goto exit;
5057
5058 status = __vxge_hw_vpath_initialize(hldev, vp_id);
5059 if (status != VXGE_HW_OK)
5060 goto exit;
5061
5062 if (vpath->ringh != NULL)
5063 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5064
5065 memset(vpath->hw_stats, 0,
5066 sizeof(struct vxge_hw_vpath_stats_hw_info));
5067
5068 memset(vpath->hw_stats_sav, 0,
5069 sizeof(struct vxge_hw_vpath_stats_hw_info));
5070
5071 writeq(vpath->stats_block->dma_addr,
5072 &vpath->vp_reg->stats_cfg);
5073
5074 status = vxge_hw_vpath_stats_enable(vp);
5075
5076 exit:
5077 return status;
5078 }
5079
5080 /*
5081 * vxge_hw_vpath_enable - Enable vpath.
5082 * This routine clears the vpath reset thereby enabling a vpath
5083 * to start forwarding frames and generating interrupts.
5084 */
5085 void
5086 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
5087 {
5088 struct __vxge_hw_device *hldev;
5089 u64 val64;
5090
5091 hldev = vp->vpath->hldev;
5092
5093 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5094 1 << (16 - vp->vpath->vp_id));
5095
5096 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5097 &hldev->common_reg->cmn_rsthdlr_cfg1);
5098 }
Linux with added FPC-III support