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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic.h
blobe5c51256243a7aa91f1801bea23871331711f3e2
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2003 - 2009 NetXen, Inc.
4 * Copyright (C) 2009 - QLogic Corporation.
5 * All rights reserved.
6 */
7
8 #ifndef _NETXEN_NIC_H_
9 #define _NETXEN_NIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <asm/io.h>
31 #include <asm/byteorder.h>
32
33 #include "netxen_nic_hdr.h"
34 #include "netxen_nic_hw.h"
35
36 #define _NETXEN_NIC_LINUX_MAJOR 4
37 #define _NETXEN_NIC_LINUX_MINOR 0
38 #define _NETXEN_NIC_LINUX_SUBVERSION 82
39 #define NETXEN_NIC_LINUX_VERSIONID "4.0.82"
40
41 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
42 #define _major(v) (((v) >> 24) & 0xff)
43 #define _minor(v) (((v) >> 16) & 0xff)
44 #define _build(v) ((v) & 0xffff)
45
46 /* version in image has weird encoding:
47 * 7:0 - major
48 * 15:8 - minor
49 * 31:16 - build (little endian)
50 */
51 #define NETXEN_DECODE_VERSION(v) \
52 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
53
54 #define NETXEN_NUM_FLASH_SECTORS (64)
55 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
56 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
57 * NETXEN_FLASH_SECTOR_SIZE)
58
59 #define RCV_DESC_RINGSIZE(rds_ring) \
60 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
61 #define RCV_BUFF_RINGSIZE(rds_ring) \
62 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
63 #define STATUS_DESC_RINGSIZE(sds_ring) \
64 (sizeof(struct status_desc) * (sds_ring)->num_desc)
65 #define TX_BUFF_RINGSIZE(tx_ring) \
66 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
67 #define TX_DESC_RINGSIZE(tx_ring) \
68 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
69
70 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
71
72 #define NETXEN_RCV_PRODUCER_OFFSET 0
73 #define NETXEN_RCV_PEG_DB_ID 2
74 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
75 #define FLASH_SUCCESS 0
76
77 #define ADDR_IN_WINDOW1(off) \
78 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
79
80 #define ADDR_IN_RANGE(addr, low, high) \
81 (((addr) < (high)) && ((addr) >= (low)))
82
83 /*
84 * normalize a 64MB crb address to 32MB PCI window
85 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
86 */
87 #define NETXEN_CRB_NORMAL(reg) \
88 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
89
90 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
91 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
92
93 #define DB_NORMALIZE(adapter, off) \
94 (adapter->ahw.db_base + (off))
95
96 #define NX_P2_C0 0x24
97 #define NX_P2_C1 0x25
98 #define NX_P3_A0 0x30
99 #define NX_P3_A2 0x30
100 #define NX_P3_B0 0x40
101 #define NX_P3_B1 0x41
102 #define NX_P3_B2 0x42
103 #define NX_P3P_A0 0x50
104
105 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
106 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
107 #define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
108
109 #define FIRST_PAGE_GROUP_START 0
110 #define FIRST_PAGE_GROUP_END 0x100000
111
112 #define SECOND_PAGE_GROUP_START 0x6000000
113 #define SECOND_PAGE_GROUP_END 0x68BC000
114
115 #define THIRD_PAGE_GROUP_START 0x70E4000
116 #define THIRD_PAGE_GROUP_END 0x8000000
117
118 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
119 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
120 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
121
122 #define P2_MAX_MTU (8000)
123 #define P3_MAX_MTU (9600)
124 #define NX_ETHERMTU 1500
125 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
126
127 #define NX_P2_RX_BUF_MAX_LEN 1760
128 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
129 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
130 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
131 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
132 #define NX_LRO_BUFFER_EXTRA 2048
133
134 #define NX_RX_LRO_BUFFER_LENGTH (8060)
135
136 /*
137 * Maximum number of ring contexts
138 */
139 #define MAX_RING_CTX 1
140
141 /* Opcodes to be used with the commands */
142 #define TX_ETHER_PKT 0x01
143 #define TX_TCP_PKT 0x02
144 #define TX_UDP_PKT 0x03
145 #define TX_IP_PKT 0x04
146 #define TX_TCP_LSO 0x05
147 #define TX_TCP_LSO6 0x06
148 #define TX_IPSEC 0x07
149 #define TX_IPSEC_CMD 0x0a
150 #define TX_TCPV6_PKT 0x0b
151 #define TX_UDPV6_PKT 0x0c
152
153 /* The following opcodes are for internal consumption. */
154 #define NETXEN_CONTROL_OP 0x10
155 #define PEGNET_REQUEST 0x11
156
157 #define MAX_NUM_CARDS 4
158
159 #define NETXEN_MAX_FRAGS_PER_TX 14
160 #define MAX_TSO_HEADER_DESC 2
161 #define MGMT_CMD_DESC_RESV 4
162 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
163 + MGMT_CMD_DESC_RESV)
164 #define NX_MAX_TX_TIMEOUTS 2
165
166 /*
167 * Following are the states of the Phantom. Phantom will set them and
168 * Host will read to check if the fields are correct.
169 */
170 #define PHAN_INITIALIZE_START 0xff00
171 #define PHAN_INITIALIZE_FAILED 0xffff
172 #define PHAN_INITIALIZE_COMPLETE 0xff01
173
174 /* Host writes the following to notify that it has done the init-handshake */
175 #define PHAN_INITIALIZE_ACK 0xf00f
176
177 #define NUM_RCV_DESC_RINGS 3
178 #define NUM_STS_DESC_RINGS 4
179
180 #define RCV_RING_NORMAL 0
181 #define RCV_RING_JUMBO 1
182 #define RCV_RING_LRO 2
183
184 #define MIN_CMD_DESCRIPTORS 64
185 #define MIN_RCV_DESCRIPTORS 64
186 #define MIN_JUMBO_DESCRIPTORS 32
187
188 #define MAX_CMD_DESCRIPTORS 1024
189 #define MAX_RCV_DESCRIPTORS_1G 4096
190 #define MAX_RCV_DESCRIPTORS_10G 8192
191 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
192 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
193 #define MAX_LRO_RCV_DESCRIPTORS 8
194
195 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
196 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
197
198 #define NETXEN_CTX_SIGNATURE 0xdee0
199 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
200 #define NETXEN_CTX_RESET 0xbad0
201 #define NETXEN_CTX_D3_RESET 0xacc0
202 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
203
204 #define PHAN_PEG_RCV_INITIALIZED 0xff01
205 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
206
207 #define get_next_index(index, length) \
208 (((index) + 1) & ((length) - 1))
209
210 #define get_index_range(index,length,count) \
211 (((index) + (count)) & ((length) - 1))
212
213 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
214 #define MPORT_MULTI_FUNCTION_MODE 0x2222
215
216 #define NX_MAX_PCI_FUNC 8
217
218 /*
219 * NetXen host-peg signal message structure
220 *
221 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
222 * Bit 2 : priv_id => must be 1
223 * Bit 3-17 : count => for doorbell
224 * Bit 18-27 : ctx_id => Context id
225 * Bit 28-31 : opcode
226 */
227
228 typedef u32 netxen_ctx_msg;
229
230 #define netxen_set_msg_peg_id(config_word, val) \
231 ((config_word) &= ~3, (config_word) |= val & 3)
232 #define netxen_set_msg_privid(config_word) \
233 ((config_word) |= 1 << 2)
234 #define netxen_set_msg_count(config_word, val) \
235 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
236 #define netxen_set_msg_ctxid(config_word, val) \
237 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
238 #define netxen_set_msg_opcode(config_word, val) \
239 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
240
241 struct netxen_rcv_ring {
242 __le64 addr;
243 __le32 size;
244 __le32 rsrvd;
245 };
246
247 struct netxen_sts_ring {
248 __le64 addr;
249 __le32 size;
250 __le16 msi_index;
251 __le16 rsvd;
252 } ;
253
254 struct netxen_ring_ctx {
255
256 /* one command ring */
257 __le64 cmd_consumer_offset;
258 __le64 cmd_ring_addr;
259 __le32 cmd_ring_size;
260 __le32 rsrvd;
261
262 /* three receive rings */
263 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
264
265 __le64 sts_ring_addr;
266 __le32 sts_ring_size;
267
268 __le32 ctx_id;
269
270 __le64 rsrvd_2[3];
271 __le32 sts_ring_count;
272 __le32 rsrvd_3;
273 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
274
275 } __attribute__ ((aligned(64)));
276
277 /*
278 * Following data structures describe the descriptors that will be used.
279 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
280 * we are doing LSO (above the 1500 size packet) only.
281 */
282
283 /*
284 * The size of reference handle been changed to 16 bits to pass the MSS fields
285 * for the LSO packet
286 */
287
288 #define FLAGS_CHECKSUM_ENABLED 0x01
289 #define FLAGS_LSO_ENABLED 0x02
290 #define FLAGS_IPSEC_SA_ADD 0x04
291 #define FLAGS_IPSEC_SA_DELETE 0x08
292 #define FLAGS_VLAN_TAGGED 0x10
293 #define FLAGS_VLAN_OOB 0x40
294
295 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
296 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
297
298 #define netxen_set_cmd_desc_port(cmd_desc, var) \
299 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
300 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
301 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
302
303 #define netxen_set_tx_port(_desc, _port) \
304 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
305
306 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
307 (_desc)->flags_opcode = \
308 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
309
310 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
311 (_desc)->nfrags__length = \
312 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
313
314 struct cmd_desc_type0 {
315 u8 tcp_hdr_offset; /* For LSO only */
316 u8 ip_hdr_offset; /* For LSO only */
317 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
318 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
319
320 __le64 addr_buffer2;
321
322 __le16 reference_handle;
323 __le16 mss;
324 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
325 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
326 __le16 conn_id; /* IPSec offoad only */
327
328 __le64 addr_buffer3;
329 __le64 addr_buffer1;
330
331 __le16 buffer_length[4];
332
333 __le64 addr_buffer4;
334
335 __le32 reserved2;
336 __le16 reserved;
337 __le16 vlan_TCI;
338
339 } __attribute__ ((aligned(64)));
340
341 /* Note: sizeof(rcv_desc) should always be a multiple of 2 */
342 struct rcv_desc {
343 __le16 reference_handle;
344 __le16 reserved;
345 __le32 buffer_length; /* allocated buffer length (usually 2K) */
346 __le64 addr_buffer;
347 };
348
349 /* opcode field in status_desc */
350 #define NETXEN_NIC_SYN_OFFLOAD 0x03
351 #define NETXEN_NIC_RXPKT_DESC 0x04
352 #define NETXEN_OLD_RXPKT_DESC 0x3f
353 #define NETXEN_NIC_RESPONSE_DESC 0x05
354 #define NETXEN_NIC_LRO_DESC 0x12
355
356 /* for status field in status_desc */
357 #define STATUS_NEED_CKSUM (1)
358 #define STATUS_CKSUM_OK (2)
359
360 /* owner bits of status_desc */
361 #define STATUS_OWNER_HOST (0x1ULL << 56)
362 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
363
364 /* Status descriptor:
365 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
366 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
367 53-55 desc_cnt, 56-57 owner, 58-63 opcode
368 */
369 #define netxen_get_sts_port(sts_data) \
370 ((sts_data) & 0x0F)
371 #define netxen_get_sts_status(sts_data) \
372 (((sts_data) >> 4) & 0x0F)
373 #define netxen_get_sts_type(sts_data) \
374 (((sts_data) >> 8) & 0x0F)
375 #define netxen_get_sts_totallength(sts_data) \
376 (((sts_data) >> 12) & 0xFFFF)
377 #define netxen_get_sts_refhandle(sts_data) \
378 (((sts_data) >> 28) & 0xFFFF)
379 #define netxen_get_sts_prot(sts_data) \
380 (((sts_data) >> 44) & 0x0F)
381 #define netxen_get_sts_pkt_offset(sts_data) \
382 (((sts_data) >> 48) & 0x1F)
383 #define netxen_get_sts_desc_cnt(sts_data) \
384 (((sts_data) >> 53) & 0x7)
385 #define netxen_get_sts_opcode(sts_data) \
386 (((sts_data) >> 58) & 0x03F)
387
388 #define netxen_get_lro_sts_refhandle(sts_data) \
389 ((sts_data) & 0x0FFFF)
390 #define netxen_get_lro_sts_length(sts_data) \
391 (((sts_data) >> 16) & 0x0FFFF)
392 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
393 (((sts_data) >> 32) & 0x0FF)
394 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
395 (((sts_data) >> 40) & 0x0FF)
396 #define netxen_get_lro_sts_timestamp(sts_data) \
397 (((sts_data) >> 48) & 0x1)
398 #define netxen_get_lro_sts_type(sts_data) \
399 (((sts_data) >> 49) & 0x7)
400 #define netxen_get_lro_sts_push_flag(sts_data) \
401 (((sts_data) >> 52) & 0x1)
402 #define netxen_get_lro_sts_seq_number(sts_data) \
403 ((sts_data) & 0x0FFFFFFFF)
404 #define netxen_get_lro_sts_mss(sts_data1) \
405 ((sts_data1 >> 32) & 0x0FFFF)
406
407
408 struct status_desc {
409 __le64 status_desc_data[2];
410 } __attribute__ ((aligned(16)));
411
412 /* UNIFIED ROMIMAGE *************************/
413 #define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
414 #define NX_UNI_DIR_SECT_BOOTLD 0x6
415 #define NX_UNI_DIR_SECT_FW 0x7
416
417 /*Offsets */
418 #define NX_UNI_CHIP_REV_OFF 10
419 #define NX_UNI_FLAGS_OFF 11
420 #define NX_UNI_BIOS_VERSION_OFF 12
421 #define NX_UNI_BOOTLD_IDX_OFF 27
422 #define NX_UNI_FIRMWARE_IDX_OFF 29
423
424 struct uni_table_desc{
425 uint32_t findex;
426 uint32_t num_entries;
427 uint32_t entry_size;
428 uint32_t reserved[5];
429 };
430
431 struct uni_data_desc{
432 uint32_t findex;
433 uint32_t size;
434 uint32_t reserved[5];
435 };
436
437 /* UNIFIED ROMIMAGE *************************/
438
439 /* The version of the main data structure */
440 #define NETXEN_BDINFO_VERSION 1
441
442 /* Magic number to let user know flash is programmed */
443 #define NETXEN_BDINFO_MAGIC 0x12345678
444
445 /* Max number of Gig ports on a Phantom board */
446 #define NETXEN_MAX_PORTS 4
447
448 #define NETXEN_BRDTYPE_P1_BD 0x0000
449 #define NETXEN_BRDTYPE_P1_SB 0x0001
450 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
451 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
452
453 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
454 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
455 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
456 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
457 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
458
459 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
460 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
461 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
462
463 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
464 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
465 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
466 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
467 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
468 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
469 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
470 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
471 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
472 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
473 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
474 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
475 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
476 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
477
478 /* Flash memory map */
479 #define NETXEN_CRBINIT_START 0 /* crbinit section */
480 #define NETXEN_BRDCFG_START 0x4000 /* board config */
481 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
482 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
483 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
484 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
485 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
486 #define NETXEN_USER_START 0x3E8000 /* Firmware info */
487 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
488 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
489
490 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
491 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
492 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
493 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
494 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
495 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
496
497 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
498 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
499 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
500
501 #define NX_FW_MIN_SIZE (0x3fffff)
502 #define NX_P2_MN_ROMIMAGE 0
503 #define NX_P3_CT_ROMIMAGE 1
504 #define NX_P3_MN_ROMIMAGE 2
505 #define NX_UNIFIED_ROMIMAGE 3
506 #define NX_FLASH_ROMIMAGE 4
507 #define NX_UNKNOWN_ROMIMAGE 0xff
508
509 #define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin"
510 #define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin"
511 #define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin"
512 #define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
513 #define NX_FLASH_ROMIMAGE_NAME "flash"
514
515 extern char netxen_nic_driver_name[];
516
517 /* Number of status descriptors to handle per interrupt */
518 #define MAX_STATUS_HANDLE (64)
519
520 /*
521 * netxen_skb_frag{} is to contain mapping info for each SG list. This
522 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
523 */
524 struct netxen_skb_frag {
525 u64 dma;
526 u64 length;
527 };
528
529 struct netxen_recv_crb {
530 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
531 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
532 u32 sw_int_mask[NUM_STS_DESC_RINGS];
533 };
534
535 /* Following defines are for the state of the buffers */
536 #define NETXEN_BUFFER_FREE 0
537 #define NETXEN_BUFFER_BUSY 1
538
539 /*
540 * There will be one netxen_buffer per skb packet. These will be
541 * used to save the dma info for pci_unmap_page()
542 */
543 struct netxen_cmd_buffer {
544 struct sk_buff *skb;
545 struct netxen_skb_frag frag_array[MAX_SKB_FRAGS + 1];
546 u32 frag_count;
547 };
548
549 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
550 struct netxen_rx_buffer {
551 struct list_head list;
552 struct sk_buff *skb;
553 u64 dma;
554 u16 ref_handle;
555 u16 state;
556 };
557
558 /* Board types */
559 #define NETXEN_NIC_GBE 0x01
560 #define NETXEN_NIC_XGBE 0x02
561
562 /*
563 * One hardware_context{} per adapter
564 * contains interrupt info as well shared hardware info.
565 */
566 struct netxen_hardware_context {
567 void __iomem *pci_base0;
568 void __iomem *pci_base1;
569 void __iomem *pci_base2;
570 void __iomem *db_base;
571 void __iomem *ocm_win_crb;
572
573 unsigned long db_len;
574 unsigned long pci_len0;
575
576 u32 ocm_win;
577 u32 crb_win;
578
579 rwlock_t crb_lock;
580 spinlock_t mem_lock;
581
582 u8 cut_through;
583 u8 revision_id;
584 u8 pci_func;
585 u8 linkup;
586 u16 port_type;
587 u16 board_type;
588 };
589
590 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
591 #define ETHERNET_FCS_SIZE 4
592
593 struct netxen_adapter_stats {
594 u64 xmitcalled;
595 u64 xmitfinished;
596 u64 rxdropped;
597 u64 txdropped;
598 u64 csummed;
599 u64 rx_pkts;
600 u64 lro_pkts;
601 u64 rxbytes;
602 u64 txbytes;
603 };
604
605 /*
606 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
607 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
608 */
609 struct nx_host_rds_ring {
610 u32 producer;
611 u32 num_desc;
612 u32 dma_size;
613 u32 skb_size;
614 u32 flags;
615 void __iomem *crb_rcv_producer;
616 struct rcv_desc *desc_head;
617 struct netxen_rx_buffer *rx_buf_arr;
618 struct list_head free_list;
619 spinlock_t lock;
620 dma_addr_t phys_addr;
621 };
622
623 struct nx_host_sds_ring {
624 u32 consumer;
625 u32 num_desc;
626 void __iomem *crb_sts_consumer;
627 void __iomem *crb_intr_mask;
628
629 struct status_desc *desc_head;
630 struct netxen_adapter *adapter;
631 struct napi_struct napi;
632 struct list_head free_list[NUM_RCV_DESC_RINGS];
633
634 int irq;
635
636 dma_addr_t phys_addr;
637 char name[IFNAMSIZ+4];
638 };
639
640 struct nx_host_tx_ring {
641 u32 producer;
642 __le32 *hw_consumer;
643 u32 sw_consumer;
644 void __iomem *crb_cmd_producer;
645 void __iomem *crb_cmd_consumer;
646 u32 num_desc;
647
648 struct netdev_queue *txq;
649
650 struct netxen_cmd_buffer *cmd_buf_arr;
651 struct cmd_desc_type0 *desc_head;
652 dma_addr_t phys_addr;
653 };
654
655 /*
656 * Receive context. There is one such structure per instance of the
657 * receive processing. Any state information that is relevant to
658 * the receive, and is must be in this structure. The global data may be
659 * present elsewhere.
660 */
661 struct netxen_recv_context {
662 u32 state;
663 u16 context_id;
664 u16 virt_port;
665
666 struct nx_host_rds_ring *rds_rings;
667 struct nx_host_sds_ring *sds_rings;
668
669 struct netxen_ring_ctx *hwctx;
670 dma_addr_t phys_addr;
671 };
672
673 struct _cdrp_cmd {
674 u32 cmd;
675 u32 arg1;
676 u32 arg2;
677 u32 arg3;
678 };
679
680 struct netxen_cmd_args {
681 struct _cdrp_cmd req;
682 struct _cdrp_cmd rsp;
683 };
684
685 /* New HW context creation */
686
687 #define NX_OS_CRB_RETRY_COUNT 4000
688 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
689 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
690
691 #define NX_CDRP_CLEAR 0x00000000
692 #define NX_CDRP_CMD_BIT 0x80000000
693
694 /*
695 * All responses must have the NX_CDRP_CMD_BIT cleared
696 * in the crb NX_CDRP_CRB_OFFSET.
697 */
698 #define NX_CDRP_FORM_RSP(rsp) (rsp)
699 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
700
701 #define NX_CDRP_RSP_OK 0x00000001
702 #define NX_CDRP_RSP_FAIL 0x00000002
703 #define NX_CDRP_RSP_TIMEOUT 0x00000003
704
705 /*
706 * All commands must have the NX_CDRP_CMD_BIT set in
707 * the crb NX_CDRP_CRB_OFFSET.
708 */
709 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
710 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
711
712 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
713 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
714 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
715 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
716 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
717 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
718 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
719 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
720 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
721 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
722 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
723 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
724 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
725 #define NX_CDRP_CMD_SET_MTU 0x00000012
726 #define NX_CDRP_CMD_READ_PHY 0x00000013
727 #define NX_CDRP_CMD_WRITE_PHY 0x00000014
728 #define NX_CDRP_CMD_READ_HW_REG 0x00000015
729 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
730 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
731 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
732 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
733 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
734 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
735 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
736 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
737 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
738 #define NX_CDRP_CMD_CONFIG_GBE_PORT 0x0000001f
739 #define NX_CDRP_CMD_MAX 0x00000020
740
741 #define NX_RCODE_SUCCESS 0
742 #define NX_RCODE_NO_HOST_MEM 1
743 #define NX_RCODE_NO_HOST_RESOURCE 2
744 #define NX_RCODE_NO_CARD_CRB 3
745 #define NX_RCODE_NO_CARD_MEM 4
746 #define NX_RCODE_NO_CARD_RESOURCE 5
747 #define NX_RCODE_INVALID_ARGS 6
748 #define NX_RCODE_INVALID_ACTION 7
749 #define NX_RCODE_INVALID_STATE 8
750 #define NX_RCODE_NOT_SUPPORTED 9
751 #define NX_RCODE_NOT_PERMITTED 10
752 #define NX_RCODE_NOT_READY 11
753 #define NX_RCODE_DOES_NOT_EXIST 12
754 #define NX_RCODE_ALREADY_EXISTS 13
755 #define NX_RCODE_BAD_SIGNATURE 14
756 #define NX_RCODE_CMD_NOT_IMPL 15
757 #define NX_RCODE_CMD_INVALID 16
758 #define NX_RCODE_TIMEOUT 17
759 #define NX_RCODE_CMD_FAILED 18
760 #define NX_RCODE_MAX_EXCEEDED 19
761 #define NX_RCODE_MAX 20
762
763 #define NX_DESTROY_CTX_RESET 0
764 #define NX_DESTROY_CTX_D3_RESET 1
765 #define NX_DESTROY_CTX_MAX 2
766
767 /*
768 * Capabilities
769 */
770 #define NX_CAP_BIT(class, bit) (1 << bit)
771 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
772 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
773 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
774 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
775 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
776 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
777 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
778 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
779 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
780 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
781 #define NX_CAP0_HW_LRO_MSS NX_CAP_BIT(0, 21)
782
783 /*
784 * Context state
785 */
786 #define NX_HOST_CTX_STATE_FREED 0
787 #define NX_HOST_CTX_STATE_ALLOCATED 1
788 #define NX_HOST_CTX_STATE_ACTIVE 2
789 #define NX_HOST_CTX_STATE_DISABLED 3
790 #define NX_HOST_CTX_STATE_QUIESCED 4
791 #define NX_HOST_CTX_STATE_MAX 5
792
793 /*
794 * Rx context
795 */
796
797 typedef struct {
798 __le64 host_phys_addr; /* Ring base addr */
799 __le32 ring_size; /* Ring entries */
800 __le16 msi_index;
801 __le16 rsvd; /* Padding */
802 } nx_hostrq_sds_ring_t;
803
804 typedef struct {
805 __le64 host_phys_addr; /* Ring base addr */
806 __le64 buff_size; /* Packet buffer size */
807 __le32 ring_size; /* Ring entries */
808 __le32 ring_kind; /* Class of ring */
809 } nx_hostrq_rds_ring_t;
810
811 typedef struct {
812 __le64 host_rsp_dma_addr; /* Response dma'd here */
813 __le32 capabilities[4]; /* Flag bit vector */
814 __le32 host_int_crb_mode; /* Interrupt crb usage */
815 __le32 host_rds_crb_mode; /* RDS crb usage */
816 /* These ring offsets are relative to data[0] below */
817 __le32 rds_ring_offset; /* Offset to RDS config */
818 __le32 sds_ring_offset; /* Offset to SDS config */
819 __le16 num_rds_rings; /* Count of RDS rings */
820 __le16 num_sds_rings; /* Count of SDS rings */
821 __le16 rsvd1; /* Padding */
822 __le16 rsvd2; /* Padding */
823 u8 reserved[128]; /* reserve space for future expansion*/
824 /* MUST BE 64-bit aligned.
825 The following is packed:
826 - N hostrq_rds_rings
827 - N hostrq_sds_rings */
828 char data[0];
829 } nx_hostrq_rx_ctx_t;
830
831 typedef struct {
832 __le32 host_producer_crb; /* Crb to use */
833 __le32 rsvd1; /* Padding */
834 } nx_cardrsp_rds_ring_t;
835
836 typedef struct {
837 __le32 host_consumer_crb; /* Crb to use */
838 __le32 interrupt_crb; /* Crb to use */
839 } nx_cardrsp_sds_ring_t;
840
841 typedef struct {
842 /* These ring offsets are relative to data[0] below */
843 __le32 rds_ring_offset; /* Offset to RDS config */
844 __le32 sds_ring_offset; /* Offset to SDS config */
845 __le32 host_ctx_state; /* Starting State */
846 __le32 num_fn_per_port; /* How many PCI fn share the port */
847 __le16 num_rds_rings; /* Count of RDS rings */
848 __le16 num_sds_rings; /* Count of SDS rings */
849 __le16 context_id; /* Handle for context */
850 u8 phys_port; /* Physical id of port */
851 u8 virt_port; /* Virtual/Logical id of port */
852 u8 reserved[128]; /* save space for future expansion */
853 /* MUST BE 64-bit aligned.
854 The following is packed:
855 - N cardrsp_rds_rings
856 - N cardrs_sds_rings */
857 char data[0];
858 } nx_cardrsp_rx_ctx_t;
859
860 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
861 (sizeof(HOSTRQ_RX) + \
862 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
863 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
864
865 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
866 (sizeof(CARDRSP_RX) + \
867 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
868 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
869
870 /*
871 * Tx context
872 */
873
874 typedef struct {
875 __le64 host_phys_addr; /* Ring base addr */
876 __le32 ring_size; /* Ring entries */
877 __le32 rsvd; /* Padding */
878 } nx_hostrq_cds_ring_t;
879
880 typedef struct {
881 __le64 host_rsp_dma_addr; /* Response dma'd here */
882 __le64 cmd_cons_dma_addr; /* */
883 __le64 dummy_dma_addr; /* */
884 __le32 capabilities[4]; /* Flag bit vector */
885 __le32 host_int_crb_mode; /* Interrupt crb usage */
886 __le32 rsvd1; /* Padding */
887 __le16 rsvd2; /* Padding */
888 __le16 interrupt_ctl;
889 __le16 msi_index;
890 __le16 rsvd3; /* Padding */
891 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
892 u8 reserved[128]; /* future expansion */
893 } nx_hostrq_tx_ctx_t;
894
895 typedef struct {
896 __le32 host_producer_crb; /* Crb to use */
897 __le32 interrupt_crb; /* Crb to use */
898 } nx_cardrsp_cds_ring_t;
899
900 typedef struct {
901 __le32 host_ctx_state; /* Starting state */
902 __le16 context_id; /* Handle for context */
903 u8 phys_port; /* Physical id of port */
904 u8 virt_port; /* Virtual/Logical id of port */
905 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
906 u8 reserved[128]; /* future expansion */
907 } nx_cardrsp_tx_ctx_t;
908
909 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
910 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
911
912 /* CRB */
913
914 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
915 #define NX_HOST_RDS_CRB_MODE_SHARED 1
916 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
917 #define NX_HOST_RDS_CRB_MODE_MAX 3
918
919 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
920 #define NX_HOST_INT_CRB_MODE_SHARED 1
921 #define NX_HOST_INT_CRB_MODE_NORX 2
922 #define NX_HOST_INT_CRB_MODE_NOTX 3
923 #define NX_HOST_INT_CRB_MODE_NORXTX 4
924
925
926 /* MAC */
927
928 #define MC_COUNT_P2 16
929 #define MC_COUNT_P3 38
930
931 #define NETXEN_MAC_NOOP 0
932 #define NETXEN_MAC_ADD 1
933 #define NETXEN_MAC_DEL 2
934
935 typedef struct nx_mac_list_s {
936 struct list_head list;
937 uint8_t mac_addr[ETH_ALEN+2];
938 } nx_mac_list_t;
939
940 struct nx_ip_list {
941 struct list_head list;
942 __be32 ip_addr;
943 bool master;
944 };
945
946 /*
947 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
948 * adjusted based on configured MTU.
949 */
950 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
951 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
952 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
953 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
954
955 #define NETXEN_NIC_INTR_DEFAULT 0x04
956
957 typedef union {
958 struct {
959 uint16_t rx_packets;
960 uint16_t rx_time_us;
961 uint16_t tx_packets;
962 uint16_t tx_time_us;
963 } data;
964 uint64_t word;
965 } nx_nic_intr_coalesce_data_t;
966
967 typedef struct {
968 uint16_t stats_time_us;
969 uint16_t rate_sample_time;
970 uint16_t flags;
971 uint16_t rsvd_1;
972 uint32_t low_threshold;
973 uint32_t high_threshold;
974 nx_nic_intr_coalesce_data_t normal;
975 nx_nic_intr_coalesce_data_t low;
976 nx_nic_intr_coalesce_data_t high;
977 nx_nic_intr_coalesce_data_t irq;
978 } nx_nic_intr_coalesce_t;
979
980 #define NX_HOST_REQUEST 0x13
981 #define NX_NIC_REQUEST 0x14
982
983 #define NX_MAC_EVENT 0x1
984
985 #define NX_IP_UP 2
986 #define NX_IP_DOWN 3
987
988 /*
989 * Driver --> Firmware
990 */
991 #define NX_NIC_H2C_OPCODE_START 0
992 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
993 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
994 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
995 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
996 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
997 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
998 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
999 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1000 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1001 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1002 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1003 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1004 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1005 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1006 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1007 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1008 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1009 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1010 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1011 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1012 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1013 #define NX_NIC_C2C_OPCODE 22
1014 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1015 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1016 #define NX_NIC_H2C_OPCODE_LAST 25
1017
1018 /*
1019 * Firmware --> Driver
1020 */
1021
1022 #define NX_NIC_C2H_OPCODE_START 128
1023 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1024 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1025 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1026 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1027 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1028 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1029 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1030 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1031 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1032 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1033 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1034 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1035 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1036 #define NX_NIC_C2H_OPCODE_LAST 142
1037
1038 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1039 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1040 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1041
1042 #define NX_NIC_LRO_REQUEST_FIRST 0
1043 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1044 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1045 #define NX_NIC_LRO_REQUEST_TIMER 3
1046 #define NX_NIC_LRO_REQUEST_CLEANUP 4
1047 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1048 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1049 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1050 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1051 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1052 #define NX_TOE_LRO_REQUEST_TIMER 10
1053 #define NX_NIC_LRO_REQUEST_LAST 11
1054
1055 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1056 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1057 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1058 #define NX_FW_CAPABILITY_BDG (1 << 8)
1059 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1060 #define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1061 #define NX_FW_CAPABILITY_GBE_LINK_CFG (1 << 11)
1062 #define NX_FW_CAPABILITY_MORE_CAPS (1 << 31)
1063 #define NX_FW_CAPABILITY_2_LRO_MAX_TCP_SEG (1 << 2)
1064
1065 /* module types */
1066 #define LINKEVENT_MODULE_NOT_PRESENT 1
1067 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1068 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1069 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1070 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1071 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1072 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1073 #define LINKEVENT_MODULE_TWINAX 8
1074
1075 #define LINKSPEED_10GBPS 10000
1076 #define LINKSPEED_1GBPS 1000
1077 #define LINKSPEED_100MBPS 100
1078 #define LINKSPEED_10MBPS 10
1079
1080 #define LINKSPEED_ENCODED_10MBPS 0
1081 #define LINKSPEED_ENCODED_100MBPS 1
1082 #define LINKSPEED_ENCODED_1GBPS 2
1083
1084 #define LINKEVENT_AUTONEG_DISABLED 0
1085 #define LINKEVENT_AUTONEG_ENABLED 1
1086
1087 #define LINKEVENT_HALF_DUPLEX 0
1088 #define LINKEVENT_FULL_DUPLEX 1
1089
1090 #define LINKEVENT_LINKSPEED_MBPS 0
1091 #define LINKEVENT_LINKSPEED_ENCODED 1
1092
1093 #define AUTO_FW_RESET_ENABLED 0xEF10AF12
1094 #define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1095
1096 /* firmware response header:
1097 * 63:58 - message type
1098 * 57:56 - owner
1099 * 55:53 - desc count
1100 * 52:48 - reserved
1101 * 47:40 - completion id
1102 * 39:32 - opcode
1103 * 31:16 - error code
1104 * 15:00 - reserved
1105 */
1106 #define netxen_get_nic_msgtype(msg_hdr) \
1107 ((msg_hdr >> 58) & 0x3F)
1108 #define netxen_get_nic_msg_compid(msg_hdr) \
1109 ((msg_hdr >> 40) & 0xFF)
1110 #define netxen_get_nic_msg_opcode(msg_hdr) \
1111 ((msg_hdr >> 32) & 0xFF)
1112 #define netxen_get_nic_msg_errcode(msg_hdr) \
1113 ((msg_hdr >> 16) & 0xFFFF)
1114
1115 typedef struct {
1116 union {
1117 struct {
1118 u64 hdr;
1119 u64 body[7];
1120 };
1121 u64 words[8];
1122 };
1123 } nx_fw_msg_t;
1124
1125 typedef struct {
1126 __le64 qhdr;
1127 __le64 req_hdr;
1128 __le64 words[6];
1129 } nx_nic_req_t;
1130
1131 typedef struct {
1132 u8 op;
1133 u8 tag;
1134 u8 mac_addr[6];
1135 } nx_mac_req_t;
1136
1137 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1138
1139 #define NETXEN_NIC_MSI_ENABLED 0x02
1140 #define NETXEN_NIC_MSIX_ENABLED 0x04
1141 #define NETXEN_NIC_LRO_ENABLED 0x08
1142 #define NETXEN_NIC_LRO_DISABLED 0x00
1143 #define NETXEN_NIC_BRIDGE_ENABLED 0X10
1144 #define NETXEN_NIC_DIAG_ENABLED 0x20
1145 #define NETXEN_FW_RESET_OWNER 0x40
1146 #define NETXEN_FW_MSS_CAP 0x80
1147 #define NETXEN_IS_MSI_FAMILY(adapter) \
1148 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1149
1150 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1151 #define NETXEN_MSIX_TBL_SPACE 8192
1152 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1153
1154 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1155
1156 #define NETXEN_ADAPTER_UP_MAGIC 777
1157 #define NETXEN_NIC_PEG_TUNE 0
1158
1159 #define __NX_FW_ATTACHED 0
1160 #define __NX_DEV_UP 1
1161 #define __NX_RESETTING 2
1162
1163 /* Mini Coredump FW supported version */
1164 #define NX_MD_SUPPORT_MAJOR 4
1165 #define NX_MD_SUPPORT_MINOR 0
1166 #define NX_MD_SUPPORT_SUBVERSION 579
1167
1168 #define LSW(x) ((uint16_t)(x))
1169 #define LSD(x) ((uint32_t)((uint64_t)(x)))
1170 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
1171
1172 /* Mini Coredump mask level */
1173 #define NX_DUMP_MASK_MIN 0x03
1174 #define NX_DUMP_MASK_DEF 0x1f
1175 #define NX_DUMP_MASK_MAX 0xff
1176
1177 /* Mini Coredump CDRP commands */
1178 #define NX_CDRP_CMD_TEMP_SIZE 0x0000002f
1179 #define NX_CDRP_CMD_GET_TEMP_HDR 0x00000030
1180
1181
1182 #define NX_DUMP_STATE_ARRAY_LEN 16
1183 #define NX_DUMP_CAP_SIZE_ARRAY_LEN 8
1184
1185 /* Mini Coredump sysfs entries flags*/
1186 #define NX_FORCE_FW_DUMP_KEY 0xdeadfeed
1187 #define NX_ENABLE_FW_DUMP 0xaddfeed
1188 #define NX_DISABLE_FW_DUMP 0xbadfeed
1189 #define NX_FORCE_FW_RESET 0xdeaddead
1190
1191
1192 /* Flash read/write address */
1193 #define NX_FW_DUMP_REG1 0x00130060
1194 #define NX_FW_DUMP_REG2 0x001e0000
1195 #define NX_FLASH_SEM2_LK 0x0013C010
1196 #define NX_FLASH_SEM2_ULK 0x0013C014
1197 #define NX_FLASH_LOCK_ID 0x001B2100
1198 #define FLASH_ROM_WINDOW 0x42110030
1199 #define FLASH_ROM_DATA 0x42150000
1200
1201 /* Mini Coredump register read/write routine */
1202 #define NX_RD_DUMP_REG(addr, bar0, data) do { \
1203 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
1204 NX_FW_DUMP_REG1)); \
1205 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \
1206 *data = readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + \
1207 LSW(addr))); \
1208 } while (0)
1209
1210 #define NX_WR_DUMP_REG(addr, bar0, data) do { \
1211 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
1212 NX_FW_DUMP_REG1)); \
1213 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \
1214 writel(data, (void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr)));\
1215 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr))); \
1216 } while (0)
1217
1218
1219 /*
1220 Entry Type Defines
1221 */
1222
1223 #define RDNOP 0
1224 #define RDCRB 1
1225 #define RDMUX 2
1226 #define QUEUE 3
1227 #define BOARD 4
1228 #define RDSRE 5
1229 #define RDOCM 6
1230 #define PREGS 7
1231 #define L1DTG 8
1232 #define L1ITG 9
1233 #define CACHE 10
1234
1235 #define L1DAT 11
1236 #define L1INS 12
1237 #define RDSTK 13
1238 #define RDCON 14
1239
1240 #define L2DTG 21
1241 #define L2ITG 22
1242 #define L2DAT 23
1243 #define L2INS 24
1244 #define RDOC3 25
1245
1246 #define MEMBK 32
1247
1248 #define RDROM 71
1249 #define RDMEM 72
1250 #define RDMN 73
1251
1252 #define INFOR 81
1253 #define CNTRL 98
1254
1255 #define TLHDR 99
1256 #define RDEND 255
1257
1258 #define PRIMQ 103
1259 #define SQG2Q 104
1260 #define SQG3Q 105
1261
1262 /*
1263 * Opcodes for Control Entries.
1264 * These Flags are bit fields.
1265 */
1266 #define NX_DUMP_WCRB 0x01
1267 #define NX_DUMP_RWCRB 0x02
1268 #define NX_DUMP_ANDCRB 0x04
1269 #define NX_DUMP_ORCRB 0x08
1270 #define NX_DUMP_POLLCRB 0x10
1271 #define NX_DUMP_RD_SAVE 0x20
1272 #define NX_DUMP_WRT_SAVED 0x40
1273 #define NX_DUMP_MOD_SAVE_ST 0x80
1274
1275 /* Driver Flags */
1276 #define NX_DUMP_SKIP 0x80 /* driver skipped this entry */
1277 #define NX_DUMP_SIZE_ERR 0x40 /*entry size vs capture size mismatch*/
1278
1279 #define NX_PCI_READ_32(ADDR) readl((ADDR))
1280 #define NX_PCI_WRITE_32(DATA, ADDR) writel(DATA, (ADDR))
1281
1282
1283
1284 struct netxen_minidump {
1285 u32 pos; /* position in the dump buffer */
1286 u8 fw_supports_md; /* FW supports Mini cordump */
1287 u8 has_valid_dump; /* indicates valid dump */
1288 u8 md_capture_mask; /* driver capture mask */
1289 u8 md_enabled; /* Turn Mini Coredump on/off */
1290 u32 md_dump_size; /* Total FW Mini Coredump size */
1291 u32 md_capture_size; /* FW dump capture size */
1292 u32 md_template_size; /* FW template size */
1293 u32 md_template_ver; /* FW template version */
1294 u64 md_timestamp; /* FW Mini dump timestamp */
1295 void *md_template; /* FW template will be stored */
1296 void *md_capture_buff; /* FW dump will be stored */
1297 };
1298
1299
1300
1301 struct netxen_minidump_template_hdr {
1302 u32 entry_type;
1303 u32 first_entry_offset;
1304 u32 size_of_template;
1305 u32 capture_mask;
1306 u32 num_of_entries;
1307 u32 version;
1308 u32 driver_timestamp;
1309 u32 checksum;
1310 u32 driver_capture_mask;
1311 u32 driver_info_word2;
1312 u32 driver_info_word3;
1313 u32 driver_info_word4;
1314 u32 saved_state_array[NX_DUMP_STATE_ARRAY_LEN];
1315 u32 capture_size_array[NX_DUMP_CAP_SIZE_ARRAY_LEN];
1316 u32 rsvd[];
1317 };
1318
1319 /* Common Entry Header: Common to All Entry Types */
1320 /*
1321 * Driver Code is for driver to write some info about the entry.
1322 * Currently not used.
1323 */
1324
1325 struct netxen_common_entry_hdr {
1326 u32 entry_type;
1327 u32 entry_size;
1328 u32 entry_capture_size;
1329 union {
1330 struct {
1331 u8 entry_capture_mask;
1332 u8 entry_code;
1333 u8 driver_code;
1334 u8 driver_flags;
1335 };
1336 u32 entry_ctrl_word;
1337 };
1338 };
1339
1340
1341 /* Generic Entry Including Header */
1342 struct netxen_minidump_entry {
1343 struct netxen_common_entry_hdr hdr;
1344 u32 entry_data00;
1345 u32 entry_data01;
1346 u32 entry_data02;
1347 u32 entry_data03;
1348 u32 entry_data04;
1349 u32 entry_data05;
1350 u32 entry_data06;
1351 u32 entry_data07;
1352 };
1353
1354 /* Read ROM Header */
1355 struct netxen_minidump_entry_rdrom {
1356 struct netxen_common_entry_hdr h;
1357 union {
1358 struct {
1359 u32 select_addr_reg;
1360 };
1361 u32 rsvd_0;
1362 };
1363 union {
1364 struct {
1365 u8 addr_stride;
1366 u8 addr_cnt;
1367 u16 data_size;
1368 };
1369 u32 rsvd_1;
1370 };
1371 union {
1372 struct {
1373 u32 op_count;
1374 };
1375 u32 rsvd_2;
1376 };
1377 union {
1378 struct {
1379 u32 read_addr_reg;
1380 };
1381 u32 rsvd_3;
1382 };
1383 union {
1384 struct {
1385 u32 write_mask;
1386 };
1387 u32 rsvd_4;
1388 };
1389 union {
1390 struct {
1391 u32 read_mask;
1392 };
1393 u32 rsvd_5;
1394 };
1395 u32 read_addr;
1396 u32 read_data_size;
1397 };
1398
1399
1400 /* Read CRB and Control Entry Header */
1401 struct netxen_minidump_entry_crb {
1402 struct netxen_common_entry_hdr h;
1403 u32 addr;
1404 union {
1405 struct {
1406 u8 addr_stride;
1407 u8 state_index_a;
1408 u16 poll_timeout;
1409 };
1410 u32 addr_cntrl;
1411 };
1412 u32 data_size;
1413 u32 op_count;
1414 union {
1415 struct {
1416 u8 opcode;
1417 u8 state_index_v;
1418 u8 shl;
1419 u8 shr;
1420 };
1421 u32 control_value;
1422 };
1423 u32 value_1;
1424 u32 value_2;
1425 u32 value_3;
1426 };
1427
1428 /* Read Memory and MN Header */
1429 struct netxen_minidump_entry_rdmem {
1430 struct netxen_common_entry_hdr h;
1431 union {
1432 struct {
1433 u32 select_addr_reg;
1434 };
1435 u32 rsvd_0;
1436 };
1437 union {
1438 struct {
1439 u8 addr_stride;
1440 u8 addr_cnt;
1441 u16 data_size;
1442 };
1443 u32 rsvd_1;
1444 };
1445 union {
1446 struct {
1447 u32 op_count;
1448 };
1449 u32 rsvd_2;
1450 };
1451 union {
1452 struct {
1453 u32 read_addr_reg;
1454 };
1455 u32 rsvd_3;
1456 };
1457 union {
1458 struct {
1459 u32 cntrl_addr_reg;
1460 };
1461 u32 rsvd_4;
1462 };
1463 union {
1464 struct {
1465 u8 wr_byte0;
1466 u8 wr_byte1;
1467 u8 poll_mask;
1468 u8 poll_cnt;
1469 };
1470 u32 rsvd_5;
1471 };
1472 u32 read_addr;
1473 u32 read_data_size;
1474 };
1475
1476 /* Read Cache L1 and L2 Header */
1477 struct netxen_minidump_entry_cache {
1478 struct netxen_common_entry_hdr h;
1479 u32 tag_reg_addr;
1480 union {
1481 struct {
1482 u16 tag_value_stride;
1483 u16 init_tag_value;
1484 };
1485 u32 select_addr_cntrl;
1486 };
1487 u32 data_size;
1488 u32 op_count;
1489 u32 control_addr;
1490 union {
1491 struct {
1492 u16 write_value;
1493 u8 poll_mask;
1494 u8 poll_wait;
1495 };
1496 u32 control_value;
1497 };
1498 u32 read_addr;
1499 union {
1500 struct {
1501 u8 read_addr_stride;
1502 u8 read_addr_cnt;
1503 u16 rsvd_1;
1504 };
1505 u32 read_addr_cntrl;
1506 };
1507 };
1508
1509 /* Read OCM Header */
1510 struct netxen_minidump_entry_rdocm {
1511 struct netxen_common_entry_hdr h;
1512 u32 rsvd_0;
1513 union {
1514 struct {
1515 u32 rsvd_1;
1516 };
1517 u32 select_addr_cntrl;
1518 };
1519 u32 data_size;
1520 u32 op_count;
1521 u32 rsvd_2;
1522 u32 rsvd_3;
1523 u32 read_addr;
1524 union {
1525 struct {
1526 u32 read_addr_stride;
1527 };
1528 u32 read_addr_cntrl;
1529 };
1530 };
1531
1532 /* Read MUX Header */
1533 struct netxen_minidump_entry_mux {
1534 struct netxen_common_entry_hdr h;
1535 u32 select_addr;
1536 union {
1537 struct {
1538 u32 rsvd_0;
1539 };
1540 u32 select_addr_cntrl;
1541 };
1542 u32 data_size;
1543 u32 op_count;
1544 u32 select_value;
1545 u32 select_value_stride;
1546 u32 read_addr;
1547 u32 rsvd_1;
1548 };
1549
1550 /* Read Queue Header */
1551 struct netxen_minidump_entry_queue {
1552 struct netxen_common_entry_hdr h;
1553 u32 select_addr;
1554 union {
1555 struct {
1556 u16 queue_id_stride;
1557 u16 rsvd_0;
1558 };
1559 u32 select_addr_cntrl;
1560 };
1561 u32 data_size;
1562 u32 op_count;
1563 u32 rsvd_1;
1564 u32 rsvd_2;
1565 u32 read_addr;
1566 union {
1567 struct {
1568 u8 read_addr_stride;
1569 u8 read_addr_cnt;
1570 u16 rsvd_3;
1571 };
1572 u32 read_addr_cntrl;
1573 };
1574 };
1575
1576 struct netxen_dummy_dma {
1577 void *addr;
1578 dma_addr_t phys_addr;
1579 };
1580
1581 struct netxen_adapter {
1582 struct netxen_hardware_context ahw;
1583
1584 struct net_device *netdev;
1585 struct pci_dev *pdev;
1586 struct list_head mac_list;
1587 struct list_head ip_list;
1588
1589 spinlock_t tx_clean_lock;
1590
1591 u16 num_txd;
1592 u16 num_rxd;
1593 u16 num_jumbo_rxd;
1594 u16 num_lro_rxd;
1595
1596 u8 max_rds_rings;
1597 u8 max_sds_rings;
1598 u8 driver_mismatch;
1599 u8 msix_supported;
1600 u8 __pad;
1601 u8 pci_using_dac;
1602 u8 portnum;
1603 u8 physical_port;
1604
1605 u8 mc_enabled;
1606 u8 max_mc_count;
1607 u8 rss_supported;
1608 u8 link_changed;
1609 u8 fw_wait_cnt;
1610 u8 fw_fail_cnt;
1611 u8 tx_timeo_cnt;
1612 u8 need_fw_reset;
1613
1614 u8 has_link_events;
1615 u8 fw_type;
1616 u16 tx_context_id;
1617 u16 mtu;
1618 u16 is_up;
1619
1620 u16 link_speed;
1621 u16 link_duplex;
1622 u16 link_autoneg;
1623 u16 module_type;
1624
1625 u32 capabilities;
1626 u32 flags;
1627 u32 irq;
1628 u32 temp;
1629
1630 u32 int_vec_bit;
1631 u32 heartbit;
1632
1633 u8 mac_addr[ETH_ALEN];
1634
1635 struct netxen_adapter_stats stats;
1636
1637 struct netxen_recv_context recv_ctx;
1638 struct nx_host_tx_ring *tx_ring;
1639
1640 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1641 int (*set_mtu) (struct netxen_adapter *, int);
1642 int (*set_promisc) (struct netxen_adapter *, u32);
1643 void (*set_multi) (struct net_device *);
1644 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1645 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1646 int (*init_port) (struct netxen_adapter *, int);
1647 int (*stop_port) (struct netxen_adapter *);
1648
1649 u32 (*crb_read)(struct netxen_adapter *, ulong);
1650 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1651
1652 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1653 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1654
1655 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1656
1657 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1658 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1659
1660 void __iomem *tgt_mask_reg;
1661 void __iomem *pci_int_reg;
1662 void __iomem *tgt_status_reg;
1663 void __iomem *crb_int_state_reg;
1664 void __iomem *isr_int_vec;
1665
1666 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1667
1668 struct netxen_dummy_dma dummy_dma;
1669
1670 struct delayed_work fw_work;
1671
1672 struct work_struct tx_timeout_task;
1673
1674 nx_nic_intr_coalesce_t coal;
1675
1676 unsigned long state;
1677 __le32 file_prd_off; /*File fw product offset*/
1678 u32 fw_version;
1679 const struct firmware *fw;
1680 struct netxen_minidump mdump; /* mdump ptr */
1681 int fw_mdump_rdy; /* for mdump ready */
1682 };
1683
1684 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1685 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1686
1687 #define NXRD32(adapter, off) \
1688 (adapter->crb_read(adapter, off))
1689 #define NXWR32(adapter, off, val) \
1690 (adapter->crb_write(adapter, off, val))
1691 #define NXRDIO(adapter, addr) \
1692 (adapter->io_read(adapter, addr))
1693 #define NXWRIO(adapter, addr, val) \
1694 (adapter->io_write(adapter, addr, val))
1695
1696 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1697 void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1698
1699 #define netxen_rom_lock(a) \
1700 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1701 #define netxen_rom_unlock(a) \
1702 netxen_pcie_sem_unlock((a), 2)
1703 #define netxen_phy_lock(a) \
1704 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1705 #define netxen_phy_unlock(a) \
1706 netxen_pcie_sem_unlock((a), 3)
1707 #define netxen_api_lock(a) \
1708 netxen_pcie_sem_lock((a), 5, 0)
1709 #define netxen_api_unlock(a) \
1710 netxen_pcie_sem_unlock((a), 5)
1711 #define netxen_sw_lock(a) \
1712 netxen_pcie_sem_lock((a), 6, 0)
1713 #define netxen_sw_unlock(a) \
1714 netxen_pcie_sem_unlock((a), 6)
1715 #define crb_win_lock(a) \
1716 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1717 #define crb_win_unlock(a) \
1718 netxen_pcie_sem_unlock((a), 7)
1719
1720 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1721 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1722
1723 /* Functions from netxen_nic_init.c */
1724 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1725 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1726
1727 int netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter);
1728 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1729 int netxen_load_firmware(struct netxen_adapter *adapter);
1730 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1731 void netxen_request_firmware(struct netxen_adapter *adapter);
1732 void netxen_release_firmware(struct netxen_adapter *adapter);
1733 int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1734
1735 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1736 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1737 u8 *bytes, size_t size);
1738 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1739 u8 *bytes, size_t size);
1740 int netxen_flash_unlock(struct netxen_adapter *adapter);
1741 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1742 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1743 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1744 void netxen_halt_pegs(struct netxen_adapter *adapter);
1745
1746 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1747
1748 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1749 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1750
1751 void netxen_setup_hwops(struct netxen_adapter *adapter);
1752 void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1753
1754 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1755 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1756
1757 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1758 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1759
1760 int netxen_init_firmware(struct netxen_adapter *adapter);
1761 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1762 void netxen_watchdog_task(struct work_struct *work);
1763 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1764 struct nx_host_rds_ring *rds_ring);
1765 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1766 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1767
1768 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1769 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1770 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1771 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd);
1772 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1773 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1774 void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *);
1775 void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64);
1776
1777 int nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
1778 u32 speed, u32 duplex, u32 autoneg);
1779 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1780 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1781 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1782 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1783 int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1784 int netxen_setup_minidump(struct netxen_adapter *adapter);
1785 void netxen_dump_fw(struct netxen_adapter *adapter);
1786 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1787 struct nx_host_tx_ring *tx_ring);
1788
1789 /* Functions from netxen_nic_main.c */
1790 int netxen_nic_reset_context(struct netxen_adapter *);
1791
1792 int nx_dev_request_reset(struct netxen_adapter *adapter);
1793
1794 /*
1795 * NetXen Board information
1796 */
1797
1798 #define NETXEN_MAX_SHORT_NAME 32
1799 struct netxen_brdinfo {
1800 int brdtype; /* type of board */
1801 long ports; /* max no of physical ports */
1802 char short_name[NETXEN_MAX_SHORT_NAME];
1803 };
1804
1805 struct netxen_dimm_cfg {
1806 u8 presence;
1807 u8 mem_type;
1808 u8 dimm_type;
1809 u32 size;
1810 };
1811
1812 static const struct netxen_brdinfo netxen_boards[] = {
1813 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1814 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1815 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1816 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1817 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1818 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1819 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1820 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1821 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1822 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1823 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1824 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1825 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1826 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1827 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1828 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1829 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1830 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1831 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1832 };
1833
1834 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1835
1836 static inline int netxen_nic_get_brd_name_by_type(u32 type, char *name)
1837 {
1838 int i, found = 0;
1839 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1840 if (netxen_boards[i].brdtype == type) {
1841 strcpy(name, netxen_boards[i].short_name);
1842 found = 1;
1843 break;
1844 }
1845 }
1846
1847 if (!found) {
1848 strcpy(name, "Unknown");
1849 return -EINVAL;
1850 }
1851
1852 return 0;
1853 }
1854
1855 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1856 {
1857 smp_mb();
1858 return find_diff_among(tx_ring->producer,
1859 tx_ring->sw_consumer, tx_ring->num_desc);
1860
1861 }
1862
1863 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1864 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1865 void netxen_change_ringparam(struct netxen_adapter *adapter);
1866 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1867
1868 extern const struct ethtool_ops netxen_nic_ethtool_ops;
1869
1870 #endif /* __NETXEN_NIC_H_ */
Linux with added FPC-III support