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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
blobd2f5855b2ea7928700a91ffb2312a15a456d901e
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
5 */
6
7 #include <linux/types.h>
8 #include <asm/byteorder.h>
9 #include <linux/io.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/mutex.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/vmalloc.h>
19 #include <linux/etherdevice.h>
20 #include <linux/qed/qed_chain.h>
21 #include <linux/qed/qed_if.h>
22 #include "qed.h"
23 #include "qed_cxt.h"
24 #include "qed_dcbx.h"
25 #include "qed_dev_api.h"
26 #include "qed_fcoe.h"
27 #include "qed_hsi.h"
28 #include "qed_hw.h"
29 #include "qed_init_ops.h"
30 #include "qed_int.h"
31 #include "qed_iscsi.h"
32 #include "qed_ll2.h"
33 #include "qed_mcp.h"
34 #include "qed_ooo.h"
35 #include "qed_reg_addr.h"
36 #include "qed_sp.h"
37 #include "qed_sriov.h"
38 #include "qed_vf.h"
39 #include "qed_rdma.h"
40
41 static DEFINE_SPINLOCK(qm_lock);
42
43 /******************** Doorbell Recovery *******************/
44 /* The doorbell recovery mechanism consists of a list of entries which represent
45 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
46 * entity needs to register with the mechanism and provide the parameters
47 * describing it's doorbell, including a location where last used doorbell data
48 * can be found. The doorbell execute function will traverse the list and
49 * doorbell all of the registered entries.
50 */
51 struct qed_db_recovery_entry {
52 struct list_head list_entry;
53 void __iomem *db_addr;
54 void *db_data;
55 enum qed_db_rec_width db_width;
56 enum qed_db_rec_space db_space;
57 u8 hwfn_idx;
58 };
59
60 /* Display a single doorbell recovery entry */
61 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
62 struct qed_db_recovery_entry *db_entry,
63 char *action)
64 {
65 DP_VERBOSE(p_hwfn,
66 QED_MSG_SPQ,
67 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
68 action,
69 db_entry,
70 db_entry->db_addr,
71 db_entry->db_data,
72 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
73 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
74 db_entry->hwfn_idx);
75 }
76
77 /* Doorbell address sanity (address within doorbell bar range) */
78 static bool qed_db_rec_sanity(struct qed_dev *cdev,
79 void __iomem *db_addr,
80 enum qed_db_rec_width db_width,
81 void *db_data)
82 {
83 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
84
85 /* Make sure doorbell address is within the doorbell bar */
86 if (db_addr < cdev->doorbells ||
87 (u8 __iomem *)db_addr + width >
88 (u8 __iomem *)cdev->doorbells + cdev->db_size) {
89 WARN(true,
90 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
91 db_addr,
92 cdev->doorbells,
93 (u8 __iomem *)cdev->doorbells + cdev->db_size);
94 return false;
95 }
96
97 /* ake sure doorbell data pointer is not null */
98 if (!db_data) {
99 WARN(true, "Illegal doorbell data pointer: %p", db_data);
100 return false;
101 }
102
103 return true;
104 }
105
106 /* Find hwfn according to the doorbell address */
107 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
108 void __iomem *db_addr)
109 {
110 struct qed_hwfn *p_hwfn;
111
112 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
113 if (cdev->num_hwfns > 1)
114 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
115 &cdev->hwfns[0] : &cdev->hwfns[1];
116 else
117 p_hwfn = QED_LEADING_HWFN(cdev);
118
119 return p_hwfn;
120 }
121
122 /* Add a new entry to the doorbell recovery mechanism */
123 int qed_db_recovery_add(struct qed_dev *cdev,
124 void __iomem *db_addr,
125 void *db_data,
126 enum qed_db_rec_width db_width,
127 enum qed_db_rec_space db_space)
128 {
129 struct qed_db_recovery_entry *db_entry;
130 struct qed_hwfn *p_hwfn;
131
132 /* Shortcircuit VFs, for now */
133 if (IS_VF(cdev)) {
134 DP_VERBOSE(cdev,
135 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
136 return 0;
137 }
138
139 /* Sanitize doorbell address */
140 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
141 return -EINVAL;
142
143 /* Obtain hwfn from doorbell address */
144 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
145
146 /* Create entry */
147 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
148 if (!db_entry) {
149 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
150 return -ENOMEM;
151 }
152
153 /* Populate entry */
154 db_entry->db_addr = db_addr;
155 db_entry->db_data = db_data;
156 db_entry->db_width = db_width;
157 db_entry->db_space = db_space;
158 db_entry->hwfn_idx = p_hwfn->my_id;
159
160 /* Display */
161 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
162
163 /* Protect the list */
164 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
165 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
166 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
167
168 return 0;
169 }
170
171 /* Remove an entry from the doorbell recovery mechanism */
172 int qed_db_recovery_del(struct qed_dev *cdev,
173 void __iomem *db_addr, void *db_data)
174 {
175 struct qed_db_recovery_entry *db_entry = NULL;
176 struct qed_hwfn *p_hwfn;
177 int rc = -EINVAL;
178
179 /* Shortcircuit VFs, for now */
180 if (IS_VF(cdev)) {
181 DP_VERBOSE(cdev,
182 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
183 return 0;
184 }
185
186 /* Obtain hwfn from doorbell address */
187 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
188
189 /* Protect the list */
190 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
191 list_for_each_entry(db_entry,
192 &p_hwfn->db_recovery_info.list, list_entry) {
193 /* search according to db_data addr since db_addr is not unique (roce) */
194 if (db_entry->db_data == db_data) {
195 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
196 list_del(&db_entry->list_entry);
197 rc = 0;
198 break;
199 }
200 }
201
202 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
203
204 if (rc == -EINVAL)
205
206 DP_NOTICE(p_hwfn,
207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
208 db_data, db_addr);
209 else
210 kfree(db_entry);
211
212 return rc;
213 }
214
215 /* Initialize the doorbell recovery mechanism */
216 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
217 {
218 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
219
220 /* Make sure db_size was set in cdev */
221 if (!p_hwfn->cdev->db_size) {
222 DP_ERR(p_hwfn->cdev, "db_size not set\n");
223 return -EINVAL;
224 }
225
226 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
227 spin_lock_init(&p_hwfn->db_recovery_info.lock);
228 p_hwfn->db_recovery_info.db_recovery_counter = 0;
229
230 return 0;
231 }
232
233 /* Destroy the doorbell recovery mechanism */
234 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
235 {
236 struct qed_db_recovery_entry *db_entry = NULL;
237
238 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
239 if (!list_empty(&p_hwfn->db_recovery_info.list)) {
240 DP_VERBOSE(p_hwfn,
241 QED_MSG_SPQ,
242 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
243 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
244 db_entry =
245 list_first_entry(&p_hwfn->db_recovery_info.list,
246 struct qed_db_recovery_entry,
247 list_entry);
248 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
249 list_del(&db_entry->list_entry);
250 kfree(db_entry);
251 }
252 }
253 p_hwfn->db_recovery_info.db_recovery_counter = 0;
254 }
255
256 /* Print the content of the doorbell recovery mechanism */
257 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
258 {
259 struct qed_db_recovery_entry *db_entry = NULL;
260
261 DP_NOTICE(p_hwfn,
262 "Displaying doorbell recovery database. Counter was %d\n",
263 p_hwfn->db_recovery_info.db_recovery_counter);
264
265 /* Protect the list */
266 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
267 list_for_each_entry(db_entry,
268 &p_hwfn->db_recovery_info.list, list_entry) {
269 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
270 }
271
272 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
273 }
274
275 /* Ring the doorbell of a single doorbell recovery entry */
276 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
277 struct qed_db_recovery_entry *db_entry)
278 {
279 /* Print according to width */
280 if (db_entry->db_width == DB_REC_WIDTH_32B) {
281 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
282 "ringing doorbell address %p data %x\n",
283 db_entry->db_addr,
284 *(u32 *)db_entry->db_data);
285 } else {
286 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
287 "ringing doorbell address %p data %llx\n",
288 db_entry->db_addr,
289 *(u64 *)(db_entry->db_data));
290 }
291
292 /* Sanity */
293 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
294 db_entry->db_width, db_entry->db_data))
295 return;
296
297 /* Flush the write combined buffer. Since there are multiple doorbelling
298 * entities using the same address, if we don't flush, a transaction
299 * could be lost.
300 */
301 wmb();
302
303 /* Ring the doorbell */
304 if (db_entry->db_width == DB_REC_WIDTH_32B)
305 DIRECT_REG_WR(db_entry->db_addr,
306 *(u32 *)(db_entry->db_data));
307 else
308 DIRECT_REG_WR64(db_entry->db_addr,
309 *(u64 *)(db_entry->db_data));
310
311 /* Flush the write combined buffer. Next doorbell may come from a
312 * different entity to the same address...
313 */
314 wmb();
315 }
316
317 /* Traverse the doorbell recovery entry list and ring all the doorbells */
318 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
319 {
320 struct qed_db_recovery_entry *db_entry = NULL;
321
322 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
323 p_hwfn->db_recovery_info.db_recovery_counter);
324
325 /* Track amount of times recovery was executed */
326 p_hwfn->db_recovery_info.db_recovery_counter++;
327
328 /* Protect the list */
329 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
330 list_for_each_entry(db_entry,
331 &p_hwfn->db_recovery_info.list, list_entry)
332 qed_db_recovery_ring(p_hwfn, db_entry);
333 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
334 }
335
336 /******************** Doorbell Recovery end ****************/
337
338 /********************************** NIG LLH ***********************************/
339
340 enum qed_llh_filter_type {
341 QED_LLH_FILTER_TYPE_MAC,
342 QED_LLH_FILTER_TYPE_PROTOCOL,
343 };
344
345 struct qed_llh_mac_filter {
346 u8 addr[ETH_ALEN];
347 };
348
349 struct qed_llh_protocol_filter {
350 enum qed_llh_prot_filter_type_t type;
351 u16 source_port_or_eth_type;
352 u16 dest_port;
353 };
354
355 union qed_llh_filter {
356 struct qed_llh_mac_filter mac;
357 struct qed_llh_protocol_filter protocol;
358 };
359
360 struct qed_llh_filter_info {
361 bool b_enabled;
362 u32 ref_cnt;
363 enum qed_llh_filter_type type;
364 union qed_llh_filter filter;
365 };
366
367 struct qed_llh_info {
368 /* Number of LLH filters banks */
369 u8 num_ppfid;
370
371 #define MAX_NUM_PPFID 8
372 u8 ppfid_array[MAX_NUM_PPFID];
373
374 /* Array of filters arrays:
375 * "num_ppfid" elements of filters banks, where each is an array of
376 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
377 */
378 struct qed_llh_filter_info **pp_filters;
379 };
380
381 static void qed_llh_free(struct qed_dev *cdev)
382 {
383 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
384 u32 i;
385
386 if (p_llh_info) {
387 if (p_llh_info->pp_filters)
388 for (i = 0; i < p_llh_info->num_ppfid; i++)
389 kfree(p_llh_info->pp_filters[i]);
390
391 kfree(p_llh_info->pp_filters);
392 }
393
394 kfree(p_llh_info);
395 cdev->p_llh_info = NULL;
396 }
397
398 static int qed_llh_alloc(struct qed_dev *cdev)
399 {
400 struct qed_llh_info *p_llh_info;
401 u32 size, i;
402
403 p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
404 if (!p_llh_info)
405 return -ENOMEM;
406 cdev->p_llh_info = p_llh_info;
407
408 for (i = 0; i < MAX_NUM_PPFID; i++) {
409 if (!(cdev->ppfid_bitmap & (0x1 << i)))
410 continue;
411
412 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
413 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
414 p_llh_info->num_ppfid, i);
415 p_llh_info->num_ppfid++;
416 }
417
418 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
419 p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
420 if (!p_llh_info->pp_filters)
421 return -ENOMEM;
422
423 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
424 sizeof(**p_llh_info->pp_filters);
425 for (i = 0; i < p_llh_info->num_ppfid; i++) {
426 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
427 if (!p_llh_info->pp_filters[i])
428 return -ENOMEM;
429 }
430
431 return 0;
432 }
433
434 static int qed_llh_shadow_sanity(struct qed_dev *cdev,
435 u8 ppfid, u8 filter_idx, const char *action)
436 {
437 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
438
439 if (ppfid >= p_llh_info->num_ppfid) {
440 DP_NOTICE(cdev,
441 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
442 action, ppfid, p_llh_info->num_ppfid);
443 return -EINVAL;
444 }
445
446 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
447 DP_NOTICE(cdev,
448 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
449 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
450 return -EINVAL;
451 }
452
453 return 0;
454 }
455
456 #define QED_LLH_INVALID_FILTER_IDX 0xff
457
458 static int
459 qed_llh_shadow_search_filter(struct qed_dev *cdev,
460 u8 ppfid,
461 union qed_llh_filter *p_filter, u8 *p_filter_idx)
462 {
463 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
464 struct qed_llh_filter_info *p_filters;
465 int rc;
466 u8 i;
467
468 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
469 if (rc)
470 return rc;
471
472 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
473
474 p_filters = p_llh_info->pp_filters[ppfid];
475 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
476 if (!memcmp(p_filter, &p_filters[i].filter,
477 sizeof(*p_filter))) {
478 *p_filter_idx = i;
479 break;
480 }
481 }
482
483 return 0;
484 }
485
486 static int
487 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
488 {
489 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
490 struct qed_llh_filter_info *p_filters;
491 int rc;
492 u8 i;
493
494 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
495 if (rc)
496 return rc;
497
498 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
499
500 p_filters = p_llh_info->pp_filters[ppfid];
501 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
502 if (!p_filters[i].b_enabled) {
503 *p_filter_idx = i;
504 break;
505 }
506 }
507
508 return 0;
509 }
510
511 static int
512 __qed_llh_shadow_add_filter(struct qed_dev *cdev,
513 u8 ppfid,
514 u8 filter_idx,
515 enum qed_llh_filter_type type,
516 union qed_llh_filter *p_filter, u32 *p_ref_cnt)
517 {
518 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
519 struct qed_llh_filter_info *p_filters;
520 int rc;
521
522 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
523 if (rc)
524 return rc;
525
526 p_filters = p_llh_info->pp_filters[ppfid];
527 if (!p_filters[filter_idx].ref_cnt) {
528 p_filters[filter_idx].b_enabled = true;
529 p_filters[filter_idx].type = type;
530 memcpy(&p_filters[filter_idx].filter, p_filter,
531 sizeof(p_filters[filter_idx].filter));
532 }
533
534 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
535
536 return 0;
537 }
538
539 static int
540 qed_llh_shadow_add_filter(struct qed_dev *cdev,
541 u8 ppfid,
542 enum qed_llh_filter_type type,
543 union qed_llh_filter *p_filter,
544 u8 *p_filter_idx, u32 *p_ref_cnt)
545 {
546 int rc;
547
548 /* Check if the same filter already exist */
549 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
550 if (rc)
551 return rc;
552
553 /* Find a new entry in case of a new filter */
554 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
555 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
556 if (rc)
557 return rc;
558 }
559
560 /* No free entry was found */
561 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
562 DP_NOTICE(cdev,
563 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
564 ppfid);
565 return -EINVAL;
566 }
567
568 return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
569 p_filter, p_ref_cnt);
570 }
571
572 static int
573 __qed_llh_shadow_remove_filter(struct qed_dev *cdev,
574 u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
575 {
576 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
577 struct qed_llh_filter_info *p_filters;
578 int rc;
579
580 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
581 if (rc)
582 return rc;
583
584 p_filters = p_llh_info->pp_filters[ppfid];
585 if (!p_filters[filter_idx].ref_cnt) {
586 DP_NOTICE(cdev,
587 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
588 return -EINVAL;
589 }
590
591 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
592 if (!p_filters[filter_idx].ref_cnt)
593 memset(&p_filters[filter_idx],
594 0, sizeof(p_filters[filter_idx]));
595
596 return 0;
597 }
598
599 static int
600 qed_llh_shadow_remove_filter(struct qed_dev *cdev,
601 u8 ppfid,
602 union qed_llh_filter *p_filter,
603 u8 *p_filter_idx, u32 *p_ref_cnt)
604 {
605 int rc;
606
607 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
608 if (rc)
609 return rc;
610
611 /* No matching filter was found */
612 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
613 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
614 return -EINVAL;
615 }
616
617 return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
618 p_ref_cnt);
619 }
620
621 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
622 {
623 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
624
625 if (ppfid >= p_llh_info->num_ppfid) {
626 DP_NOTICE(cdev,
627 "ppfid %d is not valid, available indices are 0..%hhd\n",
628 ppfid, p_llh_info->num_ppfid - 1);
629 *p_abs_ppfid = 0;
630 return -EINVAL;
631 }
632
633 *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
634
635 return 0;
636 }
637
638 static int
639 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
640 {
641 struct qed_dev *cdev = p_hwfn->cdev;
642 enum qed_eng eng;
643 u8 ppfid;
644 int rc;
645
646 rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
647 if (rc != 0 && rc != -EOPNOTSUPP) {
648 DP_NOTICE(p_hwfn,
649 "Failed to get the engine affinity configuration\n");
650 return rc;
651 }
652
653 /* RoCE PF is bound to a single engine */
654 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
655 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
656 rc = qed_llh_set_roce_affinity(cdev, eng);
657 if (rc) {
658 DP_NOTICE(cdev,
659 "Failed to set the RoCE engine affinity\n");
660 return rc;
661 }
662
663 DP_VERBOSE(cdev,
664 QED_MSG_SP,
665 "LLH: Set the engine affinity of RoCE packets as %d\n",
666 eng);
667 }
668
669 /* Storage PF is bound to a single engine while L2 PF uses both */
670 if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn))
671 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
672 else /* L2_PERSONALITY */
673 eng = QED_BOTH_ENG;
674
675 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
676 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
677 if (rc) {
678 DP_NOTICE(cdev,
679 "Failed to set the engine affinity of ppfid %d\n",
680 ppfid);
681 return rc;
682 }
683 }
684
685 DP_VERBOSE(cdev, QED_MSG_SP,
686 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
687 eng);
688
689 return 0;
690 }
691
692 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
693 struct qed_ptt *p_ptt)
694 {
695 struct qed_dev *cdev = p_hwfn->cdev;
696 u8 ppfid, abs_ppfid;
697 int rc;
698
699 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
700 u32 addr;
701
702 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
703 if (rc)
704 return rc;
705
706 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
707 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
708 }
709
710 if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
711 !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
712 rc = qed_llh_add_mac_filter(cdev, 0,
713 p_hwfn->hw_info.hw_mac_addr);
714 if (rc)
715 DP_NOTICE(cdev,
716 "Failed to add an LLH filter with the primary MAC\n");
717 }
718
719 if (QED_IS_CMT(cdev)) {
720 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
721 if (rc)
722 return rc;
723 }
724
725 return 0;
726 }
727
728 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
729 {
730 return cdev->p_llh_info->num_ppfid;
731 }
732
733 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
734 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
735 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
736 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
737
738 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
739 {
740 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
741 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
742 u32 addr, val, eng_sel;
743 u8 abs_ppfid;
744 int rc = 0;
745
746 if (!p_ptt)
747 return -EAGAIN;
748
749 if (!QED_IS_CMT(cdev))
750 goto out;
751
752 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
753 if (rc)
754 goto out;
755
756 switch (eng) {
757 case QED_ENG0:
758 eng_sel = 0;
759 break;
760 case QED_ENG1:
761 eng_sel = 1;
762 break;
763 case QED_BOTH_ENG:
764 eng_sel = 2;
765 break;
766 default:
767 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
768 rc = -EINVAL;
769 goto out;
770 }
771
772 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
773 val = qed_rd(p_hwfn, p_ptt, addr);
774 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
775 qed_wr(p_hwfn, p_ptt, addr, val);
776
777 /* The iWARP affinity is set as the affinity of ppfid 0 */
778 if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
779 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
780 out:
781 qed_ptt_release(p_hwfn, p_ptt);
782
783 return rc;
784 }
785
786 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
787 {
788 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
789 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
790 u32 addr, val, eng_sel;
791 u8 ppfid, abs_ppfid;
792 int rc = 0;
793
794 if (!p_ptt)
795 return -EAGAIN;
796
797 if (!QED_IS_CMT(cdev))
798 goto out;
799
800 switch (eng) {
801 case QED_ENG0:
802 eng_sel = 0;
803 break;
804 case QED_ENG1:
805 eng_sel = 1;
806 break;
807 case QED_BOTH_ENG:
808 eng_sel = 2;
809 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
810 0xf); /* QP bit 15 */
811 break;
812 default:
813 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
814 rc = -EINVAL;
815 goto out;
816 }
817
818 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
819 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
820 if (rc)
821 goto out;
822
823 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
824 val = qed_rd(p_hwfn, p_ptt, addr);
825 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
826 qed_wr(p_hwfn, p_ptt, addr, val);
827 }
828 out:
829 qed_ptt_release(p_hwfn, p_ptt);
830
831 return rc;
832 }
833
834 struct qed_llh_filter_details {
835 u64 value;
836 u32 mode;
837 u32 protocol_type;
838 u32 hdr_sel;
839 u32 enable;
840 };
841
842 static int
843 qed_llh_access_filter(struct qed_hwfn *p_hwfn,
844 struct qed_ptt *p_ptt,
845 u8 abs_ppfid,
846 u8 filter_idx,
847 struct qed_llh_filter_details *p_details)
848 {
849 struct qed_dmae_params params = {0};
850 u32 addr;
851 u8 pfid;
852 int rc;
853
854 /* The NIG/LLH registers that are accessed in this function have only 16
855 * rows which are exposed to a PF. I.e. only the 16 filters of its
856 * default ppfid. Accessing filters of other ppfids requires pretending
857 * to another PFs.
858 * The calculation of PPFID->PFID in AH is based on the relative index
859 * of a PF on its port.
860 * For BB the pfid is actually the abs_ppfid.
861 */
862 if (QED_IS_BB(p_hwfn->cdev))
863 pfid = abs_ppfid;
864 else
865 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
866 MFW_PORT(p_hwfn);
867
868 /* Filter enable - should be done first when removing a filter */
869 if (!p_details->enable) {
870 qed_fid_pretend(p_hwfn, p_ptt,
871 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
872
873 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
874 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
875
876 qed_fid_pretend(p_hwfn, p_ptt,
877 p_hwfn->rel_pf_id <<
878 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
879 }
880
881 /* Filter value */
882 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
883
884 SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1);
885 params.dst_pfid = pfid;
886 rc = qed_dmae_host2grc(p_hwfn,
887 p_ptt,
888 (u64)(uintptr_t)&p_details->value,
889 addr, 2 /* size_in_dwords */,
890 &params);
891 if (rc)
892 return rc;
893
894 qed_fid_pretend(p_hwfn, p_ptt,
895 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
896
897 /* Filter mode */
898 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
899 qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
900
901 /* Filter protocol type */
902 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
903 qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
904
905 /* Filter header select */
906 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
907 qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
908
909 /* Filter enable - should be done last when adding a filter */
910 if (p_details->enable) {
911 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
912 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
913 }
914
915 qed_fid_pretend(p_hwfn, p_ptt,
916 p_hwfn->rel_pf_id <<
917 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
918
919 return 0;
920 }
921
922 static int
923 qed_llh_add_filter(struct qed_hwfn *p_hwfn,
924 struct qed_ptt *p_ptt,
925 u8 abs_ppfid,
926 u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
927 {
928 struct qed_llh_filter_details filter_details;
929
930 filter_details.enable = 1;
931 filter_details.value = ((u64)high << 32) | low;
932 filter_details.hdr_sel = 0;
933 filter_details.protocol_type = filter_prot_type;
934 /* Mode: 0: MAC-address classification 1: protocol classification */
935 filter_details.mode = filter_prot_type ? 1 : 0;
936
937 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
938 &filter_details);
939 }
940
941 static int
942 qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
943 struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
944 {
945 struct qed_llh_filter_details filter_details = {0};
946
947 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
948 &filter_details);
949 }
950
951 int qed_llh_add_mac_filter(struct qed_dev *cdev,
952 u8 ppfid, u8 mac_addr[ETH_ALEN])
953 {
954 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
955 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
956 union qed_llh_filter filter = {};
957 u8 filter_idx, abs_ppfid = 0;
958 u32 high, low, ref_cnt;
959 int rc = 0;
960
961 if (!p_ptt)
962 return -EAGAIN;
963
964 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
965 goto out;
966
967 memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
968 rc = qed_llh_shadow_add_filter(cdev, ppfid,
969 QED_LLH_FILTER_TYPE_MAC,
970 &filter, &filter_idx, &ref_cnt);
971 if (rc)
972 goto err;
973
974 /* Configure the LLH only in case of a new the filter */
975 if (ref_cnt == 1) {
976 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
977 if (rc)
978 goto err;
979
980 high = mac_addr[1] | (mac_addr[0] << 8);
981 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
982 (mac_addr[2] << 24);
983 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
984 0, high, low);
985 if (rc)
986 goto err;
987 }
988
989 DP_VERBOSE(cdev,
990 QED_MSG_SP,
991 "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
992 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
993
994 goto out;
995
996 err: DP_NOTICE(cdev,
997 "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
998 mac_addr, ppfid);
999 out:
1000 qed_ptt_release(p_hwfn, p_ptt);
1001
1002 return rc;
1003 }
1004
1005 static int
1006 qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1007 enum qed_llh_prot_filter_type_t type,
1008 u16 source_port_or_eth_type,
1009 u16 dest_port, u8 *str, size_t str_len)
1010 {
1011 switch (type) {
1012 case QED_LLH_FILTER_ETHERTYPE:
1013 snprintf(str, str_len, "Ethertype 0x%04x",
1014 source_port_or_eth_type);
1015 break;
1016 case QED_LLH_FILTER_TCP_SRC_PORT:
1017 snprintf(str, str_len, "TCP src port 0x%04x",
1018 source_port_or_eth_type);
1019 break;
1020 case QED_LLH_FILTER_UDP_SRC_PORT:
1021 snprintf(str, str_len, "UDP src port 0x%04x",
1022 source_port_or_eth_type);
1023 break;
1024 case QED_LLH_FILTER_TCP_DEST_PORT:
1025 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1026 break;
1027 case QED_LLH_FILTER_UDP_DEST_PORT:
1028 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1029 break;
1030 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1031 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1032 source_port_or_eth_type, dest_port);
1033 break;
1034 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1035 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1036 source_port_or_eth_type, dest_port);
1037 break;
1038 default:
1039 DP_NOTICE(cdev,
1040 "Non valid LLH protocol filter type %d\n", type);
1041 return -EINVAL;
1042 }
1043
1044 return 0;
1045 }
1046
1047 static int
1048 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1049 enum qed_llh_prot_filter_type_t type,
1050 u16 source_port_or_eth_type,
1051 u16 dest_port, u32 *p_high, u32 *p_low)
1052 {
1053 *p_high = 0;
1054 *p_low = 0;
1055
1056 switch (type) {
1057 case QED_LLH_FILTER_ETHERTYPE:
1058 *p_high = source_port_or_eth_type;
1059 break;
1060 case QED_LLH_FILTER_TCP_SRC_PORT:
1061 case QED_LLH_FILTER_UDP_SRC_PORT:
1062 *p_low = source_port_or_eth_type << 16;
1063 break;
1064 case QED_LLH_FILTER_TCP_DEST_PORT:
1065 case QED_LLH_FILTER_UDP_DEST_PORT:
1066 *p_low = dest_port;
1067 break;
1068 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1069 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1070 *p_low = (source_port_or_eth_type << 16) | dest_port;
1071 break;
1072 default:
1073 DP_NOTICE(cdev,
1074 "Non valid LLH protocol filter type %d\n", type);
1075 return -EINVAL;
1076 }
1077
1078 return 0;
1079 }
1080
1081 int
1082 qed_llh_add_protocol_filter(struct qed_dev *cdev,
1083 u8 ppfid,
1084 enum qed_llh_prot_filter_type_t type,
1085 u16 source_port_or_eth_type, u16 dest_port)
1086 {
1087 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1088 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1089 u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1090 union qed_llh_filter filter = {};
1091 u32 high, low, ref_cnt;
1092 int rc = 0;
1093
1094 if (!p_ptt)
1095 return -EAGAIN;
1096
1097 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1098 goto out;
1099
1100 rc = qed_llh_protocol_filter_stringify(cdev, type,
1101 source_port_or_eth_type,
1102 dest_port, str, sizeof(str));
1103 if (rc)
1104 goto err;
1105
1106 filter.protocol.type = type;
1107 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1108 filter.protocol.dest_port = dest_port;
1109 rc = qed_llh_shadow_add_filter(cdev,
1110 ppfid,
1111 QED_LLH_FILTER_TYPE_PROTOCOL,
1112 &filter, &filter_idx, &ref_cnt);
1113 if (rc)
1114 goto err;
1115
1116 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1117 if (rc)
1118 goto err;
1119
1120 /* Configure the LLH only in case of a new the filter */
1121 if (ref_cnt == 1) {
1122 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1123 source_port_or_eth_type,
1124 dest_port, &high, &low);
1125 if (rc)
1126 goto err;
1127
1128 type_bitmap = 0x1 << type;
1129 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1130 filter_idx, type_bitmap, high, low);
1131 if (rc)
1132 goto err;
1133 }
1134
1135 DP_VERBOSE(cdev,
1136 QED_MSG_SP,
1137 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1138 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1139
1140 goto out;
1141
1142 err: DP_NOTICE(p_hwfn,
1143 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1144 str, ppfid);
1145 out:
1146 qed_ptt_release(p_hwfn, p_ptt);
1147
1148 return rc;
1149 }
1150
1151 void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1152 u8 ppfid, u8 mac_addr[ETH_ALEN])
1153 {
1154 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1155 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1156 union qed_llh_filter filter = {};
1157 u8 filter_idx, abs_ppfid;
1158 int rc = 0;
1159 u32 ref_cnt;
1160
1161 if (!p_ptt)
1162 return;
1163
1164 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1165 goto out;
1166
1167 ether_addr_copy(filter.mac.addr, mac_addr);
1168 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1169 &ref_cnt);
1170 if (rc)
1171 goto err;
1172
1173 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1174 if (rc)
1175 goto err;
1176
1177 /* Remove from the LLH in case the filter is not in use */
1178 if (!ref_cnt) {
1179 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1180 filter_idx);
1181 if (rc)
1182 goto err;
1183 }
1184
1185 DP_VERBOSE(cdev,
1186 QED_MSG_SP,
1187 "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1188 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1189
1190 goto out;
1191
1192 err: DP_NOTICE(cdev,
1193 "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1194 mac_addr, ppfid);
1195 out:
1196 qed_ptt_release(p_hwfn, p_ptt);
1197 }
1198
1199 void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1200 u8 ppfid,
1201 enum qed_llh_prot_filter_type_t type,
1202 u16 source_port_or_eth_type, u16 dest_port)
1203 {
1204 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1205 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1206 u8 filter_idx, abs_ppfid, str[32];
1207 union qed_llh_filter filter = {};
1208 int rc = 0;
1209 u32 ref_cnt;
1210
1211 if (!p_ptt)
1212 return;
1213
1214 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1215 goto out;
1216
1217 rc = qed_llh_protocol_filter_stringify(cdev, type,
1218 source_port_or_eth_type,
1219 dest_port, str, sizeof(str));
1220 if (rc)
1221 goto err;
1222
1223 filter.protocol.type = type;
1224 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1225 filter.protocol.dest_port = dest_port;
1226 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1227 &ref_cnt);
1228 if (rc)
1229 goto err;
1230
1231 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1232 if (rc)
1233 goto err;
1234
1235 /* Remove from the LLH in case the filter is not in use */
1236 if (!ref_cnt) {
1237 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1238 filter_idx);
1239 if (rc)
1240 goto err;
1241 }
1242
1243 DP_VERBOSE(cdev,
1244 QED_MSG_SP,
1245 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1246 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1247
1248 goto out;
1249
1250 err: DP_NOTICE(cdev,
1251 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1252 str, ppfid);
1253 out:
1254 qed_ptt_release(p_hwfn, p_ptt);
1255 }
1256
1257 /******************************* NIG LLH - End ********************************/
1258
1259 #define QED_MIN_DPIS (4)
1260 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
1261
1262 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1263 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1264 {
1265 u32 bar_reg = (bar_id == BAR_ID_0 ?
1266 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1267 u32 val;
1268
1269 if (IS_VF(p_hwfn->cdev))
1270 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1271
1272 val = qed_rd(p_hwfn, p_ptt, bar_reg);
1273 if (val)
1274 return 1 << (val + 15);
1275
1276 /* Old MFW initialized above registered only conditionally */
1277 if (p_hwfn->cdev->num_hwfns > 1) {
1278 DP_INFO(p_hwfn,
1279 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1280 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1281 } else {
1282 DP_INFO(p_hwfn,
1283 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1284 return 512 * 1024;
1285 }
1286 }
1287
1288 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1289 {
1290 u32 i;
1291
1292 cdev->dp_level = dp_level;
1293 cdev->dp_module = dp_module;
1294 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1295 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1296
1297 p_hwfn->dp_level = dp_level;
1298 p_hwfn->dp_module = dp_module;
1299 }
1300 }
1301
1302 void qed_init_struct(struct qed_dev *cdev)
1303 {
1304 u8 i;
1305
1306 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1307 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1308
1309 p_hwfn->cdev = cdev;
1310 p_hwfn->my_id = i;
1311 p_hwfn->b_active = false;
1312
1313 mutex_init(&p_hwfn->dmae_info.mutex);
1314 }
1315
1316 /* hwfn 0 is always active */
1317 cdev->hwfns[0].b_active = true;
1318
1319 /* set the default cache alignment to 128 */
1320 cdev->cache_shift = 7;
1321 }
1322
1323 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1324 {
1325 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1326
1327 kfree(qm_info->qm_pq_params);
1328 qm_info->qm_pq_params = NULL;
1329 kfree(qm_info->qm_vport_params);
1330 qm_info->qm_vport_params = NULL;
1331 kfree(qm_info->qm_port_params);
1332 qm_info->qm_port_params = NULL;
1333 kfree(qm_info->wfq_data);
1334 qm_info->wfq_data = NULL;
1335 }
1336
1337 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1338 {
1339 kfree(p_hwfn->dbg_user_info);
1340 p_hwfn->dbg_user_info = NULL;
1341 }
1342
1343 void qed_resc_free(struct qed_dev *cdev)
1344 {
1345 struct qed_rdma_info *rdma_info;
1346 struct qed_hwfn *p_hwfn;
1347 int i;
1348
1349 if (IS_VF(cdev)) {
1350 for_each_hwfn(cdev, i)
1351 qed_l2_free(&cdev->hwfns[i]);
1352 return;
1353 }
1354
1355 kfree(cdev->fw_data);
1356 cdev->fw_data = NULL;
1357
1358 kfree(cdev->reset_stats);
1359 cdev->reset_stats = NULL;
1360
1361 qed_llh_free(cdev);
1362
1363 for_each_hwfn(cdev, i) {
1364 p_hwfn = cdev->hwfns + i;
1365 rdma_info = p_hwfn->p_rdma_info;
1366
1367 qed_cxt_mngr_free(p_hwfn);
1368 qed_qm_info_free(p_hwfn);
1369 qed_spq_free(p_hwfn);
1370 qed_eq_free(p_hwfn);
1371 qed_consq_free(p_hwfn);
1372 qed_int_free(p_hwfn);
1373 #ifdef CONFIG_QED_LL2
1374 qed_ll2_free(p_hwfn);
1375 #endif
1376 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1377 qed_fcoe_free(p_hwfn);
1378
1379 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1380 qed_iscsi_free(p_hwfn);
1381 qed_ooo_free(p_hwfn);
1382 }
1383
1384 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) {
1385 qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto);
1386 qed_rdma_info_free(p_hwfn);
1387 }
1388
1389 qed_iov_free(p_hwfn);
1390 qed_l2_free(p_hwfn);
1391 qed_dmae_info_free(p_hwfn);
1392 qed_dcbx_info_free(p_hwfn);
1393 qed_dbg_user_data_free(p_hwfn);
1394 qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1395
1396 /* Destroy doorbell recovery mechanism */
1397 qed_db_recovery_teardown(p_hwfn);
1398 }
1399 }
1400
1401 /******************** QM initialization *******************/
1402 #define ACTIVE_TCS_BMAP 0x9f
1403 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1404
1405 /* determines the physical queue flags for a given PF. */
1406 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1407 {
1408 u32 flags;
1409
1410 /* common flags */
1411 flags = PQ_FLAGS_LB;
1412
1413 /* feature flags */
1414 if (IS_QED_SRIOV(p_hwfn->cdev))
1415 flags |= PQ_FLAGS_VFS;
1416
1417 /* protocol flags */
1418 switch (p_hwfn->hw_info.personality) {
1419 case QED_PCI_ETH:
1420 flags |= PQ_FLAGS_MCOS;
1421 break;
1422 case QED_PCI_FCOE:
1423 flags |= PQ_FLAGS_OFLD;
1424 break;
1425 case QED_PCI_ISCSI:
1426 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1427 break;
1428 case QED_PCI_ETH_ROCE:
1429 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1430 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1431 flags |= PQ_FLAGS_MTC;
1432 break;
1433 case QED_PCI_ETH_IWARP:
1434 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1435 PQ_FLAGS_OFLD;
1436 break;
1437 default:
1438 DP_ERR(p_hwfn,
1439 "unknown personality %d\n", p_hwfn->hw_info.personality);
1440 return 0;
1441 }
1442
1443 return flags;
1444 }
1445
1446 /* Getters for resource amounts necessary for qm initialization */
1447 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1448 {
1449 return p_hwfn->hw_info.num_hw_tc;
1450 }
1451
1452 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1453 {
1454 return IS_QED_SRIOV(p_hwfn->cdev) ?
1455 p_hwfn->cdev->p_iov_info->total_vfs : 0;
1456 }
1457
1458 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1459 {
1460 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1461
1462 if (!(PQ_FLAGS_MTC & pq_flags))
1463 return 1;
1464
1465 return qed_init_qm_get_num_tcs(p_hwfn);
1466 }
1467
1468 #define NUM_DEFAULT_RLS 1
1469
1470 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1471 {
1472 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1473
1474 /* num RLs can't exceed resource amount of rls or vports */
1475 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1476 RESC_NUM(p_hwfn, QED_VPORT));
1477
1478 /* Make sure after we reserve there's something left */
1479 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1480 return 0;
1481
1482 /* subtract rls necessary for VFs and one default one for the PF */
1483 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1484
1485 return num_pf_rls;
1486 }
1487
1488 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1489 {
1490 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1491
1492 /* all pqs share the same vport, except for vfs and pf_rl pqs */
1493 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1494 qed_init_qm_get_num_pf_rls(p_hwfn) +
1495 (!!(PQ_FLAGS_VFS & pq_flags)) *
1496 qed_init_qm_get_num_vfs(p_hwfn) + 1;
1497 }
1498
1499 /* calc amount of PQs according to the requested flags */
1500 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1501 {
1502 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1503
1504 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1505 qed_init_qm_get_num_pf_rls(p_hwfn) +
1506 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1507 qed_init_qm_get_num_tcs(p_hwfn) +
1508 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1509 (!!(PQ_FLAGS_ACK & pq_flags)) +
1510 (!!(PQ_FLAGS_OFLD & pq_flags)) *
1511 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1512 (!!(PQ_FLAGS_LLT & pq_flags)) *
1513 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1514 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1515 }
1516
1517 /* initialize the top level QM params */
1518 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1519 {
1520 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1521 bool four_port;
1522
1523 /* pq and vport bases for this PF */
1524 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1525 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1526
1527 /* rate limiting and weighted fair queueing are always enabled */
1528 qm_info->vport_rl_en = true;
1529 qm_info->vport_wfq_en = true;
1530
1531 /* TC config is different for AH 4 port */
1532 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1533
1534 /* in AH 4 port we have fewer TCs per port */
1535 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1536 NUM_OF_PHYS_TCS;
1537
1538 /* unless MFW indicated otherwise, ooo_tc == 3 for
1539 * AH 4-port and 4 otherwise.
1540 */
1541 if (!qm_info->ooo_tc)
1542 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1543 DCBX_TCP_OOO_TC;
1544 }
1545
1546 /* initialize qm vport params */
1547 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1548 {
1549 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1550 u8 i;
1551
1552 /* all vports participate in weighted fair queueing */
1553 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1554 qm_info->qm_vport_params[i].wfq = 1;
1555 }
1556
1557 /* initialize qm port params */
1558 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1559 {
1560 /* Initialize qm port parameters */
1561 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1562 struct qed_dev *cdev = p_hwfn->cdev;
1563
1564 /* indicate how ooo and high pri traffic is dealt with */
1565 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1566 ACTIVE_TCS_BMAP_4PORT_K2 :
1567 ACTIVE_TCS_BMAP;
1568
1569 for (i = 0; i < num_ports; i++) {
1570 struct init_qm_port_params *p_qm_port =
1571 &p_hwfn->qm_info.qm_port_params[i];
1572 u16 pbf_max_cmd_lines;
1573
1574 p_qm_port->active = 1;
1575 p_qm_port->active_phys_tcs = active_phys_tcs;
1576 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
1577 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1578 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
1579 }
1580 }
1581
1582 /* Reset the params which must be reset for qm init. QM init may be called as
1583 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1584 * params may be affected by the init but would simply recalculate to the same
1585 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1586 * affected as these amounts stay the same.
1587 */
1588 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1589 {
1590 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1591
1592 qm_info->num_pqs = 0;
1593 qm_info->num_vports = 0;
1594 qm_info->num_pf_rls = 0;
1595 qm_info->num_vf_pqs = 0;
1596 qm_info->first_vf_pq = 0;
1597 qm_info->first_mcos_pq = 0;
1598 qm_info->first_rl_pq = 0;
1599 }
1600
1601 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1602 {
1603 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1604
1605 qm_info->num_vports++;
1606
1607 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1608 DP_ERR(p_hwfn,
1609 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1610 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1611 }
1612
1613 /* initialize a single pq and manage qm_info resources accounting.
1614 * The pq_init_flags param determines whether the PQ is rate limited
1615 * (for VF or PF) and whether a new vport is allocated to the pq or not
1616 * (i.e. vport will be shared).
1617 */
1618
1619 /* flags for pq init */
1620 #define PQ_INIT_SHARE_VPORT (1 << 0)
1621 #define PQ_INIT_PF_RL (1 << 1)
1622 #define PQ_INIT_VF_RL (1 << 2)
1623
1624 /* defines for pq init */
1625 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1626 #define PQ_INIT_DEFAULT_TC 0
1627
1628 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1629 {
1630 p_info->offload_tc = tc;
1631 p_info->offload_tc_set = true;
1632 }
1633
1634 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1635 {
1636 return p_hwfn->hw_info.offload_tc_set;
1637 }
1638
1639 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1640 {
1641 if (qed_is_offload_tc_set(p_hwfn))
1642 return p_hwfn->hw_info.offload_tc;
1643
1644 return PQ_INIT_DEFAULT_TC;
1645 }
1646
1647 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1648 struct qed_qm_info *qm_info,
1649 u8 tc, u32 pq_init_flags)
1650 {
1651 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1652
1653 if (pq_idx > max_pq)
1654 DP_ERR(p_hwfn,
1655 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1656
1657 /* init pq params */
1658 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1659 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1660 qm_info->num_vports;
1661 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1662 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1663 qm_info->qm_pq_params[pq_idx].rl_valid =
1664 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1665
1666 /* qm params accounting */
1667 qm_info->num_pqs++;
1668 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1669 qm_info->num_vports++;
1670
1671 if (pq_init_flags & PQ_INIT_PF_RL)
1672 qm_info->num_pf_rls++;
1673
1674 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1675 DP_ERR(p_hwfn,
1676 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1677 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1678
1679 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1680 DP_ERR(p_hwfn,
1681 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1682 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1683 }
1684
1685 /* get pq index according to PQ_FLAGS */
1686 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1687 unsigned long pq_flags)
1688 {
1689 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1690
1691 /* Can't have multiple flags set here */
1692 if (bitmap_weight(&pq_flags,
1693 sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1694 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1695 goto err;
1696 }
1697
1698 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1699 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1700 goto err;
1701 }
1702
1703 switch (pq_flags) {
1704 case PQ_FLAGS_RLS:
1705 return &qm_info->first_rl_pq;
1706 case PQ_FLAGS_MCOS:
1707 return &qm_info->first_mcos_pq;
1708 case PQ_FLAGS_LB:
1709 return &qm_info->pure_lb_pq;
1710 case PQ_FLAGS_OOO:
1711 return &qm_info->ooo_pq;
1712 case PQ_FLAGS_ACK:
1713 return &qm_info->pure_ack_pq;
1714 case PQ_FLAGS_OFLD:
1715 return &qm_info->first_ofld_pq;
1716 case PQ_FLAGS_LLT:
1717 return &qm_info->first_llt_pq;
1718 case PQ_FLAGS_VFS:
1719 return &qm_info->first_vf_pq;
1720 default:
1721 goto err;
1722 }
1723
1724 err:
1725 return &qm_info->start_pq;
1726 }
1727
1728 /* save pq index in qm info */
1729 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1730 u32 pq_flags, u16 pq_val)
1731 {
1732 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1733
1734 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1735 }
1736
1737 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1738 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1739 {
1740 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1741
1742 return *base_pq_idx + CM_TX_PQ_BASE;
1743 }
1744
1745 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1746 {
1747 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1748
1749 if (max_tc == 0) {
1750 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1751 PQ_FLAGS_MCOS);
1752 return p_hwfn->qm_info.start_pq;
1753 }
1754
1755 if (tc > max_tc)
1756 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1757
1758 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1759 }
1760
1761 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1762 {
1763 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1764
1765 if (max_vf == 0) {
1766 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1767 PQ_FLAGS_VFS);
1768 return p_hwfn->qm_info.start_pq;
1769 }
1770
1771 if (vf > max_vf)
1772 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1773
1774 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1775 }
1776
1777 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1778 {
1779 u16 first_ofld_pq, pq_offset;
1780
1781 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1782 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1783 tc : PQ_INIT_DEFAULT_TC;
1784
1785 return first_ofld_pq + pq_offset;
1786 }
1787
1788 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1789 {
1790 u16 first_llt_pq, pq_offset;
1791
1792 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1793 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1794 tc : PQ_INIT_DEFAULT_TC;
1795
1796 return first_llt_pq + pq_offset;
1797 }
1798
1799 /* Functions for creating specific types of pqs */
1800 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1801 {
1802 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1803
1804 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1805 return;
1806
1807 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1808 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1809 }
1810
1811 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1812 {
1813 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1814
1815 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1816 return;
1817
1818 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1819 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1820 }
1821
1822 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1823 {
1824 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1825
1826 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1827 return;
1828
1829 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1830 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1831 PQ_INIT_SHARE_VPORT);
1832 }
1833
1834 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1835 {
1836 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1837 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1838 u8 tc;
1839
1840 /* override pq's TC if offload TC is set */
1841 for (tc = 0; tc < num_tcs; tc++)
1842 qed_init_qm_pq(p_hwfn, qm_info,
1843 qed_is_offload_tc_set(p_hwfn) ?
1844 p_hwfn->hw_info.offload_tc : tc,
1845 PQ_INIT_SHARE_VPORT);
1846 }
1847
1848 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1849 {
1850 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1851
1852 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1853 return;
1854
1855 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1856 qed_init_qm_mtc_pqs(p_hwfn);
1857 }
1858
1859 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1860 {
1861 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1862
1863 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1864 return;
1865
1866 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1867 qed_init_qm_mtc_pqs(p_hwfn);
1868 }
1869
1870 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1871 {
1872 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1873 u8 tc_idx;
1874
1875 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1876 return;
1877
1878 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1879 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1880 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1881 }
1882
1883 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1884 {
1885 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1886 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1887
1888 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1889 return;
1890
1891 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1892 qm_info->num_vf_pqs = num_vfs;
1893 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1894 qed_init_qm_pq(p_hwfn,
1895 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1896 }
1897
1898 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1899 {
1900 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1901 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1902
1903 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1904 return;
1905
1906 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1907 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1908 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1909 PQ_INIT_PF_RL);
1910 }
1911
1912 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1913 {
1914 /* rate limited pqs, must come first (FW assumption) */
1915 qed_init_qm_rl_pqs(p_hwfn);
1916
1917 /* pqs for multi cos */
1918 qed_init_qm_mcos_pqs(p_hwfn);
1919
1920 /* pure loopback pq */
1921 qed_init_qm_lb_pq(p_hwfn);
1922
1923 /* out of order pq */
1924 qed_init_qm_ooo_pq(p_hwfn);
1925
1926 /* pure ack pq */
1927 qed_init_qm_pure_ack_pq(p_hwfn);
1928
1929 /* pq for offloaded protocol */
1930 qed_init_qm_offload_pq(p_hwfn);
1931
1932 /* low latency pq */
1933 qed_init_qm_low_latency_pq(p_hwfn);
1934
1935 /* done sharing vports */
1936 qed_init_qm_advance_vport(p_hwfn);
1937
1938 /* pqs for vfs */
1939 qed_init_qm_vf_pqs(p_hwfn);
1940 }
1941
1942 /* compare values of getters against resources amounts */
1943 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1944 {
1945 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1946 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1947 return -EINVAL;
1948 }
1949
1950 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1951 return 0;
1952
1953 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1954 p_hwfn->hw_info.multi_tc_roce_en = false;
1955 DP_NOTICE(p_hwfn,
1956 "multi-tc roce was disabled to reduce requested amount of pqs\n");
1957 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1958 return 0;
1959 }
1960
1961 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1962 return -EINVAL;
1963 }
1964
1965 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1966 {
1967 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1968 struct init_qm_vport_params *vport;
1969 struct init_qm_port_params *port;
1970 struct init_qm_pq_params *pq;
1971 int i, tc;
1972
1973 /* top level params */
1974 DP_VERBOSE(p_hwfn,
1975 NETIF_MSG_HW,
1976 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1977 qm_info->start_pq,
1978 qm_info->start_vport,
1979 qm_info->pure_lb_pq,
1980 qm_info->first_ofld_pq,
1981 qm_info->first_llt_pq,
1982 qm_info->pure_ack_pq);
1983 DP_VERBOSE(p_hwfn,
1984 NETIF_MSG_HW,
1985 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
1986 qm_info->ooo_pq,
1987 qm_info->first_vf_pq,
1988 qm_info->num_pqs,
1989 qm_info->num_vf_pqs,
1990 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
1991 DP_VERBOSE(p_hwfn,
1992 NETIF_MSG_HW,
1993 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1994 qm_info->pf_rl_en,
1995 qm_info->pf_wfq_en,
1996 qm_info->vport_rl_en,
1997 qm_info->vport_wfq_en,
1998 qm_info->pf_wfq,
1999 qm_info->pf_rl,
2000 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2001
2002 /* port table */
2003 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2004 port = &(qm_info->qm_port_params[i]);
2005 DP_VERBOSE(p_hwfn,
2006 NETIF_MSG_HW,
2007 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2008 i,
2009 port->active,
2010 port->active_phys_tcs,
2011 port->num_pbf_cmd_lines,
2012 port->num_btb_blocks, port->reserved);
2013 }
2014
2015 /* vport table */
2016 for (i = 0; i < qm_info->num_vports; i++) {
2017 vport = &(qm_info->qm_vport_params[i]);
2018 DP_VERBOSE(p_hwfn,
2019 NETIF_MSG_HW,
2020 "vport idx %d, wfq %d, first_tx_pq_id [ ",
2021 qm_info->start_vport + i, vport->wfq);
2022 for (tc = 0; tc < NUM_OF_TCS; tc++)
2023 DP_VERBOSE(p_hwfn,
2024 NETIF_MSG_HW,
2025 "%d ", vport->first_tx_pq_id[tc]);
2026 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2027 }
2028
2029 /* pq table */
2030 for (i = 0; i < qm_info->num_pqs; i++) {
2031 pq = &(qm_info->qm_pq_params[i]);
2032 DP_VERBOSE(p_hwfn,
2033 NETIF_MSG_HW,
2034 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n",
2035 qm_info->start_pq + i,
2036 pq->port_id,
2037 pq->vport_id,
2038 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2039 }
2040 }
2041
2042 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2043 {
2044 /* reset params required for init run */
2045 qed_init_qm_reset_params(p_hwfn);
2046
2047 /* init QM top level params */
2048 qed_init_qm_params(p_hwfn);
2049
2050 /* init QM port params */
2051 qed_init_qm_port_params(p_hwfn);
2052
2053 /* init QM vport params */
2054 qed_init_qm_vport_params(p_hwfn);
2055
2056 /* init QM physical queue params */
2057 qed_init_qm_pq_params(p_hwfn);
2058
2059 /* display all that init */
2060 qed_dp_init_qm_params(p_hwfn);
2061 }
2062
2063 /* This function reconfigures the QM pf on the fly.
2064 * For this purpose we:
2065 * 1. reconfigure the QM database
2066 * 2. set new values to runtime array
2067 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2068 * 4. activate init tool in QM_PF stage
2069 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2070 */
2071 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2072 {
2073 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2074 bool b_rc;
2075 int rc;
2076
2077 /* initialize qed's qm data structure */
2078 qed_init_qm_info(p_hwfn);
2079
2080 /* stop PF's qm queues */
2081 spin_lock_bh(&qm_lock);
2082 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2083 qm_info->start_pq, qm_info->num_pqs);
2084 spin_unlock_bh(&qm_lock);
2085 if (!b_rc)
2086 return -EINVAL;
2087
2088 /* prepare QM portion of runtime array */
2089 qed_qm_init_pf(p_hwfn, p_ptt, false);
2090
2091 /* activate init tool on runtime array */
2092 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2093 p_hwfn->hw_info.hw_mode);
2094 if (rc)
2095 return rc;
2096
2097 /* start PF's qm queues */
2098 spin_lock_bh(&qm_lock);
2099 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2100 qm_info->start_pq, qm_info->num_pqs);
2101 spin_unlock_bh(&qm_lock);
2102 if (!b_rc)
2103 return -EINVAL;
2104
2105 return 0;
2106 }
2107
2108 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2109 {
2110 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2111 int rc;
2112
2113 rc = qed_init_qm_sanity(p_hwfn);
2114 if (rc)
2115 goto alloc_err;
2116
2117 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2118 sizeof(*qm_info->qm_pq_params),
2119 GFP_KERNEL);
2120 if (!qm_info->qm_pq_params)
2121 goto alloc_err;
2122
2123 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2124 sizeof(*qm_info->qm_vport_params),
2125 GFP_KERNEL);
2126 if (!qm_info->qm_vport_params)
2127 goto alloc_err;
2128
2129 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2130 sizeof(*qm_info->qm_port_params),
2131 GFP_KERNEL);
2132 if (!qm_info->qm_port_params)
2133 goto alloc_err;
2134
2135 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2136 sizeof(*qm_info->wfq_data),
2137 GFP_KERNEL);
2138 if (!qm_info->wfq_data)
2139 goto alloc_err;
2140
2141 return 0;
2142
2143 alloc_err:
2144 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2145 qed_qm_info_free(p_hwfn);
2146 return -ENOMEM;
2147 }
2148
2149 int qed_resc_alloc(struct qed_dev *cdev)
2150 {
2151 u32 rdma_tasks, excess_tasks;
2152 u32 line_count;
2153 int i, rc = 0;
2154
2155 if (IS_VF(cdev)) {
2156 for_each_hwfn(cdev, i) {
2157 rc = qed_l2_alloc(&cdev->hwfns[i]);
2158 if (rc)
2159 return rc;
2160 }
2161 return rc;
2162 }
2163
2164 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2165 if (!cdev->fw_data)
2166 return -ENOMEM;
2167
2168 for_each_hwfn(cdev, i) {
2169 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2170 u32 n_eqes, num_cons;
2171
2172 /* Initialize the doorbell recovery mechanism */
2173 rc = qed_db_recovery_setup(p_hwfn);
2174 if (rc)
2175 goto alloc_err;
2176
2177 /* First allocate the context manager structure */
2178 rc = qed_cxt_mngr_alloc(p_hwfn);
2179 if (rc)
2180 goto alloc_err;
2181
2182 /* Set the HW cid/tid numbers (in the contest manager)
2183 * Must be done prior to any further computations.
2184 */
2185 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2186 if (rc)
2187 goto alloc_err;
2188
2189 rc = qed_alloc_qm_data(p_hwfn);
2190 if (rc)
2191 goto alloc_err;
2192
2193 /* init qm info */
2194 qed_init_qm_info(p_hwfn);
2195
2196 /* Compute the ILT client partition */
2197 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2198 if (rc) {
2199 DP_NOTICE(p_hwfn,
2200 "too many ILT lines; re-computing with less lines\n");
2201 /* In case there are not enough ILT lines we reduce the
2202 * number of RDMA tasks and re-compute.
2203 */
2204 excess_tasks =
2205 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2206 if (!excess_tasks)
2207 goto alloc_err;
2208
2209 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2210 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2211 if (rc)
2212 goto alloc_err;
2213
2214 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2215 if (rc) {
2216 DP_ERR(p_hwfn,
2217 "failed ILT compute. Requested too many lines: %u\n",
2218 line_count);
2219
2220 goto alloc_err;
2221 }
2222 }
2223
2224 /* CID map / ILT shadow table / T2
2225 * The talbes sizes are determined by the computations above
2226 */
2227 rc = qed_cxt_tables_alloc(p_hwfn);
2228 if (rc)
2229 goto alloc_err;
2230
2231 /* SPQ, must follow ILT because initializes SPQ context */
2232 rc = qed_spq_alloc(p_hwfn);
2233 if (rc)
2234 goto alloc_err;
2235
2236 /* SP status block allocation */
2237 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2238 RESERVED_PTT_DPC);
2239
2240 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2241 if (rc)
2242 goto alloc_err;
2243
2244 rc = qed_iov_alloc(p_hwfn);
2245 if (rc)
2246 goto alloc_err;
2247
2248 /* EQ */
2249 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2250 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2251 u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn);
2252 enum protocol_type rdma_proto;
2253
2254 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2255 rdma_proto = PROTOCOLID_ROCE;
2256 else
2257 rdma_proto = PROTOCOLID_IWARP;
2258
2259 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2260 rdma_proto,
2261 NULL) * 2;
2262 /* EQ should be able to get events from all SRQ's
2263 * at the same time
2264 */
2265 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq;
2266 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2267 num_cons =
2268 qed_cxt_get_proto_cid_count(p_hwfn,
2269 PROTOCOLID_ISCSI,
2270 NULL);
2271 n_eqes += 2 * num_cons;
2272 }
2273
2274 if (n_eqes > 0xFFFF) {
2275 DP_ERR(p_hwfn,
2276 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2277 n_eqes, 0xFFFF);
2278 goto alloc_no_mem;
2279 }
2280
2281 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2282 if (rc)
2283 goto alloc_err;
2284
2285 rc = qed_consq_alloc(p_hwfn);
2286 if (rc)
2287 goto alloc_err;
2288
2289 rc = qed_l2_alloc(p_hwfn);
2290 if (rc)
2291 goto alloc_err;
2292
2293 #ifdef CONFIG_QED_LL2
2294 if (p_hwfn->using_ll2) {
2295 rc = qed_ll2_alloc(p_hwfn);
2296 if (rc)
2297 goto alloc_err;
2298 }
2299 #endif
2300
2301 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2302 rc = qed_fcoe_alloc(p_hwfn);
2303 if (rc)
2304 goto alloc_err;
2305 }
2306
2307 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2308 rc = qed_iscsi_alloc(p_hwfn);
2309 if (rc)
2310 goto alloc_err;
2311 rc = qed_ooo_alloc(p_hwfn);
2312 if (rc)
2313 goto alloc_err;
2314 }
2315
2316 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2317 rc = qed_rdma_info_alloc(p_hwfn);
2318 if (rc)
2319 goto alloc_err;
2320 }
2321
2322 /* DMA info initialization */
2323 rc = qed_dmae_info_alloc(p_hwfn);
2324 if (rc)
2325 goto alloc_err;
2326
2327 /* DCBX initialization */
2328 rc = qed_dcbx_info_alloc(p_hwfn);
2329 if (rc)
2330 goto alloc_err;
2331
2332 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2333 if (rc)
2334 goto alloc_err;
2335 }
2336
2337 rc = qed_llh_alloc(cdev);
2338 if (rc) {
2339 DP_NOTICE(cdev,
2340 "Failed to allocate memory for the llh_info structure\n");
2341 goto alloc_err;
2342 }
2343
2344 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2345 if (!cdev->reset_stats)
2346 goto alloc_no_mem;
2347
2348 return 0;
2349
2350 alloc_no_mem:
2351 rc = -ENOMEM;
2352 alloc_err:
2353 qed_resc_free(cdev);
2354 return rc;
2355 }
2356
2357 void qed_resc_setup(struct qed_dev *cdev)
2358 {
2359 int i;
2360
2361 if (IS_VF(cdev)) {
2362 for_each_hwfn(cdev, i)
2363 qed_l2_setup(&cdev->hwfns[i]);
2364 return;
2365 }
2366
2367 for_each_hwfn(cdev, i) {
2368 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2369
2370 qed_cxt_mngr_setup(p_hwfn);
2371 qed_spq_setup(p_hwfn);
2372 qed_eq_setup(p_hwfn);
2373 qed_consq_setup(p_hwfn);
2374
2375 /* Read shadow of current MFW mailbox */
2376 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2377 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2378 p_hwfn->mcp_info->mfw_mb_cur,
2379 p_hwfn->mcp_info->mfw_mb_length);
2380
2381 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2382
2383 qed_l2_setup(p_hwfn);
2384 qed_iov_setup(p_hwfn);
2385 #ifdef CONFIG_QED_LL2
2386 if (p_hwfn->using_ll2)
2387 qed_ll2_setup(p_hwfn);
2388 #endif
2389 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2390 qed_fcoe_setup(p_hwfn);
2391
2392 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2393 qed_iscsi_setup(p_hwfn);
2394 qed_ooo_setup(p_hwfn);
2395 }
2396 }
2397 }
2398
2399 #define FINAL_CLEANUP_POLL_CNT (100)
2400 #define FINAL_CLEANUP_POLL_TIME (10)
2401 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2402 struct qed_ptt *p_ptt, u16 id, bool is_vf)
2403 {
2404 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2405 int rc = -EBUSY;
2406
2407 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2408 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2409
2410 if (is_vf)
2411 id += 0x10;
2412
2413 command |= X_FINAL_CLEANUP_AGG_INT <<
2414 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2415 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2416 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2417 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2418
2419 /* Make sure notification is not set before initiating final cleanup */
2420 if (REG_RD(p_hwfn, addr)) {
2421 DP_NOTICE(p_hwfn,
2422 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2423 REG_WR(p_hwfn, addr, 0);
2424 }
2425
2426 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2427 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2428 id, command);
2429
2430 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2431
2432 /* Poll until completion */
2433 while (!REG_RD(p_hwfn, addr) && count--)
2434 msleep(FINAL_CLEANUP_POLL_TIME);
2435
2436 if (REG_RD(p_hwfn, addr))
2437 rc = 0;
2438 else
2439 DP_NOTICE(p_hwfn,
2440 "Failed to receive FW final cleanup notification\n");
2441
2442 /* Cleanup afterwards */
2443 REG_WR(p_hwfn, addr, 0);
2444
2445 return rc;
2446 }
2447
2448 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2449 {
2450 int hw_mode = 0;
2451
2452 if (QED_IS_BB_B0(p_hwfn->cdev)) {
2453 hw_mode |= 1 << MODE_BB;
2454 } else if (QED_IS_AH(p_hwfn->cdev)) {
2455 hw_mode |= 1 << MODE_K2;
2456 } else {
2457 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2458 p_hwfn->cdev->type);
2459 return -EINVAL;
2460 }
2461
2462 switch (p_hwfn->cdev->num_ports_in_engine) {
2463 case 1:
2464 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2465 break;
2466 case 2:
2467 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2468 break;
2469 case 4:
2470 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2471 break;
2472 default:
2473 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2474 p_hwfn->cdev->num_ports_in_engine);
2475 return -EINVAL;
2476 }
2477
2478 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2479 hw_mode |= 1 << MODE_MF_SD;
2480 else
2481 hw_mode |= 1 << MODE_MF_SI;
2482
2483 hw_mode |= 1 << MODE_ASIC;
2484
2485 if (p_hwfn->cdev->num_hwfns > 1)
2486 hw_mode |= 1 << MODE_100G;
2487
2488 p_hwfn->hw_info.hw_mode = hw_mode;
2489
2490 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2491 "Configuring function for hw_mode: 0x%08x\n",
2492 p_hwfn->hw_info.hw_mode);
2493
2494 return 0;
2495 }
2496
2497 /* Init run time data for all PFs on an engine. */
2498 static void qed_init_cau_rt_data(struct qed_dev *cdev)
2499 {
2500 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2501 int i, igu_sb_id;
2502
2503 for_each_hwfn(cdev, i) {
2504 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2505 struct qed_igu_info *p_igu_info;
2506 struct qed_igu_block *p_block;
2507 struct cau_sb_entry sb_entry;
2508
2509 p_igu_info = p_hwfn->hw_info.p_igu_info;
2510
2511 for (igu_sb_id = 0;
2512 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2513 p_block = &p_igu_info->entry[igu_sb_id];
2514
2515 if (!p_block->is_pf)
2516 continue;
2517
2518 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2519 p_block->function_id, 0, 0);
2520 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2521 sb_entry);
2522 }
2523 }
2524 }
2525
2526 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2527 struct qed_ptt *p_ptt)
2528 {
2529 u32 val, wr_mbs, cache_line_size;
2530
2531 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2532 switch (val) {
2533 case 0:
2534 wr_mbs = 128;
2535 break;
2536 case 1:
2537 wr_mbs = 256;
2538 break;
2539 case 2:
2540 wr_mbs = 512;
2541 break;
2542 default:
2543 DP_INFO(p_hwfn,
2544 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2545 val);
2546 return;
2547 }
2548
2549 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2550 switch (cache_line_size) {
2551 case 32:
2552 val = 0;
2553 break;
2554 case 64:
2555 val = 1;
2556 break;
2557 case 128:
2558 val = 2;
2559 break;
2560 case 256:
2561 val = 3;
2562 break;
2563 default:
2564 DP_INFO(p_hwfn,
2565 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2566 cache_line_size);
2567 }
2568
2569 if (L1_CACHE_BYTES > wr_mbs)
2570 DP_INFO(p_hwfn,
2571 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2572 L1_CACHE_BYTES, wr_mbs);
2573
2574 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2575 if (val > 0) {
2576 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2577 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2578 }
2579 }
2580
2581 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2582 struct qed_ptt *p_ptt, int hw_mode)
2583 {
2584 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2585 struct qed_qm_common_rt_init_params params;
2586 struct qed_dev *cdev = p_hwfn->cdev;
2587 u8 vf_id, max_num_vfs;
2588 u16 num_pfs, pf_id;
2589 u32 concrete_fid;
2590 int rc = 0;
2591
2592 qed_init_cau_rt_data(cdev);
2593
2594 /* Program GTT windows */
2595 qed_gtt_init(p_hwfn);
2596
2597 if (p_hwfn->mcp_info) {
2598 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2599 qm_info->pf_rl_en = true;
2600 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2601 qm_info->pf_wfq_en = true;
2602 }
2603
2604 memset(&params, 0, sizeof(params));
2605 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2606 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2607 params.pf_rl_en = qm_info->pf_rl_en;
2608 params.pf_wfq_en = qm_info->pf_wfq_en;
2609 params.global_rl_en = qm_info->vport_rl_en;
2610 params.vport_wfq_en = qm_info->vport_wfq_en;
2611 params.port_params = qm_info->qm_port_params;
2612
2613 qed_qm_common_rt_init(p_hwfn, &params);
2614
2615 qed_cxt_hw_init_common(p_hwfn);
2616
2617 qed_init_cache_line_size(p_hwfn, p_ptt);
2618
2619 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2620 if (rc)
2621 return rc;
2622
2623 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2624 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2625
2626 if (QED_IS_BB(p_hwfn->cdev)) {
2627 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2628 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2629 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2630 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2631 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2632 }
2633 /* pretend to original PF */
2634 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2635 }
2636
2637 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2638 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2639 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2640 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2641 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2642 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2643 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2644 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2645 }
2646 /* pretend to original PF */
2647 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2648
2649 return rc;
2650 }
2651
2652 static int
2653 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2654 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2655 {
2656 u32 dpi_bit_shift, dpi_count, dpi_page_size;
2657 u32 min_dpis;
2658 u32 n_wids;
2659
2660 /* Calculate DPI size */
2661 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2662 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2663 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2664 dpi_bit_shift = ilog2(dpi_page_size / 4096);
2665 dpi_count = pwm_region_size / dpi_page_size;
2666
2667 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2668 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2669
2670 p_hwfn->dpi_size = dpi_page_size;
2671 p_hwfn->dpi_count = dpi_count;
2672
2673 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2674
2675 if (dpi_count < min_dpis)
2676 return -EINVAL;
2677
2678 return 0;
2679 }
2680
2681 enum QED_ROCE_EDPM_MODE {
2682 QED_ROCE_EDPM_MODE_ENABLE = 0,
2683 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2684 QED_ROCE_EDPM_MODE_DISABLE = 2,
2685 };
2686
2687 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2688 {
2689 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2690 return false;
2691
2692 return true;
2693 }
2694
2695 static int
2696 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2697 {
2698 u32 pwm_regsize, norm_regsize;
2699 u32 non_pwm_conn, min_addr_reg1;
2700 u32 db_bar_size, n_cpus = 1;
2701 u32 roce_edpm_mode;
2702 u32 pf_dems_shift;
2703 int rc = 0;
2704 u8 cond;
2705
2706 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2707 if (p_hwfn->cdev->num_hwfns > 1)
2708 db_bar_size /= 2;
2709
2710 /* Calculate doorbell regions */
2711 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2712 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2713 NULL) +
2714 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2715 NULL);
2716 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2717 min_addr_reg1 = norm_regsize / 4096;
2718 pwm_regsize = db_bar_size - norm_regsize;
2719
2720 /* Check that the normal and PWM sizes are valid */
2721 if (db_bar_size < norm_regsize) {
2722 DP_ERR(p_hwfn->cdev,
2723 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2724 db_bar_size, norm_regsize);
2725 return -EINVAL;
2726 }
2727
2728 if (pwm_regsize < QED_MIN_PWM_REGION) {
2729 DP_ERR(p_hwfn->cdev,
2730 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2731 pwm_regsize,
2732 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2733 return -EINVAL;
2734 }
2735
2736 /* Calculate number of DPIs */
2737 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2738 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2739 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2740 /* Either EDPM is mandatory, or we are attempting to allocate a
2741 * WID per CPU.
2742 */
2743 n_cpus = num_present_cpus();
2744 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2745 }
2746
2747 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2748 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2749 if (cond || p_hwfn->dcbx_no_edpm) {
2750 /* Either EDPM is disabled from user configuration, or it is
2751 * disabled via DCBx, or it is not mandatory and we failed to
2752 * allocated a WID per CPU.
2753 */
2754 n_cpus = 1;
2755 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2756
2757 if (cond)
2758 qed_rdma_dpm_bar(p_hwfn, p_ptt);
2759 }
2760
2761 p_hwfn->wid_count = (u16) n_cpus;
2762
2763 DP_INFO(p_hwfn,
2764 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2765 norm_regsize,
2766 pwm_regsize,
2767 p_hwfn->dpi_size,
2768 p_hwfn->dpi_count,
2769 (!qed_edpm_enabled(p_hwfn)) ?
2770 "disabled" : "enabled", PAGE_SIZE);
2771
2772 if (rc) {
2773 DP_ERR(p_hwfn,
2774 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2775 p_hwfn->dpi_count,
2776 p_hwfn->pf_params.rdma_pf_params.min_dpis);
2777 return -EINVAL;
2778 }
2779
2780 p_hwfn->dpi_start_offset = norm_regsize;
2781
2782 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2783 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2784 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2785 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2786
2787 return 0;
2788 }
2789
2790 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2791 struct qed_ptt *p_ptt, int hw_mode)
2792 {
2793 int rc = 0;
2794
2795 /* In CMT the gate should be cleared by the 2nd hwfn */
2796 if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2797 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2798
2799 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2800 if (rc)
2801 return rc;
2802
2803 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2804
2805 return 0;
2806 }
2807
2808 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2809 struct qed_ptt *p_ptt,
2810 struct qed_tunnel_info *p_tunn,
2811 int hw_mode,
2812 bool b_hw_start,
2813 enum qed_int_mode int_mode,
2814 bool allow_npar_tx_switch)
2815 {
2816 u8 rel_pf_id = p_hwfn->rel_pf_id;
2817 int rc = 0;
2818
2819 if (p_hwfn->mcp_info) {
2820 struct qed_mcp_function_info *p_info;
2821
2822 p_info = &p_hwfn->mcp_info->func_info;
2823 if (p_info->bandwidth_min)
2824 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2825
2826 /* Update rate limit once we'll actually have a link */
2827 p_hwfn->qm_info.pf_rl = 100000;
2828 }
2829
2830 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2831
2832 qed_int_igu_init_rt(p_hwfn);
2833
2834 /* Set VLAN in NIG if needed */
2835 if (hw_mode & BIT(MODE_MF_SD)) {
2836 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2837 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2838 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2839 p_hwfn->hw_info.ovlan);
2840
2841 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2842 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2843 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2844 1);
2845 }
2846
2847 /* Enable classification by MAC if needed */
2848 if (hw_mode & BIT(MODE_MF_SI)) {
2849 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2850 "Configuring TAGMAC_CLS_TYPE\n");
2851 STORE_RT_REG(p_hwfn,
2852 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2853 }
2854
2855 /* Protocol Configuration */
2856 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2857 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
2858 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2859 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2860 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2861
2862 /* Sanity check before the PF init sequence that uses DMAE */
2863 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2864 if (rc)
2865 return rc;
2866
2867 /* PF Init sequence */
2868 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2869 if (rc)
2870 return rc;
2871
2872 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2873 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2874 if (rc)
2875 return rc;
2876
2877 qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
2878
2879 /* Pure runtime initializations - directly to the HW */
2880 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2881
2882 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2883 if (rc)
2884 return rc;
2885
2886 /* Use the leading hwfn since in CMT only NIG #0 is operational */
2887 if (IS_LEAD_HWFN(p_hwfn)) {
2888 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2889 if (rc)
2890 return rc;
2891 }
2892
2893 if (b_hw_start) {
2894 /* enable interrupts */
2895 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2896
2897 /* send function start command */
2898 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2899 allow_npar_tx_switch);
2900 if (rc) {
2901 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2902 return rc;
2903 }
2904 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2905 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2906 qed_wr(p_hwfn, p_ptt,
2907 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2908 0x100);
2909 }
2910 }
2911 return rc;
2912 }
2913
2914 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2915 struct qed_ptt *p_ptt, bool b_enable)
2916 {
2917 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2918
2919 /* Configure the PF's internal FID_enable for master transactions */
2920 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2921
2922 /* Wait until value is set - try for 1 second every 50us */
2923 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2924 val = qed_rd(p_hwfn, p_ptt,
2925 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2926 if (val == set_val)
2927 break;
2928
2929 usleep_range(50, 60);
2930 }
2931
2932 if (val != set_val) {
2933 DP_NOTICE(p_hwfn,
2934 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2935 return -EAGAIN;
2936 }
2937
2938 return 0;
2939 }
2940
2941 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2942 struct qed_ptt *p_main_ptt)
2943 {
2944 /* Read shadow of current MFW mailbox */
2945 qed_mcp_read_mb(p_hwfn, p_main_ptt);
2946 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2947 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2948 }
2949
2950 static void
2951 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2952 struct qed_drv_load_params *p_drv_load)
2953 {
2954 memset(p_load_req, 0, sizeof(*p_load_req));
2955
2956 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2957 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2958 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2959 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2960 p_load_req->override_force_load = p_drv_load->override_force_load;
2961 }
2962
2963 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2964 struct qed_hw_init_params *p_params)
2965 {
2966 if (p_params->p_tunn) {
2967 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2968 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2969 }
2970
2971 p_hwfn->b_int_enabled = true;
2972
2973 return 0;
2974 }
2975
2976 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2977 {
2978 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2979 BIT(p_hwfn->abs_pf_id));
2980 }
2981
2982 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
2983 {
2984 struct qed_load_req_params load_req_params;
2985 u32 load_code, resp, param, drv_mb_param;
2986 bool b_default_mtu = true;
2987 struct qed_hwfn *p_hwfn;
2988 const u32 *fw_overlays;
2989 u32 fw_overlays_len;
2990 u16 ether_type;
2991 int rc = 0, i;
2992
2993 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
2994 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
2995 return -EINVAL;
2996 }
2997
2998 if (IS_PF(cdev)) {
2999 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3000 if (rc)
3001 return rc;
3002 }
3003
3004 for_each_hwfn(cdev, i) {
3005 p_hwfn = &cdev->hwfns[i];
3006
3007 /* If management didn't provide a default, set one of our own */
3008 if (!p_hwfn->hw_info.mtu) {
3009 p_hwfn->hw_info.mtu = 1500;
3010 b_default_mtu = false;
3011 }
3012
3013 if (IS_VF(cdev)) {
3014 qed_vf_start(p_hwfn, p_params);
3015 continue;
3016 }
3017
3018 rc = qed_calc_hw_mode(p_hwfn);
3019 if (rc)
3020 return rc;
3021
3022 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3023 &cdev->mf_bits) ||
3024 test_bit(QED_MF_8021AD_TAGGING,
3025 &cdev->mf_bits))) {
3026 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3027 ether_type = ETH_P_8021Q;
3028 else
3029 ether_type = ETH_P_8021AD;
3030 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3031 ether_type);
3032 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3033 ether_type);
3034 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3035 ether_type);
3036 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3037 ether_type);
3038 }
3039
3040 qed_fill_load_req_params(&load_req_params,
3041 p_params->p_drv_load_params);
3042 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3043 &load_req_params);
3044 if (rc) {
3045 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3046 return rc;
3047 }
3048
3049 load_code = load_req_params.load_code;
3050 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3051 "Load request was sent. Load code: 0x%x\n",
3052 load_code);
3053
3054 /* Only relevant for recovery:
3055 * Clear the indication after LOAD_REQ is responded by the MFW.
3056 */
3057 cdev->recov_in_prog = false;
3058
3059 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3060
3061 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3062
3063 /* Clean up chip from previous driver if such remains exist.
3064 * This is not needed when the PF is the first one on the
3065 * engine, since afterwards we are going to init the FW.
3066 */
3067 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3068 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3069 p_hwfn->rel_pf_id, false);
3070 if (rc) {
3071 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt,
3072 QED_HW_ERR_RAMROD_FAIL,
3073 "Final cleanup failed\n");
3074 goto load_err;
3075 }
3076 }
3077
3078 /* Log and clear previous pglue_b errors if such exist */
3079 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3080
3081 /* Enable the PF's internal FID_enable in the PXP */
3082 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3083 true);
3084 if (rc)
3085 goto load_err;
3086
3087 /* Clear the pglue_b was_error indication.
3088 * In E4 it must be done after the BME and the internal
3089 * FID_enable for the PF are set, since VDMs may cause the
3090 * indication to be set again.
3091 */
3092 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3093
3094 fw_overlays = cdev->fw_data->fw_overlays;
3095 fw_overlays_len = cdev->fw_data->fw_overlays_len;
3096 p_hwfn->fw_overlay_mem =
3097 qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3098 fw_overlays_len);
3099 if (!p_hwfn->fw_overlay_mem) {
3100 DP_NOTICE(p_hwfn,
3101 "Failed to allocate fw overlay memory\n");
3102 rc = -ENOMEM;
3103 goto load_err;
3104 }
3105
3106 switch (load_code) {
3107 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3108 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3109 p_hwfn->hw_info.hw_mode);
3110 if (rc)
3111 break;
3112 fallthrough;
3113 case FW_MSG_CODE_DRV_LOAD_PORT:
3114 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3115 p_hwfn->hw_info.hw_mode);
3116 if (rc)
3117 break;
3118
3119 fallthrough;
3120 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3121 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3122 p_params->p_tunn,
3123 p_hwfn->hw_info.hw_mode,
3124 p_params->b_hw_start,
3125 p_params->int_mode,
3126 p_params->allow_npar_tx_switch);
3127 break;
3128 default:
3129 DP_NOTICE(p_hwfn,
3130 "Unexpected load code [0x%08x]", load_code);
3131 rc = -EINVAL;
3132 break;
3133 }
3134
3135 if (rc) {
3136 DP_NOTICE(p_hwfn,
3137 "init phase failed for loadcode 0x%x (rc %d)\n",
3138 load_code, rc);
3139 goto load_err;
3140 }
3141
3142 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3143 if (rc)
3144 return rc;
3145
3146 /* send DCBX attention request command */
3147 DP_VERBOSE(p_hwfn,
3148 QED_MSG_DCB,
3149 "sending phony dcbx set command to trigger DCBx attention handling\n");
3150 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3151 DRV_MSG_CODE_SET_DCBX,
3152 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3153 &resp, &param);
3154 if (rc) {
3155 DP_NOTICE(p_hwfn,
3156 "Failed to send DCBX attention request\n");
3157 return rc;
3158 }
3159
3160 p_hwfn->hw_init_done = true;
3161 }
3162
3163 if (IS_PF(cdev)) {
3164 p_hwfn = QED_LEADING_HWFN(cdev);
3165
3166 /* Get pre-negotiated values for stag, bandwidth etc. */
3167 DP_VERBOSE(p_hwfn,
3168 QED_MSG_SPQ,
3169 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3170 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3171 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3172 DRV_MSG_CODE_GET_OEM_UPDATES,
3173 drv_mb_param, &resp, &param);
3174 if (rc)
3175 DP_NOTICE(p_hwfn,
3176 "Failed to send GET_OEM_UPDATES attention request\n");
3177
3178 drv_mb_param = STORM_FW_VERSION;
3179 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3180 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3181 drv_mb_param, &load_code, &param);
3182 if (rc)
3183 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3184
3185 if (!b_default_mtu) {
3186 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3187 p_hwfn->hw_info.mtu);
3188 if (rc)
3189 DP_INFO(p_hwfn,
3190 "Failed to update default mtu\n");
3191 }
3192
3193 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3194 p_hwfn->p_main_ptt,
3195 QED_OV_DRIVER_STATE_DISABLED);
3196 if (rc)
3197 DP_INFO(p_hwfn, "Failed to update driver state\n");
3198
3199 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3200 QED_OV_ESWITCH_NONE);
3201 if (rc)
3202 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3203 }
3204
3205 return 0;
3206
3207 load_err:
3208 /* The MFW load lock should be released also when initialization fails.
3209 */
3210 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3211 return rc;
3212 }
3213
3214 #define QED_HW_STOP_RETRY_LIMIT (10)
3215 static void qed_hw_timers_stop(struct qed_dev *cdev,
3216 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3217 {
3218 int i;
3219
3220 /* close timers */
3221 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3222 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3223
3224 if (cdev->recov_in_prog)
3225 return;
3226
3227 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3228 if ((!qed_rd(p_hwfn, p_ptt,
3229 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3230 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3231 break;
3232
3233 /* Dependent on number of connection/tasks, possibly
3234 * 1ms sleep is required between polls
3235 */
3236 usleep_range(1000, 2000);
3237 }
3238
3239 if (i < QED_HW_STOP_RETRY_LIMIT)
3240 return;
3241
3242 DP_NOTICE(p_hwfn,
3243 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3244 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3245 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3246 }
3247
3248 void qed_hw_timers_stop_all(struct qed_dev *cdev)
3249 {
3250 int j;
3251
3252 for_each_hwfn(cdev, j) {
3253 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3254 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3255
3256 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3257 }
3258 }
3259
3260 int qed_hw_stop(struct qed_dev *cdev)
3261 {
3262 struct qed_hwfn *p_hwfn;
3263 struct qed_ptt *p_ptt;
3264 int rc, rc2 = 0;
3265 int j;
3266
3267 for_each_hwfn(cdev, j) {
3268 p_hwfn = &cdev->hwfns[j];
3269 p_ptt = p_hwfn->p_main_ptt;
3270
3271 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3272
3273 if (IS_VF(cdev)) {
3274 qed_vf_pf_int_cleanup(p_hwfn);
3275 rc = qed_vf_pf_reset(p_hwfn);
3276 if (rc) {
3277 DP_NOTICE(p_hwfn,
3278 "qed_vf_pf_reset failed. rc = %d.\n",
3279 rc);
3280 rc2 = -EINVAL;
3281 }
3282 continue;
3283 }
3284
3285 /* mark the hw as uninitialized... */
3286 p_hwfn->hw_init_done = false;
3287
3288 /* Send unload command to MCP */
3289 if (!cdev->recov_in_prog) {
3290 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3291 if (rc) {
3292 DP_NOTICE(p_hwfn,
3293 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3294 rc);
3295 rc2 = -EINVAL;
3296 }
3297 }
3298
3299 qed_slowpath_irq_sync(p_hwfn);
3300
3301 /* After this point no MFW attentions are expected, e.g. prevent
3302 * race between pf stop and dcbx pf update.
3303 */
3304 rc = qed_sp_pf_stop(p_hwfn);
3305 if (rc) {
3306 DP_NOTICE(p_hwfn,
3307 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3308 rc);
3309 rc2 = -EINVAL;
3310 }
3311
3312 qed_wr(p_hwfn, p_ptt,
3313 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3314
3315 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3316 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3317 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3318 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3319 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3320
3321 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3322
3323 /* Disable Attention Generation */
3324 qed_int_igu_disable_int(p_hwfn, p_ptt);
3325
3326 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3327 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3328
3329 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3330
3331 /* Need to wait 1ms to guarantee SBs are cleared */
3332 usleep_range(1000, 2000);
3333
3334 /* Disable PF in HW blocks */
3335 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3336 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3337
3338 if (IS_LEAD_HWFN(p_hwfn) &&
3339 test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3340 !QED_IS_FCOE_PERSONALITY(p_hwfn))
3341 qed_llh_remove_mac_filter(cdev, 0,
3342 p_hwfn->hw_info.hw_mac_addr);
3343
3344 if (!cdev->recov_in_prog) {
3345 rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3346 if (rc) {
3347 DP_NOTICE(p_hwfn,
3348 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3349 rc);
3350 rc2 = -EINVAL;
3351 }
3352 }
3353 }
3354
3355 if (IS_PF(cdev) && !cdev->recov_in_prog) {
3356 p_hwfn = QED_LEADING_HWFN(cdev);
3357 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3358
3359 /* Clear the PF's internal FID_enable in the PXP.
3360 * In CMT this should only be done for first hw-function, and
3361 * only after all transactions have stopped for all active
3362 * hw-functions.
3363 */
3364 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3365 if (rc) {
3366 DP_NOTICE(p_hwfn,
3367 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3368 rc);
3369 rc2 = -EINVAL;
3370 }
3371 }
3372
3373 return rc2;
3374 }
3375
3376 int qed_hw_stop_fastpath(struct qed_dev *cdev)
3377 {
3378 int j;
3379
3380 for_each_hwfn(cdev, j) {
3381 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3382 struct qed_ptt *p_ptt;
3383
3384 if (IS_VF(cdev)) {
3385 qed_vf_pf_int_cleanup(p_hwfn);
3386 continue;
3387 }
3388 p_ptt = qed_ptt_acquire(p_hwfn);
3389 if (!p_ptt)
3390 return -EAGAIN;
3391
3392 DP_VERBOSE(p_hwfn,
3393 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3394
3395 qed_wr(p_hwfn, p_ptt,
3396 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3397
3398 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3399 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3400 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3401 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3402 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3403
3404 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3405
3406 /* Need to wait 1ms to guarantee SBs are cleared */
3407 usleep_range(1000, 2000);
3408 qed_ptt_release(p_hwfn, p_ptt);
3409 }
3410
3411 return 0;
3412 }
3413
3414 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3415 {
3416 struct qed_ptt *p_ptt;
3417
3418 if (IS_VF(p_hwfn->cdev))
3419 return 0;
3420
3421 p_ptt = qed_ptt_acquire(p_hwfn);
3422 if (!p_ptt)
3423 return -EAGAIN;
3424
3425 if (p_hwfn->p_rdma_info &&
3426 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3427 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3428
3429 /* Re-open incoming traffic */
3430 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3431 qed_ptt_release(p_hwfn, p_ptt);
3432
3433 return 0;
3434 }
3435
3436 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3437 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3438 {
3439 qed_ptt_pool_free(p_hwfn);
3440 kfree(p_hwfn->hw_info.p_igu_info);
3441 p_hwfn->hw_info.p_igu_info = NULL;
3442 }
3443
3444 /* Setup bar access */
3445 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3446 {
3447 /* clear indirect access */
3448 if (QED_IS_AH(p_hwfn->cdev)) {
3449 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3450 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3451 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3452 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3453 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3454 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3455 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3456 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3457 } else {
3458 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3459 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3460 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3461 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3462 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3463 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3464 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3465 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3466 }
3467
3468 /* Clean previous pglue_b errors if such exist */
3469 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3470
3471 /* enable internal target-read */
3472 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3473 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3474 }
3475
3476 static void get_function_id(struct qed_hwfn *p_hwfn)
3477 {
3478 /* ME Register */
3479 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3480 PXP_PF_ME_OPAQUE_ADDR);
3481
3482 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3483
3484 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3485 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3486 PXP_CONCRETE_FID_PFID);
3487 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3488 PXP_CONCRETE_FID_PORT);
3489
3490 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3491 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3492 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3493 }
3494
3495 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3496 {
3497 u32 *feat_num = p_hwfn->hw_info.feat_num;
3498 struct qed_sb_cnt_info sb_cnt;
3499 u32 non_l2_sbs = 0;
3500
3501 memset(&sb_cnt, 0, sizeof(sb_cnt));
3502 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3503
3504 if (IS_ENABLED(CONFIG_QED_RDMA) &&
3505 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3506 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3507 * the status blocks equally between L2 / RoCE but with
3508 * consideration as to how many l2 queues / cnqs we have.
3509 */
3510 feat_num[QED_RDMA_CNQ] =
3511 min_t(u32, sb_cnt.cnt / 2,
3512 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3513
3514 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3515 }
3516 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3517 /* Start by allocating VF queues, then PF's */
3518 feat_num[QED_VF_L2_QUE] = min_t(u32,
3519 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3520 sb_cnt.iov_cnt);
3521 feat_num[QED_PF_L2_QUE] = min_t(u32,
3522 sb_cnt.cnt - non_l2_sbs,
3523 RESC_NUM(p_hwfn,
3524 QED_L2_QUEUE) -
3525 FEAT_NUM(p_hwfn,
3526 QED_VF_L2_QUE));
3527 }
3528
3529 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3530 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
3531 RESC_NUM(p_hwfn,
3532 QED_CMDQS_CQS));
3533
3534 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3535 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3536 RESC_NUM(p_hwfn,
3537 QED_CMDQS_CQS));
3538 DP_VERBOSE(p_hwfn,
3539 NETIF_MSG_PROBE,
3540 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
3541 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3542 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3543 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3544 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3545 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3546 (int)sb_cnt.cnt);
3547 }
3548
3549 const char *qed_hw_get_resc_name(enum qed_resources res_id)
3550 {
3551 switch (res_id) {
3552 case QED_L2_QUEUE:
3553 return "L2_QUEUE";
3554 case QED_VPORT:
3555 return "VPORT";
3556 case QED_RSS_ENG:
3557 return "RSS_ENG";
3558 case QED_PQ:
3559 return "PQ";
3560 case QED_RL:
3561 return "RL";
3562 case QED_MAC:
3563 return "MAC";
3564 case QED_VLAN:
3565 return "VLAN";
3566 case QED_RDMA_CNQ_RAM:
3567 return "RDMA_CNQ_RAM";
3568 case QED_ILT:
3569 return "ILT";
3570 case QED_LL2_RAM_QUEUE:
3571 return "LL2_RAM_QUEUE";
3572 case QED_LL2_CTX_QUEUE:
3573 return "LL2_CTX_QUEUE";
3574 case QED_CMDQS_CQS:
3575 return "CMDQS_CQS";
3576 case QED_RDMA_STATS_QUEUE:
3577 return "RDMA_STATS_QUEUE";
3578 case QED_BDQ:
3579 return "BDQ";
3580 case QED_SB:
3581 return "SB";
3582 default:
3583 return "UNKNOWN_RESOURCE";
3584 }
3585 }
3586
3587 static int
3588 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3589 struct qed_ptt *p_ptt,
3590 enum qed_resources res_id,
3591 u32 resc_max_val, u32 *p_mcp_resp)
3592 {
3593 int rc;
3594
3595 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3596 resc_max_val, p_mcp_resp);
3597 if (rc) {
3598 DP_NOTICE(p_hwfn,
3599 "MFW response failure for a max value setting of resource %d [%s]\n",
3600 res_id, qed_hw_get_resc_name(res_id));
3601 return rc;
3602 }
3603
3604 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3605 DP_INFO(p_hwfn,
3606 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3607 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3608
3609 return 0;
3610 }
3611
3612 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
3613 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
3614 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
3615 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
3616 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
3617 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
3618 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
3619 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
3620 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
3621 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
3622 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
3623 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
3624 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
3625 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
3626 };
3627
3628 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
3629 {
3630 enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
3631
3632 if (type >= QED_NUM_HSI_DEFS) {
3633 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
3634 return 0;
3635 }
3636
3637 return qed_hsi_def_val[type][chip_id];
3638 }
3639 static int
3640 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3641 {
3642 u32 resc_max_val, mcp_resp;
3643 u8 res_id;
3644 int rc;
3645 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3646 switch (res_id) {
3647 case QED_LL2_RAM_QUEUE:
3648 resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;
3649 break;
3650 case QED_LL2_CTX_QUEUE:
3651 resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;
3652 break;
3653 case QED_RDMA_CNQ_RAM:
3654 /* No need for a case for QED_CMDQS_CQS since
3655 * CNQ/CMDQS are the same resource.
3656 */
3657 resc_max_val = NUM_OF_GLOBAL_QUEUES;
3658 break;
3659 case QED_RDMA_STATS_QUEUE:
3660 resc_max_val =
3661 NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
3662 break;
3663 case QED_BDQ:
3664 resc_max_val = BDQ_NUM_RESOURCES;
3665 break;
3666 default:
3667 continue;
3668 }
3669
3670 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3671 resc_max_val, &mcp_resp);
3672 if (rc)
3673 return rc;
3674
3675 /* There's no point to continue to the next resource if the
3676 * command is not supported by the MFW.
3677 * We do continue if the command is supported but the resource
3678 * is unknown to the MFW. Such a resource will be later
3679 * configured with the default allocation values.
3680 */
3681 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3682 return -EINVAL;
3683 }
3684
3685 return 0;
3686 }
3687
3688 static
3689 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3690 enum qed_resources res_id,
3691 u32 *p_resc_num, u32 *p_resc_start)
3692 {
3693 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3694 struct qed_dev *cdev = p_hwfn->cdev;
3695
3696 switch (res_id) {
3697 case QED_L2_QUEUE:
3698 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
3699 break;
3700 case QED_VPORT:
3701 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
3702 break;
3703 case QED_RSS_ENG:
3704 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
3705 break;
3706 case QED_PQ:
3707 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
3708 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
3709 break;
3710 case QED_RL:
3711 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
3712 break;
3713 case QED_MAC:
3714 case QED_VLAN:
3715 /* Each VFC resource can accommodate both a MAC and a VLAN */
3716 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3717 break;
3718 case QED_ILT:
3719 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
3720 break;
3721 case QED_LL2_RAM_QUEUE:
3722 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
3723 break;
3724 case QED_LL2_CTX_QUEUE:
3725 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;
3726 break;
3727 case QED_RDMA_CNQ_RAM:
3728 case QED_CMDQS_CQS:
3729 /* CNQ/CMDQS are the same resource */
3730 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3731 break;
3732 case QED_RDMA_STATS_QUEUE:
3733 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
3734 break;
3735 case QED_BDQ:
3736 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3737 p_hwfn->hw_info.personality != QED_PCI_FCOE)
3738 *p_resc_num = 0;
3739 else
3740 *p_resc_num = 1;
3741 break;
3742 case QED_SB:
3743 /* Since we want its value to reflect whether MFW supports
3744 * the new scheme, have a default of 0.
3745 */
3746 *p_resc_num = 0;
3747 break;
3748 default:
3749 return -EINVAL;
3750 }
3751
3752 switch (res_id) {
3753 case QED_BDQ:
3754 if (!*p_resc_num)
3755 *p_resc_start = 0;
3756 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3757 *p_resc_start = p_hwfn->port_id;
3758 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
3759 *p_resc_start = p_hwfn->port_id;
3760 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3761 *p_resc_start = p_hwfn->port_id + 2;
3762 break;
3763 default:
3764 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3765 break;
3766 }
3767
3768 return 0;
3769 }
3770
3771 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3772 enum qed_resources res_id)
3773 {
3774 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3775 u32 mcp_resp, *p_resc_num, *p_resc_start;
3776 int rc;
3777
3778 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3779 p_resc_start = &RESC_START(p_hwfn, res_id);
3780
3781 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3782 &dflt_resc_start);
3783 if (rc) {
3784 DP_ERR(p_hwfn,
3785 "Failed to get default amount for resource %d [%s]\n",
3786 res_id, qed_hw_get_resc_name(res_id));
3787 return rc;
3788 }
3789
3790 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3791 &mcp_resp, p_resc_num, p_resc_start);
3792 if (rc) {
3793 DP_NOTICE(p_hwfn,
3794 "MFW response failure for an allocation request for resource %d [%s]\n",
3795 res_id, qed_hw_get_resc_name(res_id));
3796 return rc;
3797 }
3798
3799 /* Default driver values are applied in the following cases:
3800 * - The resource allocation MB command is not supported by the MFW
3801 * - There is an internal error in the MFW while processing the request
3802 * - The resource ID is unknown to the MFW
3803 */
3804 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3805 DP_INFO(p_hwfn,
3806 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3807 res_id,
3808 qed_hw_get_resc_name(res_id),
3809 mcp_resp, dflt_resc_num, dflt_resc_start);
3810 *p_resc_num = dflt_resc_num;
3811 *p_resc_start = dflt_resc_start;
3812 goto out;
3813 }
3814
3815 out:
3816 /* PQs have to divide by 8 [that's the HW granularity].
3817 * Reduce number so it would fit.
3818 */
3819 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3820 DP_INFO(p_hwfn,
3821 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3822 *p_resc_num,
3823 (*p_resc_num) & ~0x7,
3824 *p_resc_start, (*p_resc_start) & ~0x7);
3825 *p_resc_num &= ~0x7;
3826 *p_resc_start &= ~0x7;
3827 }
3828
3829 return 0;
3830 }
3831
3832 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3833 {
3834 int rc;
3835 u8 res_id;
3836
3837 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3838 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3839 if (rc)
3840 return rc;
3841 }
3842
3843 return 0;
3844 }
3845
3846 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3847 struct qed_ptt *p_ptt)
3848 {
3849 struct qed_dev *cdev = p_hwfn->cdev;
3850 u8 native_ppfid_idx;
3851 int rc;
3852
3853 /* Calculation of BB/AH is different for native_ppfid_idx */
3854 if (QED_IS_BB(cdev))
3855 native_ppfid_idx = p_hwfn->rel_pf_id;
3856 else
3857 native_ppfid_idx = p_hwfn->rel_pf_id /
3858 cdev->num_ports_in_engine;
3859
3860 rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3861 if (rc != 0 && rc != -EOPNOTSUPP)
3862 return rc;
3863 else if (rc == -EOPNOTSUPP)
3864 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3865
3866 if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3867 DP_INFO(p_hwfn,
3868 "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3869 native_ppfid_idx, cdev->ppfid_bitmap);
3870 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3871 }
3872
3873 return 0;
3874 }
3875
3876 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3877 {
3878 struct qed_resc_unlock_params resc_unlock_params;
3879 struct qed_resc_lock_params resc_lock_params;
3880 bool b_ah = QED_IS_AH(p_hwfn->cdev);
3881 u8 res_id;
3882 int rc;
3883
3884 /* Setting the max values of the soft resources and the following
3885 * resources allocation queries should be atomic. Since several PFs can
3886 * run in parallel - a resource lock is needed.
3887 * If either the resource lock or resource set value commands are not
3888 * supported - skip the the max values setting, release the lock if
3889 * needed, and proceed to the queries. Other failures, including a
3890 * failure to acquire the lock, will cause this function to fail.
3891 */
3892 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3893 QED_RESC_LOCK_RESC_ALLOC, false);
3894
3895 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3896 if (rc && rc != -EINVAL) {
3897 return rc;
3898 } else if (rc == -EINVAL) {
3899 DP_INFO(p_hwfn,
3900 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3901 } else if (!rc && !resc_lock_params.b_granted) {
3902 DP_NOTICE(p_hwfn,
3903 "Failed to acquire the resource lock for the resource allocation commands\n");
3904 return -EBUSY;
3905 } else {
3906 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3907 if (rc && rc != -EINVAL) {
3908 DP_NOTICE(p_hwfn,
3909 "Failed to set the max values of the soft resources\n");
3910 goto unlock_and_exit;
3911 } else if (rc == -EINVAL) {
3912 DP_INFO(p_hwfn,
3913 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3914 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3915 &resc_unlock_params);
3916 if (rc)
3917 DP_INFO(p_hwfn,
3918 "Failed to release the resource lock for the resource allocation commands\n");
3919 }
3920 }
3921
3922 rc = qed_hw_set_resc_info(p_hwfn);
3923 if (rc)
3924 goto unlock_and_exit;
3925
3926 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3927 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3928 if (rc)
3929 DP_INFO(p_hwfn,
3930 "Failed to release the resource lock for the resource allocation commands\n");
3931 }
3932
3933 /* PPFID bitmap */
3934 if (IS_LEAD_HWFN(p_hwfn)) {
3935 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3936 if (rc)
3937 return rc;
3938 }
3939
3940 /* Sanity for ILT */
3941 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3942 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3943 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3944 RESC_START(p_hwfn, QED_ILT),
3945 RESC_END(p_hwfn, QED_ILT) - 1);
3946 return -EINVAL;
3947 }
3948
3949 /* This will also learn the number of SBs from MFW */
3950 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3951 return -EINVAL;
3952
3953 qed_hw_set_feat(p_hwfn);
3954
3955 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3956 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3957 qed_hw_get_resc_name(res_id),
3958 RESC_NUM(p_hwfn, res_id),
3959 RESC_START(p_hwfn, res_id));
3960
3961 return 0;
3962
3963 unlock_and_exit:
3964 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3965 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3966 return rc;
3967 }
3968
3969 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3970 {
3971 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld;
3972 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
3973 struct qed_mcp_link_speed_params *ext_speed;
3974 struct qed_mcp_link_capabilities *p_caps;
3975 struct qed_mcp_link_params *link;
3976 int i;
3977
3978 /* Read global nvm_cfg address */
3979 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3980
3981 /* Verify MCP has initialized it */
3982 if (!nvm_cfg_addr) {
3983 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
3984 return -EINVAL;
3985 }
3986
3987 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3988 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3989
3990 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3991 offsetof(struct nvm_cfg1, glob) +
3992 offsetof(struct nvm_cfg1_glob, core_cfg);
3993
3994 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
3995
3996 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3997 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3998 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3999 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4000 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4001 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4002 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4003 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4004 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4005 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4006 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4007 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4008 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4009 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1:
4010 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1:
4011 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2:
4012 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2:
4013 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4:
4014 break;
4015 default:
4016 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4017 break;
4018 }
4019
4020 /* Read default link configuration */
4021 link = &p_hwfn->mcp_info->link_input;
4022 p_caps = &p_hwfn->mcp_info->link_capabilities;
4023 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4024 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4025 link_temp = qed_rd(p_hwfn, p_ptt,
4026 port_cfg_addr +
4027 offsetof(struct nvm_cfg1_port, speed_cap_mask));
4028 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4029 link->speed.advertised_speeds = link_temp;
4030
4031 p_caps->speed_capabilities = link->speed.advertised_speeds;
4032
4033 link_temp = qed_rd(p_hwfn, p_ptt,
4034 port_cfg_addr +
4035 offsetof(struct nvm_cfg1_port, link_settings));
4036 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4037 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4038 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4039 link->speed.autoneg = true;
4040 break;
4041 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4042 link->speed.forced_speed = 1000;
4043 break;
4044 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4045 link->speed.forced_speed = 10000;
4046 break;
4047 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4048 link->speed.forced_speed = 20000;
4049 break;
4050 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4051 link->speed.forced_speed = 25000;
4052 break;
4053 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4054 link->speed.forced_speed = 40000;
4055 break;
4056 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4057 link->speed.forced_speed = 50000;
4058 break;
4059 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4060 link->speed.forced_speed = 100000;
4061 break;
4062 default:
4063 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4064 }
4065
4066 p_caps->default_speed_autoneg = link->speed.autoneg;
4067
4068 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL);
4069 link->pause.autoneg = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4070 link->pause.forced_rx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4071 link->pause.forced_tx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4072 link->loopback_mode = 0;
4073
4074 if (p_hwfn->mcp_info->capabilities &
4075 FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) {
4076 switch (GET_MFW_FIELD(link_temp,
4077 NVM_CFG1_PORT_FEC_FORCE_MODE)) {
4078 case NVM_CFG1_PORT_FEC_FORCE_MODE_NONE:
4079 p_caps->fec_default |= QED_FEC_MODE_NONE;
4080 break;
4081 case NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE:
4082 p_caps->fec_default |= QED_FEC_MODE_FIRECODE;
4083 break;
4084 case NVM_CFG1_PORT_FEC_FORCE_MODE_RS:
4085 p_caps->fec_default |= QED_FEC_MODE_RS;
4086 break;
4087 case NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO:
4088 p_caps->fec_default |= QED_FEC_MODE_AUTO;
4089 break;
4090 default:
4091 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4092 "unknown FEC mode in 0x%08x\n", link_temp);
4093 }
4094 } else {
4095 p_caps->fec_default = QED_FEC_MODE_UNSUPPORTED;
4096 }
4097
4098 link->fec = p_caps->fec_default;
4099
4100 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4101 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4102 offsetof(struct nvm_cfg1_port, ext_phy));
4103 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4104 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4105 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4106 link->eee.enable = true;
4107 switch (link_temp) {
4108 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4109 p_caps->default_eee = QED_MCP_EEE_DISABLED;
4110 link->eee.enable = false;
4111 break;
4112 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4113 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4114 break;
4115 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4116 p_caps->eee_lpi_timer =
4117 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4118 break;
4119 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4120 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4121 break;
4122 }
4123
4124 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4125 link->eee.tx_lpi_enable = link->eee.enable;
4126 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4127 } else {
4128 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4129 }
4130
4131 if (p_hwfn->mcp_info->capabilities &
4132 FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) {
4133 ext_speed = &link->ext_speed;
4134
4135 link_temp = qed_rd(p_hwfn, p_ptt,
4136 port_cfg_addr +
4137 offsetof(struct nvm_cfg1_port,
4138 extended_speed));
4139
4140 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_EXTENDED_SPEED);
4141 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN)
4142 ext_speed->autoneg = true;
4143
4144 ext_speed->forced_speed = 0;
4145 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G)
4146 ext_speed->forced_speed |= QED_EXT_SPEED_1G;
4147 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G)
4148 ext_speed->forced_speed |= QED_EXT_SPEED_10G;
4149 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G)
4150 ext_speed->forced_speed |= QED_EXT_SPEED_20G;
4151 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G)
4152 ext_speed->forced_speed |= QED_EXT_SPEED_25G;
4153 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G)
4154 ext_speed->forced_speed |= QED_EXT_SPEED_40G;
4155 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R)
4156 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R;
4157 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2)
4158 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R2;
4159 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2)
4160 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R2;
4161 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4)
4162 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R4;
4163 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4)
4164 ext_speed->forced_speed |= QED_EXT_SPEED_100G_P4;
4165
4166 fld = GET_MFW_FIELD(link_temp,
4167 NVM_CFG1_PORT_EXTENDED_SPEED_CAP);
4168
4169 ext_speed->advertised_speeds = 0;
4170 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED)
4171 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_RES;
4172 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G)
4173 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_1G;
4174 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G)
4175 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_10G;
4176 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G)
4177 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_20G;
4178 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G)
4179 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_25G;
4180 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G)
4181 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_40G;
4182 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R)
4183 ext_speed->advertised_speeds |=
4184 QED_EXT_SPEED_MASK_50G_R;
4185 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2)
4186 ext_speed->advertised_speeds |=
4187 QED_EXT_SPEED_MASK_50G_R2;
4188 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2)
4189 ext_speed->advertised_speeds |=
4190 QED_EXT_SPEED_MASK_100G_R2;
4191 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4)
4192 ext_speed->advertised_speeds |=
4193 QED_EXT_SPEED_MASK_100G_R4;
4194 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4)
4195 ext_speed->advertised_speeds |=
4196 QED_EXT_SPEED_MASK_100G_P4;
4197
4198 link_temp = qed_rd(p_hwfn, p_ptt,
4199 port_cfg_addr +
4200 offsetof(struct nvm_cfg1_port,
4201 extended_fec_mode));
4202 link->ext_fec_mode = link_temp;
4203
4204 p_caps->default_ext_speed_caps = ext_speed->advertised_speeds;
4205 p_caps->default_ext_speed = ext_speed->forced_speed;
4206 p_caps->default_ext_autoneg = ext_speed->autoneg;
4207 p_caps->default_ext_fec = link->ext_fec_mode;
4208
4209 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4210 "Read default extended link config: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, FEC: 0x%02x\n",
4211 ext_speed->forced_speed,
4212 ext_speed->advertised_speeds, ext_speed->autoneg,
4213 p_caps->default_ext_fec);
4214 }
4215
4216 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4217 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x, EEE: 0x%02x [0x%08x usec], FEC: 0x%02x\n",
4218 link->speed.forced_speed, link->speed.advertised_speeds,
4219 link->speed.autoneg, link->pause.autoneg,
4220 p_caps->default_eee, p_caps->eee_lpi_timer,
4221 p_caps->fec_default);
4222
4223 if (IS_LEAD_HWFN(p_hwfn)) {
4224 struct qed_dev *cdev = p_hwfn->cdev;
4225
4226 /* Read Multi-function information from shmem */
4227 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4228 offsetof(struct nvm_cfg1, glob) +
4229 offsetof(struct nvm_cfg1_glob, generic_cont0);
4230
4231 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4232
4233 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4234 NVM_CFG1_GLOB_MF_MODE_OFFSET;
4235
4236 switch (mf_mode) {
4237 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4238 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4239 break;
4240 case NVM_CFG1_GLOB_MF_MODE_UFP:
4241 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4242 BIT(QED_MF_LLH_PROTO_CLSS) |
4243 BIT(QED_MF_UFP_SPECIFIC) |
4244 BIT(QED_MF_8021Q_TAGGING) |
4245 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4246 break;
4247 case NVM_CFG1_GLOB_MF_MODE_BD:
4248 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4249 BIT(QED_MF_LLH_PROTO_CLSS) |
4250 BIT(QED_MF_8021AD_TAGGING) |
4251 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4252 break;
4253 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4254 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4255 BIT(QED_MF_LLH_PROTO_CLSS) |
4256 BIT(QED_MF_LL2_NON_UNICAST) |
4257 BIT(QED_MF_INTER_PF_SWITCH) |
4258 BIT(QED_MF_DISABLE_ARFS);
4259 break;
4260 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4261 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4262 BIT(QED_MF_LLH_PROTO_CLSS) |
4263 BIT(QED_MF_LL2_NON_UNICAST);
4264 if (QED_IS_BB(p_hwfn->cdev))
4265 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4266 break;
4267 }
4268
4269 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4270 cdev->mf_bits);
4271
4272 /* In CMT the PF is unknown when the GFS block processes the
4273 * packet. Therefore cannot use searcher as it has a per PF
4274 * database, and thus ARFS must be disabled.
4275 *
4276 */
4277 if (QED_IS_CMT(cdev))
4278 cdev->mf_bits |= BIT(QED_MF_DISABLE_ARFS);
4279 }
4280
4281 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4282 p_hwfn->cdev->mf_bits);
4283
4284 /* Read device capabilities information from shmem */
4285 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4286 offsetof(struct nvm_cfg1, glob) +
4287 offsetof(struct nvm_cfg1_glob, device_capabilities);
4288
4289 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4290 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4291 __set_bit(QED_DEV_CAP_ETH,
4292 &p_hwfn->hw_info.device_capabilities);
4293 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4294 __set_bit(QED_DEV_CAP_FCOE,
4295 &p_hwfn->hw_info.device_capabilities);
4296 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4297 __set_bit(QED_DEV_CAP_ISCSI,
4298 &p_hwfn->hw_info.device_capabilities);
4299 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4300 __set_bit(QED_DEV_CAP_ROCE,
4301 &p_hwfn->hw_info.device_capabilities);
4302
4303 /* Read device serial number information from shmem */
4304 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4305 offsetof(struct nvm_cfg1, glob) +
4306 offsetof(struct nvm_cfg1_glob, serial_number);
4307
4308 for (i = 0; i < 4; i++)
4309 p_hwfn->hw_info.part_num[i] = qed_rd(p_hwfn, p_ptt, addr + i * 4);
4310
4311 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4312 }
4313
4314 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4315 {
4316 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4317 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4318 struct qed_dev *cdev = p_hwfn->cdev;
4319
4320 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4321
4322 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4323 * in the other bits are selected.
4324 * Bits 1-15 are for functions 1-15, respectively, and their value is
4325 * '0' only for enabled functions (function 0 always exists and
4326 * enabled).
4327 * In case of CMT, only the "even" functions are enabled, and thus the
4328 * number of functions for both hwfns is learnt from the same bits.
4329 */
4330 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4331
4332 if (reg_function_hide & 0x1) {
4333 if (QED_IS_BB(cdev)) {
4334 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4335 num_funcs = 0;
4336 eng_mask = 0xaaaa;
4337 } else {
4338 num_funcs = 1;
4339 eng_mask = 0x5554;
4340 }
4341 } else {
4342 num_funcs = 1;
4343 eng_mask = 0xfffe;
4344 }
4345
4346 /* Get the number of the enabled functions on the engine */
4347 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4348 while (tmp) {
4349 if (tmp & 0x1)
4350 num_funcs++;
4351 tmp >>= 0x1;
4352 }
4353
4354 /* Get the PF index within the enabled functions */
4355 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4356 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4357 while (tmp) {
4358 if (tmp & 0x1)
4359 enabled_func_idx--;
4360 tmp >>= 0x1;
4361 }
4362 }
4363
4364 p_hwfn->num_funcs_on_engine = num_funcs;
4365 p_hwfn->enabled_func_idx = enabled_func_idx;
4366
4367 DP_VERBOSE(p_hwfn,
4368 NETIF_MSG_PROBE,
4369 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4370 p_hwfn->rel_pf_id,
4371 p_hwfn->abs_pf_id,
4372 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4373 }
4374
4375 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4376 {
4377 u32 addr, global_offsize, global_addr, port_mode;
4378 struct qed_dev *cdev = p_hwfn->cdev;
4379
4380 /* In CMT there is always only one port */
4381 if (cdev->num_hwfns > 1) {
4382 cdev->num_ports_in_engine = 1;
4383 cdev->num_ports = 1;
4384 return;
4385 }
4386
4387 /* Determine the number of ports per engine */
4388 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4389 switch (port_mode) {
4390 case 0x0:
4391 cdev->num_ports_in_engine = 1;
4392 break;
4393 case 0x1:
4394 cdev->num_ports_in_engine = 2;
4395 break;
4396 case 0x2:
4397 cdev->num_ports_in_engine = 4;
4398 break;
4399 default:
4400 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4401 cdev->num_ports_in_engine = 1; /* Default to something */
4402 break;
4403 }
4404
4405 /* Get the total number of ports of the device */
4406 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4407 PUBLIC_GLOBAL);
4408 global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4409 global_addr = SECTION_ADDR(global_offsize, 0);
4410 addr = global_addr + offsetof(struct public_global, max_ports);
4411 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4412 }
4413
4414 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4415 {
4416 struct qed_mcp_link_capabilities *p_caps;
4417 u32 eee_status;
4418
4419 p_caps = &p_hwfn->mcp_info->link_capabilities;
4420 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4421 return;
4422
4423 p_caps->eee_speed_caps = 0;
4424 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4425 offsetof(struct public_port, eee_status));
4426 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4427 EEE_SUPPORTED_SPEED_OFFSET;
4428
4429 if (eee_status & EEE_1G_SUPPORTED)
4430 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4431 if (eee_status & EEE_10G_ADV)
4432 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4433 }
4434
4435 static int
4436 qed_get_hw_info(struct qed_hwfn *p_hwfn,
4437 struct qed_ptt *p_ptt,
4438 enum qed_pci_personality personality)
4439 {
4440 int rc;
4441
4442 /* Since all information is common, only first hwfns should do this */
4443 if (IS_LEAD_HWFN(p_hwfn)) {
4444 rc = qed_iov_hw_info(p_hwfn);
4445 if (rc)
4446 return rc;
4447 }
4448
4449 if (IS_LEAD_HWFN(p_hwfn))
4450 qed_hw_info_port_num(p_hwfn, p_ptt);
4451
4452 qed_mcp_get_capabilities(p_hwfn, p_ptt);
4453
4454 qed_hw_get_nvm_info(p_hwfn, p_ptt);
4455
4456 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4457 if (rc)
4458 return rc;
4459
4460 if (qed_mcp_is_init(p_hwfn))
4461 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4462 p_hwfn->mcp_info->func_info.mac);
4463 else
4464 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4465
4466 if (qed_mcp_is_init(p_hwfn)) {
4467 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4468 p_hwfn->hw_info.ovlan =
4469 p_hwfn->mcp_info->func_info.ovlan;
4470
4471 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4472
4473 qed_get_eee_caps(p_hwfn, p_ptt);
4474
4475 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4476 }
4477
4478 if (qed_mcp_is_init(p_hwfn)) {
4479 enum qed_pci_personality protocol;
4480
4481 protocol = p_hwfn->mcp_info->func_info.protocol;
4482 p_hwfn->hw_info.personality = protocol;
4483 }
4484
4485 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4486 p_hwfn->hw_info.multi_tc_roce_en = true;
4487
4488 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4489 p_hwfn->hw_info.num_active_tc = 1;
4490
4491 qed_get_num_funcs(p_hwfn, p_ptt);
4492
4493 if (qed_mcp_is_init(p_hwfn))
4494 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4495
4496 return qed_hw_get_resc(p_hwfn, p_ptt);
4497 }
4498
4499 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4500 {
4501 struct qed_dev *cdev = p_hwfn->cdev;
4502 u16 device_id_mask;
4503 u32 tmp;
4504
4505 /* Read Vendor Id / Device Id */
4506 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4507 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4508
4509 /* Determine type */
4510 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4511 switch (device_id_mask) {
4512 case QED_DEV_ID_MASK_BB:
4513 cdev->type = QED_DEV_TYPE_BB;
4514 break;
4515 case QED_DEV_ID_MASK_AH:
4516 cdev->type = QED_DEV_TYPE_AH;
4517 break;
4518 default:
4519 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4520 return -EBUSY;
4521 }
4522
4523 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4524 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4525
4526 MASK_FIELD(CHIP_REV, cdev->chip_rev);
4527
4528 /* Learn number of HW-functions */
4529 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4530
4531 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4532 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4533 cdev->num_hwfns = 2;
4534 } else {
4535 cdev->num_hwfns = 1;
4536 }
4537
4538 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4539 MISCS_REG_CHIP_TEST_REG) >> 4;
4540 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4541 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4542 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4543
4544 DP_INFO(cdev->hwfns,
4545 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4546 QED_IS_BB(cdev) ? "BB" : "AH",
4547 'A' + cdev->chip_rev,
4548 (int)cdev->chip_metal,
4549 cdev->chip_num, cdev->chip_rev,
4550 cdev->chip_bond_id, cdev->chip_metal);
4551
4552 return 0;
4553 }
4554
4555 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4556 void __iomem *p_regview,
4557 void __iomem *p_doorbells,
4558 u64 db_phys_addr,
4559 enum qed_pci_personality personality)
4560 {
4561 struct qed_dev *cdev = p_hwfn->cdev;
4562 int rc = 0;
4563
4564 /* Split PCI bars evenly between hwfns */
4565 p_hwfn->regview = p_regview;
4566 p_hwfn->doorbells = p_doorbells;
4567 p_hwfn->db_phys_addr = db_phys_addr;
4568
4569 if (IS_VF(p_hwfn->cdev))
4570 return qed_vf_hw_prepare(p_hwfn);
4571
4572 /* Validate that chip access is feasible */
4573 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4574 DP_ERR(p_hwfn,
4575 "Reading the ME register returns all Fs; Preventing further chip access\n");
4576 return -EINVAL;
4577 }
4578
4579 get_function_id(p_hwfn);
4580
4581 /* Allocate PTT pool */
4582 rc = qed_ptt_pool_alloc(p_hwfn);
4583 if (rc)
4584 goto err0;
4585
4586 /* Allocate the main PTT */
4587 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4588
4589 /* First hwfn learns basic information, e.g., number of hwfns */
4590 if (!p_hwfn->my_id) {
4591 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4592 if (rc)
4593 goto err1;
4594 }
4595
4596 qed_hw_hwfn_prepare(p_hwfn);
4597
4598 /* Initialize MCP structure */
4599 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4600 if (rc) {
4601 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4602 goto err1;
4603 }
4604
4605 /* Read the device configuration information from the HW and SHMEM */
4606 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4607 if (rc) {
4608 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4609 goto err2;
4610 }
4611
4612 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4613 * is called as it sets the ports number in an engine.
4614 */
4615 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4616 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4617 if (rc)
4618 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4619 }
4620
4621 /* NVRAM info initialization and population */
4622 if (IS_LEAD_HWFN(p_hwfn)) {
4623 rc = qed_mcp_nvm_info_populate(p_hwfn);
4624 if (rc) {
4625 DP_NOTICE(p_hwfn,
4626 "Failed to populate nvm info shadow\n");
4627 goto err2;
4628 }
4629 }
4630
4631 /* Allocate the init RT array and initialize the init-ops engine */
4632 rc = qed_init_alloc(p_hwfn);
4633 if (rc)
4634 goto err3;
4635
4636 return rc;
4637 err3:
4638 if (IS_LEAD_HWFN(p_hwfn))
4639 qed_mcp_nvm_info_free(p_hwfn);
4640 err2:
4641 if (IS_LEAD_HWFN(p_hwfn))
4642 qed_iov_free_hw_info(p_hwfn->cdev);
4643 qed_mcp_free(p_hwfn);
4644 err1:
4645 qed_hw_hwfn_free(p_hwfn);
4646 err0:
4647 return rc;
4648 }
4649
4650 int qed_hw_prepare(struct qed_dev *cdev,
4651 int personality)
4652 {
4653 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4654 int rc;
4655
4656 /* Store the precompiled init data ptrs */
4657 if (IS_PF(cdev))
4658 qed_init_iro_array(cdev);
4659
4660 /* Initialize the first hwfn - will learn number of hwfns */
4661 rc = qed_hw_prepare_single(p_hwfn,
4662 cdev->regview,
4663 cdev->doorbells,
4664 cdev->db_phys_addr,
4665 personality);
4666 if (rc)
4667 return rc;
4668
4669 personality = p_hwfn->hw_info.personality;
4670
4671 /* Initialize the rest of the hwfns */
4672 if (cdev->num_hwfns > 1) {
4673 void __iomem *p_regview, *p_doorbell;
4674 u64 db_phys_addr;
4675 u32 offset;
4676
4677 /* adjust bar offset for second engine */
4678 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4679 BAR_ID_0) / 2;
4680 p_regview = cdev->regview + offset;
4681
4682 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4683 BAR_ID_1) / 2;
4684
4685 p_doorbell = cdev->doorbells + offset;
4686
4687 db_phys_addr = cdev->db_phys_addr + offset;
4688
4689 /* prepare second hw function */
4690 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4691 p_doorbell, db_phys_addr,
4692 personality);
4693
4694 /* in case of error, need to free the previously
4695 * initiliazed hwfn 0.
4696 */
4697 if (rc) {
4698 if (IS_PF(cdev)) {
4699 qed_init_free(p_hwfn);
4700 qed_mcp_nvm_info_free(p_hwfn);
4701 qed_mcp_free(p_hwfn);
4702 qed_hw_hwfn_free(p_hwfn);
4703 }
4704 }
4705 }
4706
4707 return rc;
4708 }
4709
4710 void qed_hw_remove(struct qed_dev *cdev)
4711 {
4712 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4713 int i;
4714
4715 if (IS_PF(cdev))
4716 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4717 QED_OV_DRIVER_STATE_NOT_LOADED);
4718
4719 for_each_hwfn(cdev, i) {
4720 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4721
4722 if (IS_VF(cdev)) {
4723 qed_vf_pf_release(p_hwfn);
4724 continue;
4725 }
4726
4727 qed_init_free(p_hwfn);
4728 qed_hw_hwfn_free(p_hwfn);
4729 qed_mcp_free(p_hwfn);
4730 }
4731
4732 qed_iov_free_hw_info(cdev);
4733
4734 qed_mcp_nvm_info_free(p_hwfn);
4735 }
4736
4737 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4738 {
4739 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4740 u16 min, max;
4741
4742 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4743 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4744 DP_NOTICE(p_hwfn,
4745 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4746 src_id, min, max);
4747
4748 return -EINVAL;
4749 }
4750
4751 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4752
4753 return 0;
4754 }
4755
4756 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4757 {
4758 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4759 u8 min, max;
4760
4761 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4762 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4763 DP_NOTICE(p_hwfn,
4764 "vport id [%d] is not valid, available indices [%d - %d]\n",
4765 src_id, min, max);
4766
4767 return -EINVAL;
4768 }
4769
4770 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4771
4772 return 0;
4773 }
4774
4775 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4776 {
4777 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4778 u8 min, max;
4779
4780 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4781 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4782 DP_NOTICE(p_hwfn,
4783 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4784 src_id, min, max);
4785
4786 return -EINVAL;
4787 }
4788
4789 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4790
4791 return 0;
4792 }
4793
4794 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4795 u32 hw_addr, void *p_eth_qzone,
4796 size_t eth_qzone_size, u8 timeset)
4797 {
4798 struct coalescing_timeset *p_coal_timeset;
4799
4800 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4801 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4802 return -EINVAL;
4803 }
4804
4805 p_coal_timeset = p_eth_qzone;
4806 memset(p_eth_qzone, 0, eth_qzone_size);
4807 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4808 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4809 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4810
4811 return 0;
4812 }
4813
4814 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
4815 {
4816 struct qed_queue_cid *p_cid = p_handle;
4817 struct qed_hwfn *p_hwfn;
4818 struct qed_ptt *p_ptt;
4819 int rc = 0;
4820
4821 p_hwfn = p_cid->p_owner;
4822
4823 if (IS_VF(p_hwfn->cdev))
4824 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
4825
4826 p_ptt = qed_ptt_acquire(p_hwfn);
4827 if (!p_ptt)
4828 return -EAGAIN;
4829
4830 if (rx_coal) {
4831 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4832 if (rc)
4833 goto out;
4834 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
4835 }
4836
4837 if (tx_coal) {
4838 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4839 if (rc)
4840 goto out;
4841 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
4842 }
4843 out:
4844 qed_ptt_release(p_hwfn, p_ptt);
4845 return rc;
4846 }
4847
4848 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
4849 struct qed_ptt *p_ptt,
4850 u16 coalesce, struct qed_queue_cid *p_cid)
4851 {
4852 struct ustorm_eth_queue_zone eth_qzone;
4853 u8 timeset, timer_res;
4854 u32 address;
4855 int rc;
4856
4857 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4858 if (coalesce <= 0x7F) {
4859 timer_res = 0;
4860 } else if (coalesce <= 0xFF) {
4861 timer_res = 1;
4862 } else if (coalesce <= 0x1FF) {
4863 timer_res = 2;
4864 } else {
4865 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4866 return -EINVAL;
4867 }
4868 timeset = (u8)(coalesce >> timer_res);
4869
4870 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4871 p_cid->sb_igu_id, false);
4872 if (rc)
4873 goto out;
4874
4875 address = BAR0_MAP_REG_USDM_RAM +
4876 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4877
4878 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4879 sizeof(struct ustorm_eth_queue_zone), timeset);
4880 if (rc)
4881 goto out;
4882
4883 out:
4884 return rc;
4885 }
4886
4887 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
4888 struct qed_ptt *p_ptt,
4889 u16 coalesce, struct qed_queue_cid *p_cid)
4890 {
4891 struct xstorm_eth_queue_zone eth_qzone;
4892 u8 timeset, timer_res;
4893 u32 address;
4894 int rc;
4895
4896 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4897 if (coalesce <= 0x7F) {
4898 timer_res = 0;
4899 } else if (coalesce <= 0xFF) {
4900 timer_res = 1;
4901 } else if (coalesce <= 0x1FF) {
4902 timer_res = 2;
4903 } else {
4904 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4905 return -EINVAL;
4906 }
4907 timeset = (u8)(coalesce >> timer_res);
4908
4909 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4910 p_cid->sb_igu_id, true);
4911 if (rc)
4912 goto out;
4913
4914 address = BAR0_MAP_REG_XSDM_RAM +
4915 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4916
4917 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4918 sizeof(struct xstorm_eth_queue_zone), timeset);
4919 out:
4920 return rc;
4921 }
4922
4923 /* Calculate final WFQ values for all vports and configure them.
4924 * After this configuration each vport will have
4925 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4926 */
4927 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4928 struct qed_ptt *p_ptt,
4929 u32 min_pf_rate)
4930 {
4931 struct init_qm_vport_params *vport_params;
4932 int i;
4933
4934 vport_params = p_hwfn->qm_info.qm_vport_params;
4935
4936 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4937 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4938
4939 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) /
4940 min_pf_rate;
4941 qed_init_vport_wfq(p_hwfn, p_ptt,
4942 vport_params[i].first_tx_pq_id,
4943 vport_params[i].wfq);
4944 }
4945 }
4946
4947 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4948 u32 min_pf_rate)
4949
4950 {
4951 int i;
4952
4953 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4954 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
4955 }
4956
4957 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4958 struct qed_ptt *p_ptt,
4959 u32 min_pf_rate)
4960 {
4961 struct init_qm_vport_params *vport_params;
4962 int i;
4963
4964 vport_params = p_hwfn->qm_info.qm_vport_params;
4965
4966 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4967 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4968 qed_init_vport_wfq(p_hwfn, p_ptt,
4969 vport_params[i].first_tx_pq_id,
4970 vport_params[i].wfq);
4971 }
4972 }
4973
4974 /* This function performs several validations for WFQ
4975 * configuration and required min rate for a given vport
4976 * 1. req_rate must be greater than one percent of min_pf_rate.
4977 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4978 * rates to get less than one percent of min_pf_rate.
4979 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4980 */
4981 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4982 u16 vport_id, u32 req_rate, u32 min_pf_rate)
4983 {
4984 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4985 int non_requested_count = 0, req_count = 0, i, num_vports;
4986
4987 num_vports = p_hwfn->qm_info.num_vports;
4988
4989 /* Accounting for the vports which are configured for WFQ explicitly */
4990 for (i = 0; i < num_vports; i++) {
4991 u32 tmp_speed;
4992
4993 if ((i != vport_id) &&
4994 p_hwfn->qm_info.wfq_data[i].configured) {
4995 req_count++;
4996 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4997 total_req_min_rate += tmp_speed;
4998 }
4999 }
5000
5001 /* Include current vport data as well */
5002 req_count++;
5003 total_req_min_rate += req_rate;
5004 non_requested_count = num_vports - req_count;
5005
5006 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5007 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5008 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5009 vport_id, req_rate, min_pf_rate);
5010 return -EINVAL;
5011 }
5012
5013 if (num_vports > QED_WFQ_UNIT) {
5014 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5015 "Number of vports is greater than %d\n",
5016 QED_WFQ_UNIT);
5017 return -EINVAL;
5018 }
5019
5020 if (total_req_min_rate > min_pf_rate) {
5021 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5022 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5023 total_req_min_rate, min_pf_rate);
5024 return -EINVAL;
5025 }
5026
5027 total_left_rate = min_pf_rate - total_req_min_rate;
5028
5029 left_rate_per_vp = total_left_rate / non_requested_count;
5030 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
5031 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5032 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5033 left_rate_per_vp, min_pf_rate);
5034 return -EINVAL;
5035 }
5036
5037 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5038 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5039
5040 for (i = 0; i < num_vports; i++) {
5041 if (p_hwfn->qm_info.wfq_data[i].configured)
5042 continue;
5043
5044 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5045 }
5046
5047 return 0;
5048 }
5049
5050 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5051 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5052 {
5053 struct qed_mcp_link_state *p_link;
5054 int rc = 0;
5055
5056 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5057
5058 if (!p_link->min_pf_rate) {
5059 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5060 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5061 return rc;
5062 }
5063
5064 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5065
5066 if (!rc)
5067 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5068 p_link->min_pf_rate);
5069 else
5070 DP_NOTICE(p_hwfn,
5071 "Validation failed while configuring min rate\n");
5072
5073 return rc;
5074 }
5075
5076 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5077 struct qed_ptt *p_ptt,
5078 u32 min_pf_rate)
5079 {
5080 bool use_wfq = false;
5081 int rc = 0;
5082 u16 i;
5083
5084 /* Validate all pre configured vports for wfq */
5085 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5086 u32 rate;
5087
5088 if (!p_hwfn->qm_info.wfq_data[i].configured)
5089 continue;
5090
5091 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5092 use_wfq = true;
5093
5094 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5095 if (rc) {
5096 DP_NOTICE(p_hwfn,
5097 "WFQ validation failed while configuring min rate\n");
5098 break;
5099 }
5100 }
5101
5102 if (!rc && use_wfq)
5103 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5104 else
5105 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5106
5107 return rc;
5108 }
5109
5110 /* Main API for qed clients to configure vport min rate.
5111 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5112 * rate - Speed in Mbps needs to be assigned to a given vport.
5113 */
5114 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5115 {
5116 int i, rc = -EINVAL;
5117
5118 /* Currently not supported; Might change in future */
5119 if (cdev->num_hwfns > 1) {
5120 DP_NOTICE(cdev,
5121 "WFQ configuration is not supported for this device\n");
5122 return rc;
5123 }
5124
5125 for_each_hwfn(cdev, i) {
5126 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5127 struct qed_ptt *p_ptt;
5128
5129 p_ptt = qed_ptt_acquire(p_hwfn);
5130 if (!p_ptt)
5131 return -EBUSY;
5132
5133 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5134
5135 if (rc) {
5136 qed_ptt_release(p_hwfn, p_ptt);
5137 return rc;
5138 }
5139
5140 qed_ptt_release(p_hwfn, p_ptt);
5141 }
5142
5143 return rc;
5144 }
5145
5146 /* API to configure WFQ from mcp link change */
5147 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5148 struct qed_ptt *p_ptt, u32 min_pf_rate)
5149 {
5150 int i;
5151
5152 if (cdev->num_hwfns > 1) {
5153 DP_VERBOSE(cdev,
5154 NETIF_MSG_LINK,
5155 "WFQ configuration is not supported for this device\n");
5156 return;
5157 }
5158
5159 for_each_hwfn(cdev, i) {
5160 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5161
5162 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5163 min_pf_rate);
5164 }
5165 }
5166
5167 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5168 struct qed_ptt *p_ptt,
5169 struct qed_mcp_link_state *p_link,
5170 u8 max_bw)
5171 {
5172 int rc = 0;
5173
5174 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5175
5176 if (!p_link->line_speed && (max_bw != 100))
5177 return rc;
5178
5179 p_link->speed = (p_link->line_speed * max_bw) / 100;
5180 p_hwfn->qm_info.pf_rl = p_link->speed;
5181
5182 /* Since the limiter also affects Tx-switched traffic, we don't want it
5183 * to limit such traffic in case there's no actual limit.
5184 * In that case, set limit to imaginary high boundary.
5185 */
5186 if (max_bw == 100)
5187 p_hwfn->qm_info.pf_rl = 100000;
5188
5189 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5190 p_hwfn->qm_info.pf_rl);
5191
5192 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5193 "Configured MAX bandwidth to be %08x Mb/sec\n",
5194 p_link->speed);
5195
5196 return rc;
5197 }
5198
5199 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5200 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5201 {
5202 int i, rc = -EINVAL;
5203
5204 if (max_bw < 1 || max_bw > 100) {
5205 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5206 return rc;
5207 }
5208
5209 for_each_hwfn(cdev, i) {
5210 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5211 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5212 struct qed_mcp_link_state *p_link;
5213 struct qed_ptt *p_ptt;
5214
5215 p_link = &p_lead->mcp_info->link_output;
5216
5217 p_ptt = qed_ptt_acquire(p_hwfn);
5218 if (!p_ptt)
5219 return -EBUSY;
5220
5221 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5222 p_link, max_bw);
5223
5224 qed_ptt_release(p_hwfn, p_ptt);
5225
5226 if (rc)
5227 break;
5228 }
5229
5230 return rc;
5231 }
5232
5233 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5234 struct qed_ptt *p_ptt,
5235 struct qed_mcp_link_state *p_link,
5236 u8 min_bw)
5237 {
5238 int rc = 0;
5239
5240 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5241 p_hwfn->qm_info.pf_wfq = min_bw;
5242
5243 if (!p_link->line_speed)
5244 return rc;
5245
5246 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5247
5248 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5249
5250 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5251 "Configured MIN bandwidth to be %d Mb/sec\n",
5252 p_link->min_pf_rate);
5253
5254 return rc;
5255 }
5256
5257 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5258 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5259 {
5260 int i, rc = -EINVAL;
5261
5262 if (min_bw < 1 || min_bw > 100) {
5263 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5264 return rc;
5265 }
5266
5267 for_each_hwfn(cdev, i) {
5268 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5269 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5270 struct qed_mcp_link_state *p_link;
5271 struct qed_ptt *p_ptt;
5272
5273 p_link = &p_lead->mcp_info->link_output;
5274
5275 p_ptt = qed_ptt_acquire(p_hwfn);
5276 if (!p_ptt)
5277 return -EBUSY;
5278
5279 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5280 p_link, min_bw);
5281 if (rc) {
5282 qed_ptt_release(p_hwfn, p_ptt);
5283 return rc;
5284 }
5285
5286 if (p_link->min_pf_rate) {
5287 u32 min_rate = p_link->min_pf_rate;
5288
5289 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5290 p_ptt,
5291 min_rate);
5292 }
5293
5294 qed_ptt_release(p_hwfn, p_ptt);
5295 }
5296
5297 return rc;
5298 }
5299
5300 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5301 {
5302 struct qed_mcp_link_state *p_link;
5303
5304 p_link = &p_hwfn->mcp_info->link_output;
5305
5306 if (p_link->min_pf_rate)
5307 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5308 p_link->min_pf_rate);
5309
5310 memset(p_hwfn->qm_info.wfq_data, 0,
5311 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5312 }
5313
5314 int qed_device_num_ports(struct qed_dev *cdev)
5315 {
5316 return cdev->num_ports;
5317 }
5318
5319 void qed_set_fw_mac_addr(__le16 *fw_msb,
5320 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5321 {
5322 ((u8 *)fw_msb)[0] = mac[1];
5323 ((u8 *)fw_msb)[1] = mac[0];
5324 ((u8 *)fw_mid)[0] = mac[3];
5325 ((u8 *)fw_mid)[1] = mac[2];
5326 ((u8 *)fw_lsb)[0] = mac[5];
5327 ((u8 *)fw_lsb)[1] = mac[4];
5328 }
Linux with added FPC-III support