drivers/net/ethernet/qlogic/qed/qed_int.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2 /* QLogic qed NIC Driver
   3  * Copyright (c) 2015-2017  QLogic Corporation
   4  * Copyright (c) 2019-2020 Marvell International Ltd.
   5  */
   6
   7 #ifndef _QED_INT_H
   8 #define _QED_INT_H
   9
  10 #include <linux/types.h>
  11 #include <linux/slab.h>
  12 #include "qed.h"
  13
  14 /* Fields of IGU PF CONFIGURATION REGISTER */
  15 #define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
  16 #define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
  17 #define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
  18 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
  19 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
  20 #define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
  21 /* Fields of IGU VF CONFIGURATION REGISTER */
  22 #define IGU_VF_CONF_FUNC_EN        (0x1 << 0)   /* function enable        */
  23 #define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)   /* MSI/MSIX enable        */
  24 #define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)   /* single ISR mode enable */
  25 #define IGU_VF_CONF_PARENT_MASK    (0xF)        /* Parent PF              */
  26 #define IGU_VF_CONF_PARENT_SHIFT   5            /* Parent PF              */
  27
  28 /* Igu control commands
  29  */
  30 enum igu_ctrl_cmd {
  31         IGU_CTRL_CMD_TYPE_RD,
  32         IGU_CTRL_CMD_TYPE_WR,
  33         MAX_IGU_CTRL_CMD
  34 };
  35
  36 /* Control register for the IGU command register
  37  */
  38 struct igu_ctrl_reg {
  39         u32 ctrl_data;
  40 #define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID    */
  41 #define IGU_CTRL_REG_FID_SHIFT          0
  42 #define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
  43 #define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
  44 #define IGU_CTRL_REG_RESERVED_MASK      0x1
  45 #define IGU_CTRL_REG_RESERVED_SHIFT     28
  46 #define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
  47 #define IGU_CTRL_REG_TYPE_SHIFT         31
  48 };
  49
  50 enum qed_coalescing_fsm {
  51         QED_COAL_RX_STATE_MACHINE,
  52         QED_COAL_TX_STATE_MACHINE
  53 };
  54
  55 /**
  56  * @brief qed_int_igu_enable_int - enable device interrupts
  57  *
  58  * @param p_hwfn
  59  * @param p_ptt
  60  * @param int_mode - interrupt mode to use
  61  */
  62 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
  63                             struct qed_ptt *p_ptt,
  64                             enum qed_int_mode int_mode);
  65
  66 /**
  67  * @brief qed_int_igu_disable_int - disable device interrupts
  68  *
  69  * @param p_hwfn
  70  * @param p_ptt
  71  */
  72 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
  73                              struct qed_ptt *p_ptt);
  74
  75 /**
  76  * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
  77  *        register from igu.
  78  *
  79  * @param p_hwfn
  80  *
  81  * @return u64
  82  */
  83 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
  84
  85 #define QED_SP_SB_ID 0xffff
  86 /**
  87  * @brief qed_int_sb_init - Initializes the sb_info structure.
  88  *
  89  * once the structure is initialized it can be passed to sb related functions.
  90  *
  91  * @param p_hwfn
  92  * @param p_ptt
  93  * @param sb_info       points to an uninitialized (but
  94  *                      allocated) sb_info structure
  95  * @param sb_virt_addr
  96  * @param sb_phy_addr
  97  * @param sb_id the sb_id to be used (zero based in driver)
  98  *                      should use QED_SP_SB_ID for SP Status block
  99  *
 100  * @return int
 101  */
 102 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
 103                     struct qed_ptt *p_ptt,
 104                     struct qed_sb_info *sb_info,
 105                     void *sb_virt_addr,
 106                     dma_addr_t sb_phy_addr,
 107                     u16 sb_id);
 108 /**
 109  * @brief qed_int_sb_setup - Setup the sb.
 110  *
 111  * @param p_hwfn
 112  * @param p_ptt
 113  * @param sb_info       initialized sb_info structure
 114  */
 115 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
 116                       struct qed_ptt *p_ptt,
 117                       struct qed_sb_info *sb_info);
 118
 119 /**
 120  * @brief qed_int_sb_release - releases the sb_info structure.
 121  *
 122  * once the structure is released, it's memory can be freed
 123  *
 124  * @param p_hwfn
 125  * @param sb_info       points to an allocated sb_info structure
 126  * @param sb_id         the sb_id to be used (zero based in driver)
 127  *                      should never be equal to QED_SP_SB_ID
 128  *                      (SP Status block)
 129  *
 130  * @return int
 131  */
 132 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
 133                        struct qed_sb_info *sb_info,
 134                        u16 sb_id);
 135
 136 /**
 137  * @brief qed_int_sp_dpc - To be called when an interrupt is received on the
 138  *        default status block.
 139  *
 140  * @param p_hwfn - pointer to hwfn
 141  *
 142  */
 143 void qed_int_sp_dpc(struct tasklet_struct *t);
 144
 145 /**
 146  * @brief qed_int_get_num_sbs - get the number of status
 147  *        blocks configured for this funciton in the igu.
 148  *
 149  * @param p_hwfn
 150  * @param p_sb_cnt_info
 151  *
 152  * @return int - number of status blocks configured
 153  */
 154 void qed_int_get_num_sbs(struct qed_hwfn        *p_hwfn,
 155                          struct qed_sb_cnt_info *p_sb_cnt_info);
 156
 157 /**
 158  * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
 159  *        release. The API need to be called after releasing all slowpath IRQs
 160  *        of the device.
 161  *
 162  * @param cdev
 163  *
 164  */
 165 void qed_int_disable_post_isr_release(struct qed_dev *cdev);
 166
 167 /**
 168  * @brief qed_int_attn_clr_enable - sets whether the general behavior is
 169  *        preventing attentions from being reasserted, or following the
 170  *        attributes of the specific attention.
 171  *
 172  * @param cdev
 173  * @param clr_enable
 174  *
 175  */
 176 void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable);
 177
 178 /**
 179  * @brief - Doorbell Recovery handler.
 180  *          Run doorbell recovery in case of PF overflow (and flush DORQ if
 181  *          needed).
 182  *
 183  * @param p_hwfn
 184  * @param p_ptt
 185  */
 186 int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 187
 188 #define QED_CAU_DEF_RX_TIMER_RES 0
 189 #define QED_CAU_DEF_TX_TIMER_RES 0
 190
 191 #define QED_SB_ATT_IDX  0x0001
 192 #define QED_SB_EVENT_MASK       0x0003
 193
 194 #define SB_ALIGNED_SIZE(p_hwfn) \
 195         ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
 196
 197 #define QED_SB_INVALID_IDX      0xffff
 198
 199 struct qed_igu_block {
 200         u8 status;
 201 #define QED_IGU_STATUS_FREE     0x01
 202 #define QED_IGU_STATUS_VALID    0x02
 203 #define QED_IGU_STATUS_PF       0x04
 204 #define QED_IGU_STATUS_DSB      0x08
 205
 206         u8 vector_number;
 207         u8 function_id;
 208         u8 is_pf;
 209
 210         /* Index inside IGU [meant for back reference] */
 211         u16 igu_sb_id;
 212
 213         struct qed_sb_info *sb_info;
 214 };
 215
 216 struct qed_igu_info {
 217         struct qed_igu_block entry[MAX_TOT_SB_PER_PATH];
 218         u16 igu_dsb_id;
 219
 220         struct qed_sb_cnt_info usage;
 221
 222         bool b_allow_pf_vf_change;
 223 };
 224
 225 /**
 226  * @brief - Make sure the IGU CAM reflects the resources provided by MFW
 227  *
 228  * @param p_hwfn
 229  * @param p_ptt
 230  */
 231 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 232
 233 /**
 234  * @brief Translate the weakly-defined client sb-id into an IGU sb-id
 235  *
 236  * @param p_hwfn
 237  * @param sb_id - user provided sb_id
 238  *
 239  * @return an index inside IGU CAM where the SB resides
 240  */
 241 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
 242
 243 /**
 244  * @brief return a pointer to an unused valid SB
 245  *
 246  * @param p_hwfn
 247  * @param b_is_pf - true iff we want a SB belonging to a PF
 248  *
 249  * @return point to an igu_block, NULL if none is available
 250  */
 251 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn,
 252                                           bool b_is_pf);
 253
 254 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
 255                               struct qed_ptt *p_ptt,
 256                               bool b_set,
 257                               bool b_slowpath);
 258
 259 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
 260
 261 /**
 262  * @brief qed_int_igu_read_cam - Reads the IGU CAM.
 263  *      This function needs to be called during hardware
 264  *      prepare. It reads the info from igu cam to know which
 265  *      status block is the default / base status block etc.
 266  *
 267  * @param p_hwfn
 268  * @param p_ptt
 269  *
 270  * @return int
 271  */
 272 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
 273                          struct qed_ptt *p_ptt);
 274
 275 typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
 276                                  void *cookie);
 277 /**
 278  * @brief qed_int_register_cb - Register callback func for
 279  *      slowhwfn statusblock.
 280  *
 281  *      Every protocol that uses the slowhwfn status block
 282  *      should register a callback function that will be called
 283  *      once there is an update of the sp status block.
 284  *
 285  * @param p_hwfn
 286  * @param comp_cb - function to be called when there is an
 287  *                  interrupt on the sp sb
 288  *
 289  * @param cookie  - passed to the callback function
 290  * @param sb_idx  - OUT parameter which gives the chosen index
 291  *                  for this protocol.
 292  * @param p_fw_cons  - pointer to the actual address of the
 293  *                     consumer for this protocol.
 294  *
 295  * @return int
 296  */
 297 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
 298                         qed_int_comp_cb_t comp_cb,
 299                         void *cookie,
 300                         u8 *sb_idx,
 301                         __le16 **p_fw_cons);
 302
 303 /**
 304  * @brief qed_int_unregister_cb - Unregisters callback
 305  *      function from sp sb.
 306  *      Partner of qed_int_register_cb -> should be called
 307  *      when no longer required.
 308  *
 309  * @param p_hwfn
 310  * @param pi
 311  *
 312  * @return int
 313  */
 314 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
 315                           u8 pi);
 316
 317 /**
 318  * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
 319  *
 320  * @param p_hwfn
 321  *
 322  * @return u16
 323  */
 324 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
 325
 326 /**
 327  * @brief Status block cleanup. Should be called for each status
 328  *        block that will be used -> both PF / VF
 329  *
 330  * @param p_hwfn
 331  * @param p_ptt
 332  * @param igu_sb_id     - igu status block id
 333  * @param opaque        - opaque fid of the sb owner.
 334  * @param b_set         - set(1) / clear(0)
 335  */
 336 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
 337                                      struct qed_ptt *p_ptt,
 338                                      u16 igu_sb_id,
 339                                      u16 opaque,
 340                                      bool b_set);
 341
 342 /**
 343  * @brief qed_int_cau_conf - configure cau for a given status
 344  *        block
 345  *
 346  * @param p_hwfn
 347  * @param ptt
 348  * @param sb_phys
 349  * @param igu_sb_id
 350  * @param vf_number
 351  * @param vf_valid
 352  */
 353 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
 354                          struct qed_ptt *p_ptt,
 355                          dma_addr_t sb_phys,
 356                          u16 igu_sb_id,
 357                          u16 vf_number,
 358                          u8 vf_valid);
 359
 360 /**
 361  * @brief qed_int_alloc
 362  *
 363  * @param p_hwfn
 364  * @param p_ptt
 365  *
 366  * @return int
 367  */
 368 int qed_int_alloc(struct qed_hwfn *p_hwfn,
 369                   struct qed_ptt *p_ptt);
 370
 371 /**
 372  * @brief qed_int_free
 373  *
 374  * @param p_hwfn
 375  */
 376 void qed_int_free(struct qed_hwfn *p_hwfn);
 377
 378 /**
 379  * @brief qed_int_setup
 380  *
 381  * @param p_hwfn
 382  * @param p_ptt
 383  */
 384 void qed_int_setup(struct qed_hwfn *p_hwfn,
 385                    struct qed_ptt *p_ptt);
 386
 387 /**
 388  * @brief - Enable Interrupt & Attention for hw function
 389  *
 390  * @param p_hwfn
 391  * @param p_ptt
 392  * @param int_mode
 393  *
 394  * @return int
 395  */
 396 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 397                        enum qed_int_mode int_mode);
 398
 399 /**
 400  * @brief - Initialize CAU status block entry
 401  *
 402  * @param p_hwfn
 403  * @param p_sb_entry
 404  * @param pf_id
 405  * @param vf_number
 406  * @param vf_valid
 407  */
 408 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
 409                            struct cau_sb_entry *p_sb_entry,
 410                            u8 pf_id,
 411                            u16 vf_number,
 412                            u8 vf_valid);
 413
 414 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 415                           u8 timer_res, u16 sb_id, bool tx);
 416
 417 #define QED_MAPPING_MEMORY_SIZE(dev)    (NUM_OF_SBS(dev))
 418
 419 int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 420                                 bool hw_init);
 421
 422 #endif