drivers/net/ethernet/sfc/nic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2013 Solarflare Communications Inc.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/pci.h>
  12 #include <linux/module.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/cpu_rmap.h>
  15 #include "net_driver.h"
  16 #include "bitfield.h"
  17 #include "efx.h"
  18 #include "nic.h"
  19 #include "ef10_regs.h"
  20 #include "farch_regs.h"
  21 #include "io.h"
  22 #include "workarounds.h"
  23 #include "mcdi_pcol.h"
  24
  25 /**************************************************************************
  26  *
  27  * Generic buffer handling
  28  * These buffers are used for interrupt status, MAC stats, etc.
  29  *
  30  **************************************************************************/
  31
  32 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
  33                          unsigned int len, gfp_t gfp_flags)
  34 {
  35         buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
  36                                           &buffer->dma_addr, gfp_flags);
  37         if (!buffer->addr)
  38                 return -ENOMEM;
  39         buffer->len = len;
  40         return 0;
  41 }
  42
  43 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
  44 {
  45         if (buffer->addr) {
  46                 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
  47                                   buffer->addr, buffer->dma_addr);
  48                 buffer->addr = NULL;
  49         }
  50 }
  51
  52 /* Check whether an event is present in the eventq at the current
  53  * read pointer.  Only useful for self-test.
  54  */
  55 bool efx_nic_event_present(struct efx_channel *channel)
  56 {
  57         return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
  58 }
  59
  60 void efx_nic_event_test_start(struct efx_channel *channel)
  61 {
  62         channel->event_test_cpu = -1;
  63         smp_wmb();
  64         channel->efx->type->ev_test_generate(channel);
  65 }
  66
  67 int efx_nic_irq_test_start(struct efx_nic *efx)
  68 {
  69         efx->last_irq_cpu = -1;
  70         smp_wmb();
  71         return efx->type->irq_test_generate(efx);
  72 }
  73
  74 /* Hook interrupt handler(s)
  75  * Try MSI and then legacy interrupts.
  76  */
  77 int efx_nic_init_interrupt(struct efx_nic *efx)
  78 {
  79         struct efx_channel *channel;
  80         unsigned int n_irqs;
  81         int rc;
  82
  83         if (!EFX_INT_MODE_USE_MSI(efx)) {
  84                 rc = request_irq(efx->legacy_irq,
  85                                  efx->type->irq_handle_legacy, IRQF_SHARED,
  86                                  efx->name, efx);
  87                 if (rc) {
  88                         netif_err(efx, drv, efx->net_dev,
  89                                   "failed to hook legacy IRQ %d\n",
  90                                   efx->pci_dev->irq);
  91                         goto fail1;
  92                 }
  93                 return 0;
  94         }
  95
  96 #ifdef CONFIG_RFS_ACCEL
  97         if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
  98                 efx->net_dev->rx_cpu_rmap =
  99                         alloc_irq_cpu_rmap(efx->n_rx_channels);
 100                 if (!efx->net_dev->rx_cpu_rmap) {
 101                         rc = -ENOMEM;
 102                         goto fail1;
 103                 }
 104         }
 105 #endif
 106
 107         /* Hook MSI or MSI-X interrupt */
 108         n_irqs = 0;
 109         efx_for_each_channel(channel, efx) {
 110                 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
 111                                  IRQF_PROBE_SHARED, /* Not shared */
 112                                  efx->msi_context[channel->channel].name,
 113                                  &efx->msi_context[channel->channel]);
 114                 if (rc) {
 115                         netif_err(efx, drv, efx->net_dev,
 116                                   "failed to hook IRQ %d\n", channel->irq);
 117                         goto fail2;
 118                 }
 119                 ++n_irqs;
 120
 121 #ifdef CONFIG_RFS_ACCEL
 122                 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
 123                     channel->channel < efx->n_rx_channels) {
 124                         rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
 125                                               channel->irq);
 126                         if (rc)
 127                                 goto fail2;
 128                 }
 129 #endif
 130         }
 131
 132         efx->irqs_hooked = true;
 133         return 0;
 134
 135  fail2:
 136 #ifdef CONFIG_RFS_ACCEL
 137         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 138         efx->net_dev->rx_cpu_rmap = NULL;
 139 #endif
 140         efx_for_each_channel(channel, efx) {
 141                 if (n_irqs-- == 0)
 142                         break;
 143                 free_irq(channel->irq, &efx->msi_context[channel->channel]);
 144         }
 145  fail1:
 146         return rc;
 147 }
 148
 149 void efx_nic_fini_interrupt(struct efx_nic *efx)
 150 {
 151         struct efx_channel *channel;
 152
 153 #ifdef CONFIG_RFS_ACCEL
 154         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 155         efx->net_dev->rx_cpu_rmap = NULL;
 156 #endif
 157
 158         if (!efx->irqs_hooked)
 159                 return;
 160         if (EFX_INT_MODE_USE_MSI(efx)) {
 161                 /* Disable MSI/MSI-X interrupts */
 162                 efx_for_each_channel(channel, efx)
 163                         free_irq(channel->irq,
 164                                  &efx->msi_context[channel->channel]);
 165         } else {
 166                 /* Disable legacy interrupt */
 167                 free_irq(efx->legacy_irq, efx);
 168         }
 169         efx->irqs_hooked = false;
 170 }
 171
 172 /* Register dump */
 173
 174 #define REGISTER_REVISION_FA    1
 175 #define REGISTER_REVISION_FB    2
 176 #define REGISTER_REVISION_FC    3
 177 #define REGISTER_REVISION_FZ    3       /* last Falcon arch revision */
 178 #define REGISTER_REVISION_ED    4
 179 #define REGISTER_REVISION_EZ    4       /* latest EF10 revision */
 180
 181 struct efx_nic_reg {
 182         u32 offset:24;
 183         u32 min_revision:3, max_revision:3;
 184 };
 185
 186 #define REGISTER(name, arch, min_rev, max_rev) {                        \
 187         arch ## R_ ## min_rev ## max_rev ## _ ## name,                  \
 188         REGISTER_REVISION_ ## arch ## min_rev,                          \
 189         REGISTER_REVISION_ ## arch ## max_rev                           \
 190 }
 191 #define REGISTER_AA(name) REGISTER(name, F, A, A)
 192 #define REGISTER_AB(name) REGISTER(name, F, A, B)
 193 #define REGISTER_AZ(name) REGISTER(name, F, A, Z)
 194 #define REGISTER_BB(name) REGISTER(name, F, B, B)
 195 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
 196 #define REGISTER_CZ(name) REGISTER(name, F, C, Z)
 197 #define REGISTER_DZ(name) REGISTER(name, E, D, Z)
 198
 199 static const struct efx_nic_reg efx_nic_regs[] = {
 200         REGISTER_AZ(ADR_REGION),
 201         REGISTER_AZ(INT_EN_KER),
 202         REGISTER_BZ(INT_EN_CHAR),
 203         REGISTER_AZ(INT_ADR_KER),
 204         REGISTER_BZ(INT_ADR_CHAR),
 205         /* INT_ACK_KER is WO */
 206         /* INT_ISR0 is RC */
 207         REGISTER_AZ(HW_INIT),
 208         REGISTER_CZ(USR_EV_CFG),
 209         REGISTER_AB(EE_SPI_HCMD),
 210         REGISTER_AB(EE_SPI_HADR),
 211         REGISTER_AB(EE_SPI_HDATA),
 212         REGISTER_AB(EE_BASE_PAGE),
 213         REGISTER_AB(EE_VPD_CFG0),
 214         /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
 215         /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
 216         /* PCIE_CORE_INDIRECT is indirect */
 217         REGISTER_AB(NIC_STAT),
 218         REGISTER_AB(GPIO_CTL),
 219         REGISTER_AB(GLB_CTL),
 220         /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
 221         REGISTER_BZ(DP_CTRL),
 222         REGISTER_AZ(MEM_STAT),
 223         REGISTER_AZ(CS_DEBUG),
 224         REGISTER_AZ(ALTERA_BUILD),
 225         REGISTER_AZ(CSR_SPARE),
 226         REGISTER_AB(PCIE_SD_CTL0123),
 227         REGISTER_AB(PCIE_SD_CTL45),
 228         REGISTER_AB(PCIE_PCS_CTL_STAT),
 229         /* DEBUG_DATA_OUT is not used */
 230         /* DRV_EV is WO */
 231         REGISTER_AZ(EVQ_CTL),
 232         REGISTER_AZ(EVQ_CNT1),
 233         REGISTER_AZ(EVQ_CNT2),
 234         REGISTER_AZ(BUF_TBL_CFG),
 235         REGISTER_AZ(SRM_RX_DC_CFG),
 236         REGISTER_AZ(SRM_TX_DC_CFG),
 237         REGISTER_AZ(SRM_CFG),
 238         /* BUF_TBL_UPD is WO */
 239         REGISTER_AZ(SRM_UPD_EVQ),
 240         REGISTER_AZ(SRAM_PARITY),
 241         REGISTER_AZ(RX_CFG),
 242         REGISTER_BZ(RX_FILTER_CTL),
 243         /* RX_FLUSH_DESCQ is WO */
 244         REGISTER_AZ(RX_DC_CFG),
 245         REGISTER_AZ(RX_DC_PF_WM),
 246         REGISTER_BZ(RX_RSS_TKEY),
 247         /* RX_NODESC_DROP is RC */
 248         REGISTER_AA(RX_SELF_RST),
 249         /* RX_DEBUG, RX_PUSH_DROP are not used */
 250         REGISTER_CZ(RX_RSS_IPV6_REG1),
 251         REGISTER_CZ(RX_RSS_IPV6_REG2),
 252         REGISTER_CZ(RX_RSS_IPV6_REG3),
 253         /* TX_FLUSH_DESCQ is WO */
 254         REGISTER_AZ(TX_DC_CFG),
 255         REGISTER_AA(TX_CHKSM_CFG),
 256         REGISTER_AZ(TX_CFG),
 257         /* TX_PUSH_DROP is not used */
 258         REGISTER_AZ(TX_RESERVED),
 259         REGISTER_BZ(TX_PACE),
 260         /* TX_PACE_DROP_QID is RC */
 261         REGISTER_BB(TX_VLAN),
 262         REGISTER_BZ(TX_IPFIL_PORTEN),
 263         REGISTER_AB(MD_TXD),
 264         REGISTER_AB(MD_RXD),
 265         REGISTER_AB(MD_CS),
 266         REGISTER_AB(MD_PHY_ADR),
 267         REGISTER_AB(MD_ID),
 268         /* MD_STAT is RC */
 269         REGISTER_AB(MAC_STAT_DMA),
 270         REGISTER_AB(MAC_CTRL),
 271         REGISTER_BB(GEN_MODE),
 272         REGISTER_AB(MAC_MC_HASH_REG0),
 273         REGISTER_AB(MAC_MC_HASH_REG1),
 274         REGISTER_AB(GM_CFG1),
 275         REGISTER_AB(GM_CFG2),
 276         /* GM_IPG and GM_HD are not used */
 277         REGISTER_AB(GM_MAX_FLEN),
 278         /* GM_TEST is not used */
 279         REGISTER_AB(GM_ADR1),
 280         REGISTER_AB(GM_ADR2),
 281         REGISTER_AB(GMF_CFG0),
 282         REGISTER_AB(GMF_CFG1),
 283         REGISTER_AB(GMF_CFG2),
 284         REGISTER_AB(GMF_CFG3),
 285         REGISTER_AB(GMF_CFG4),
 286         REGISTER_AB(GMF_CFG5),
 287         REGISTER_BB(TX_SRC_MAC_CTL),
 288         REGISTER_AB(XM_ADR_LO),
 289         REGISTER_AB(XM_ADR_HI),
 290         REGISTER_AB(XM_GLB_CFG),
 291         REGISTER_AB(XM_TX_CFG),
 292         REGISTER_AB(XM_RX_CFG),
 293         REGISTER_AB(XM_MGT_INT_MASK),
 294         REGISTER_AB(XM_FC),
 295         REGISTER_AB(XM_PAUSE_TIME),
 296         REGISTER_AB(XM_TX_PARAM),
 297         REGISTER_AB(XM_RX_PARAM),
 298         /* XM_MGT_INT_MSK (note no 'A') is RC */
 299         REGISTER_AB(XX_PWR_RST),
 300         REGISTER_AB(XX_SD_CTL),
 301         REGISTER_AB(XX_TXDRV_CTL),
 302         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
 303         /* XX_CORE_STAT is partly RC */
 304         REGISTER_DZ(BIU_HW_REV_ID),
 305         REGISTER_DZ(MC_DB_LWRD),
 306         REGISTER_DZ(MC_DB_HWRD),
 307 };
 308
 309 struct efx_nic_reg_table {
 310         u32 offset:24;
 311         u32 min_revision:3, max_revision:3;
 312         u32 step:6, rows:21;
 313 };
 314
 315 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
 316         offset,                                                         \
 317         REGISTER_REVISION_ ## arch ## min_rev,                          \
 318         REGISTER_REVISION_ ## arch ## max_rev,                          \
 319         step, rows                                                      \
 320 }
 321 #define REGISTER_TABLE(name, arch, min_rev, max_rev)                    \
 322         REGISTER_TABLE_DIMENSIONS(                                      \
 323                 name, arch ## R_ ## min_rev ## max_rev ## _ ## name,    \
 324                 arch, min_rev, max_rev,                                 \
 325                 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
 326                 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
 327 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
 328 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
 329 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
 330 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
 331 #define REGISTER_TABLE_BB_CZ(name)                                      \
 332         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B,        \
 333                                   FR_BZ_ ## name ## _STEP,              \
 334                                   FR_BB_ ## name ## _ROWS),             \
 335         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z,        \
 336                                   FR_BZ_ ## name ## _STEP,              \
 337                                   FR_CZ_ ## name ## _ROWS)
 338 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
 339 #define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
 340
 341 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
 342         /* DRIVER is not used */
 343         /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
 344         REGISTER_TABLE_BB(TX_IPFIL_TBL),
 345         REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
 346         REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
 347         REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
 348         REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
 349         REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
 350         REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
 351         REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
 352         /* We can't reasonably read all of the buffer table (up to 8MB!).
 353          * However this driver will only use a few entries.  Reading
 354          * 1K entries allows for some expansion of queue count and
 355          * size before we need to change the version. */
 356         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
 357                                   F, A, A, 8, 1024),
 358         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
 359                                   F, B, Z, 8, 1024),
 360         REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
 361         REGISTER_TABLE_BB_CZ(TIMER_TBL),
 362         REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
 363         REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
 364         /* TX_FILTER_TBL0 is huge and not used by this driver */
 365         REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
 366         REGISTER_TABLE_CZ(MC_TREG_SMEM),
 367         /* MSIX_PBA_TABLE is not mapped */
 368         /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
 369         REGISTER_TABLE_BZ(RX_FILTER_TBL0),
 370         REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
 371 };
 372
 373 size_t efx_nic_get_regs_len(struct efx_nic *efx)
 374 {
 375         const struct efx_nic_reg *reg;
 376         const struct efx_nic_reg_table *table;
 377         size_t len = 0;
 378
 379         for (reg = efx_nic_regs;
 380              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 381              reg++)
 382                 if (efx->type->revision >= reg->min_revision &&
 383                     efx->type->revision <= reg->max_revision)
 384                         len += sizeof(efx_oword_t);
 385
 386         for (table = efx_nic_reg_tables;
 387              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 388              table++)
 389                 if (efx->type->revision >= table->min_revision &&
 390                     efx->type->revision <= table->max_revision)
 391                         len += table->rows * min_t(size_t, table->step, 16);
 392
 393         return len;
 394 }
 395
 396 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
 397 {
 398         const struct efx_nic_reg *reg;
 399         const struct efx_nic_reg_table *table;
 400
 401         for (reg = efx_nic_regs;
 402              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 403              reg++) {
 404                 if (efx->type->revision >= reg->min_revision &&
 405                     efx->type->revision <= reg->max_revision) {
 406                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
 407                         buf += sizeof(efx_oword_t);
 408                 }
 409         }
 410
 411         for (table = efx_nic_reg_tables;
 412              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 413              table++) {
 414                 size_t size, i;
 415
 416                 if (!(efx->type->revision >= table->min_revision &&
 417                       efx->type->revision <= table->max_revision))
 418                         continue;
 419
 420                 size = min_t(size_t, table->step, 16);
 421
 422                 for (i = 0; i < table->rows; i++) {
 423                         switch (table->step) {
 424                         case 4: /* 32-bit SRAM */
 425                                 efx_readd(efx, buf, table->offset + 4 * i);
 426                                 break;
 427                         case 8: /* 64-bit SRAM */
 428                                 efx_sram_readq(efx,
 429                                                efx->membase + table->offset,
 430                                                buf, i);
 431                                 break;
 432                         case 16: /* 128-bit-readable register */
 433                                 efx_reado_table(efx, buf, table->offset, i);
 434                                 break;
 435                         case 32: /* 128-bit register, interleaved */
 436                                 efx_reado_table(efx, buf, table->offset, 2 * i);
 437                                 break;
 438                         default:
 439                                 WARN_ON(1);
 440                                 return;
 441                         }
 442                         buf += size;
 443                 }
 444         }
 445 }
 446
 447 /**
 448  * efx_nic_describe_stats - Describe supported statistics for ethtool
 449  * @desc: Array of &struct efx_hw_stat_desc describing the statistics
 450  * @count: Length of the @desc array
 451  * @mask: Bitmask of which elements of @desc are enabled
 452  * @names: Buffer to copy names to, or %NULL.  The names are copied
 453  *      starting at intervals of %ETH_GSTRING_LEN bytes.
 454  *
 455  * Returns the number of visible statistics, i.e. the number of set
 456  * bits in the first @count bits of @mask for which a name is defined.
 457  */
 458 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
 459                               const unsigned long *mask, u8 *names)
 460 {
 461         size_t visible = 0;
 462         size_t index;
 463
 464         for_each_set_bit(index, mask, count) {
 465                 if (desc[index].name) {
 466                         if (names) {
 467                                 strlcpy(names, desc[index].name,
 468                                         ETH_GSTRING_LEN);
 469                                 names += ETH_GSTRING_LEN;
 470                         }
 471                         ++visible;
 472                 }
 473         }
 474
 475         return visible;
 476 }
 477
 478 /**
 479  * efx_nic_copy_stats - Copy stats from the DMA buffer in to an
 480  *      intermediate buffer. This is used to get a consistent
 481  *      set of stats while the DMA buffer can be written at any time
 482  *      by the NIC.
 483  * @efx: The associated NIC.
 484  * @dest: Destination buffer. Must be the same size as the DMA buffer.
 485  */
 486 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest)
 487 {
 488         __le64 *dma_stats = efx->stats_buffer.addr;
 489         __le64 generation_start, generation_end;
 490         int rc = 0, retry;
 491
 492         if (!dest)
 493                 return 0;
 494
 495         if (!dma_stats)
 496                 goto return_zeroes;
 497
 498         /* If we're unlucky enough to read statistics during the DMA, wait
 499          * up to 10ms for it to finish (typically takes <500us)
 500          */
 501         for (retry = 0; retry < 100; ++retry) {
 502                 generation_end = dma_stats[efx->num_mac_stats - 1];
 503                 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 504                         goto return_zeroes;
 505                 rmb();
 506                 memcpy(dest, dma_stats, efx->num_mac_stats * sizeof(__le64));
 507                 rmb();
 508                 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 509                 if (generation_end == generation_start)
 510                         return 0; /* return good data */
 511                 udelay(100);
 512         }
 513
 514         rc = -EIO;
 515
 516 return_zeroes:
 517         memset(dest, 0, efx->num_mac_stats * sizeof(u64));
 518         return rc;
 519 }
 520
 521 /**
 522  * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
 523  * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
 524  *      layout.  DMA widths of 0, 16, 32 and 64 are supported; where
 525  *      the width is specified as 0 the corresponding element of
 526  *      @stats is not updated.
 527  * @count: Length of the @desc array
 528  * @mask: Bitmask of which elements of @desc are enabled
 529  * @stats: Buffer to update with the converted statistics.  The length
 530  *      of this array must be at least @count.
 531  * @dma_buf: DMA buffer containing hardware statistics
 532  * @accumulate: If set, the converted values will be added rather than
 533  *      directly stored to the corresponding elements of @stats
 534  */
 535 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
 536                           const unsigned long *mask,
 537                           u64 *stats, const void *dma_buf, bool accumulate)
 538 {
 539         size_t index;
 540
 541         for_each_set_bit(index, mask, count) {
 542                 if (desc[index].dma_width) {
 543                         const void *addr = dma_buf + desc[index].offset;
 544                         u64 val;
 545
 546                         switch (desc[index].dma_width) {
 547                         case 16:
 548                                 val = le16_to_cpup((__le16 *)addr);
 549                                 break;
 550                         case 32:
 551                                 val = le32_to_cpup((__le32 *)addr);
 552                                 break;
 553                         case 64:
 554                                 val = le64_to_cpup((__le64 *)addr);
 555                                 break;
 556                         default:
 557                                 WARN_ON(1);
 558                                 val = 0;
 559                                 break;
 560                         }
 561
 562                         if (accumulate)
 563                                 stats[index] += val;
 564                         else
 565                                 stats[index] = val;
 566                 }
 567         }
 568 }
 569
 570 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
 571 {
 572         /* if down, or this is the first update after coming up */
 573         if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
 574                 efx->rx_nodesc_drops_while_down +=
 575                         *rx_nodesc_drops - efx->rx_nodesc_drops_total;
 576         efx->rx_nodesc_drops_total = *rx_nodesc_drops;
 577         efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
 578         *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
 579 }