1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2020, Intel Corporation
3 * DWMAC Intel header file
6 #ifndef __DWMAC_INTEL_H__
7 #define __DWMAC_INTEL_H__
9 #define POLL_DELAY_US 8
12 #define SERDES_GSR0 0x5 /* Global Status Reg0 */
13 #define SERDES_GCR0 0xb /* Global Configuration Reg0 */
16 #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
17 #define SERDES_RST BIT(2) /* Serdes Reset */
18 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
19 #define SERDES_PWR_ST_SHIFT 4
20 #define SERDES_PWR_ST_P0 0x0
21 #define SERDES_PWR_ST_P3 0x3
23 #endif /* __DWMAC_INTEL_H__ */