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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_core.c
blob29f765a246a05f91ae4f53081b583af73a63b6cf
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
5 *
6 * This only implements the mac core functions for this chip.
7 *
8 * Copyright (C) 2015 STMicroelectronics Ltd
9 *
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
11 */
12
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
16 #include <linux/io.h>
17 #include <net/dsa.h>
18 #include "stmmac.h"
19 #include "stmmac_pcs.h"
20 #include "dwmac4.h"
21 #include "dwmac5.h"
22
23 static void dwmac4_core_init(struct mac_device_info *hw,
24 struct net_device *dev)
25 {
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONFIG);
28
29 value |= GMAC_CORE_INIT;
30
31 if (hw->ps) {
32 value |= GMAC_CONFIG_TE;
33
34 value &= hw->link.speed_mask;
35 switch (hw->ps) {
36 case SPEED_1000:
37 value |= hw->link.speed1000;
38 break;
39 case SPEED_100:
40 value |= hw->link.speed100;
41 break;
42 case SPEED_10:
43 value |= hw->link.speed10;
44 break;
45 }
46 }
47
48 writel(value, ioaddr + GMAC_CONFIG);
49
50 /* Enable GMAC interrupts */
51 value = GMAC_INT_DEFAULT_ENABLE;
52
53 if (hw->pcs)
54 value |= GMAC_PCS_IRQ_DEFAULT;
55
56 writel(value, ioaddr + GMAC_INT_EN);
57 }
58
59 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
60 u8 mode, u32 queue)
61 {
62 void __iomem *ioaddr = hw->pcsr;
63 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
64
65 value &= GMAC_RX_QUEUE_CLEAR(queue);
66 if (mode == MTL_QUEUE_AVB)
67 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
68 else if (mode == MTL_QUEUE_DCB)
69 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
70
71 writel(value, ioaddr + GMAC_RXQ_CTRL0);
72 }
73
74 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
75 u32 prio, u32 queue)
76 {
77 void __iomem *ioaddr = hw->pcsr;
78 u32 base_register;
79 u32 value;
80
81 base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
82 if (queue >= 4)
83 queue -= 4;
84
85 value = readl(ioaddr + base_register);
86
87 value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
88 value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
89 GMAC_RXQCTRL_PSRQX_MASK(queue);
90 writel(value, ioaddr + base_register);
91 }
92
93 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
94 u32 prio, u32 queue)
95 {
96 void __iomem *ioaddr = hw->pcsr;
97 u32 base_register;
98 u32 value;
99
100 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
101 if (queue >= 4)
102 queue -= 4;
103
104 value = readl(ioaddr + base_register);
105
106 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
107 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
108 GMAC_TXQCTRL_PSTQX_MASK(queue);
109
110 writel(value, ioaddr + base_register);
111 }
112
113 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
114 u8 packet, u32 queue)
115 {
116 void __iomem *ioaddr = hw->pcsr;
117 u32 value;
118
119 static const struct stmmac_rx_routing route_possibilities[] = {
120 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
121 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
122 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
123 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
124 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
125 };
126
127 value = readl(ioaddr + GMAC_RXQ_CTRL1);
128
129 /* routing configuration */
130 value &= ~route_possibilities[packet - 1].reg_mask;
131 value |= (queue << route_possibilities[packet-1].reg_shift) &
132 route_possibilities[packet - 1].reg_mask;
133
134 /* some packets require extra ops */
135 if (packet == PACKET_AVCPQ) {
136 value &= ~GMAC_RXQCTRL_TACPQE;
137 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
138 } else if (packet == PACKET_MCBCQ) {
139 value &= ~GMAC_RXQCTRL_MCBCQEN;
140 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
141 }
142
143 writel(value, ioaddr + GMAC_RXQ_CTRL1);
144 }
145
146 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
147 u32 rx_alg)
148 {
149 void __iomem *ioaddr = hw->pcsr;
150 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
151
152 value &= ~MTL_OPERATION_RAA;
153 switch (rx_alg) {
154 case MTL_RX_ALGORITHM_SP:
155 value |= MTL_OPERATION_RAA_SP;
156 break;
157 case MTL_RX_ALGORITHM_WSP:
158 value |= MTL_OPERATION_RAA_WSP;
159 break;
160 default:
161 break;
162 }
163
164 writel(value, ioaddr + MTL_OPERATION_MODE);
165 }
166
167 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
168 u32 tx_alg)
169 {
170 void __iomem *ioaddr = hw->pcsr;
171 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
172
173 value &= ~MTL_OPERATION_SCHALG_MASK;
174 switch (tx_alg) {
175 case MTL_TX_ALGORITHM_WRR:
176 value |= MTL_OPERATION_SCHALG_WRR;
177 break;
178 case MTL_TX_ALGORITHM_WFQ:
179 value |= MTL_OPERATION_SCHALG_WFQ;
180 break;
181 case MTL_TX_ALGORITHM_DWRR:
182 value |= MTL_OPERATION_SCHALG_DWRR;
183 break;
184 case MTL_TX_ALGORITHM_SP:
185 value |= MTL_OPERATION_SCHALG_SP;
186 break;
187 default:
188 break;
189 }
190
191 writel(value, ioaddr + MTL_OPERATION_MODE);
192 }
193
194 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
195 u32 weight, u32 queue)
196 {
197 void __iomem *ioaddr = hw->pcsr;
198 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
199
200 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
201 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
202 writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
203 }
204
205 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
206 {
207 void __iomem *ioaddr = hw->pcsr;
208 u32 value;
209
210 if (queue < 4)
211 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
212 else
213 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
214
215 if (queue == 0 || queue == 4) {
216 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
217 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
218 } else {
219 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
220 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
221 }
222
223 if (queue < 4)
224 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
225 else
226 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
227 }
228
229 static void dwmac4_config_cbs(struct mac_device_info *hw,
230 u32 send_slope, u32 idle_slope,
231 u32 high_credit, u32 low_credit, u32 queue)
232 {
233 void __iomem *ioaddr = hw->pcsr;
234 u32 value;
235
236 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
237 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
238 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
239 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
240 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
241
242 /* enable AV algorithm */
243 value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
244 value |= MTL_ETS_CTRL_AVALG;
245 value |= MTL_ETS_CTRL_CC;
246 writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
247
248 /* configure send slope */
249 value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
250 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
251 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
252 writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
253
254 /* configure idle slope (same register as tx weight) */
255 dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
256
257 /* configure high credit */
258 value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
259 value &= ~MTL_HIGH_CRED_HC_MASK;
260 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
261 writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
262
263 /* configure high credit */
264 value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
265 value &= ~MTL_HIGH_CRED_LC_MASK;
266 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
267 writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
268 }
269
270 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
271 {
272 void __iomem *ioaddr = hw->pcsr;
273 int i;
274
275 for (i = 0; i < GMAC_REG_NUM; i++)
276 reg_space[i] = readl(ioaddr + i * 4);
277 }
278
279 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
280 {
281 void __iomem *ioaddr = hw->pcsr;
282 u32 value = readl(ioaddr + GMAC_CONFIG);
283
284 if (hw->rx_csum)
285 value |= GMAC_CONFIG_IPC;
286 else
287 value &= ~GMAC_CONFIG_IPC;
288
289 writel(value, ioaddr + GMAC_CONFIG);
290
291 value = readl(ioaddr + GMAC_CONFIG);
292
293 return !!(value & GMAC_CONFIG_IPC);
294 }
295
296 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
297 {
298 void __iomem *ioaddr = hw->pcsr;
299 unsigned int pmt = 0;
300 u32 config;
301
302 if (mode & WAKE_MAGIC) {
303 pr_debug("GMAC: WOL Magic frame\n");
304 pmt |= power_down | magic_pkt_en;
305 }
306 if (mode & WAKE_UCAST) {
307 pr_debug("GMAC: WOL on global unicast\n");
308 pmt |= power_down | global_unicast | wake_up_frame_en;
309 }
310
311 if (pmt) {
312 /* The receiver must be enabled for WOL before powering down */
313 config = readl(ioaddr + GMAC_CONFIG);
314 config |= GMAC_CONFIG_RE;
315 writel(config, ioaddr + GMAC_CONFIG);
316 }
317 writel(pmt, ioaddr + GMAC_PMT);
318 }
319
320 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
321 unsigned char *addr, unsigned int reg_n)
322 {
323 void __iomem *ioaddr = hw->pcsr;
324
325 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
326 GMAC_ADDR_LOW(reg_n));
327 }
328
329 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
330 unsigned char *addr, unsigned int reg_n)
331 {
332 void __iomem *ioaddr = hw->pcsr;
333
334 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
335 GMAC_ADDR_LOW(reg_n));
336 }
337
338 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
339 bool en_tx_lpi_clockgating)
340 {
341 void __iomem *ioaddr = hw->pcsr;
342 u32 value;
343
344 /* Enable the link status receive on RGMII, SGMII ore SMII
345 * receive path and instruct the transmit to enter in LPI
346 * state.
347 */
348 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
349 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
350
351 if (en_tx_lpi_clockgating)
352 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
353
354 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
355 }
356
357 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
358 {
359 void __iomem *ioaddr = hw->pcsr;
360 u32 value;
361
362 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
363 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
364 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
365 }
366
367 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
368 {
369 void __iomem *ioaddr = hw->pcsr;
370 u32 value;
371
372 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
373
374 if (link)
375 value |= GMAC4_LPI_CTRL_STATUS_PLS;
376 else
377 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
378
379 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
380 }
381
382 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, int et)
383 {
384 void __iomem *ioaddr = hw->pcsr;
385 int value = et & STMMAC_ET_MAX;
386 int regval;
387
388 /* Program LPI entry timer value into register */
389 writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
390
391 /* Enable/disable LPI entry timer */
392 regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
393 regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
394
395 if (et)
396 regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
397 else
398 regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
399
400 writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
401 }
402
403 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
404 {
405 void __iomem *ioaddr = hw->pcsr;
406 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
407
408 /* Program the timers in the LPI timer control register:
409 * LS: minimum time (ms) for which the link
410 * status from PHY should be ok before transmitting
411 * the LPI pattern.
412 * TW: minimum time (us) for which the core waits
413 * after it has stopped transmitting the LPI pattern.
414 */
415 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
416 }
417
418 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
419 {
420 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
421 u32 val;
422
423 val = readl(ioaddr + GMAC_VLAN_TAG);
424 val &= ~GMAC_VLAN_TAG_VID;
425 val |= GMAC_VLAN_TAG_ETV | vid;
426
427 writel(val, ioaddr + GMAC_VLAN_TAG);
428 }
429
430 static int dwmac4_write_vlan_filter(struct net_device *dev,
431 struct mac_device_info *hw,
432 u8 index, u32 data)
433 {
434 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
435 int i, timeout = 10;
436 u32 val;
437
438 if (index >= hw->num_vlan)
439 return -EINVAL;
440
441 writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
442
443 val = readl(ioaddr + GMAC_VLAN_TAG);
444 val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
445 GMAC_VLAN_TAG_CTRL_CT |
446 GMAC_VLAN_TAG_CTRL_OB);
447 val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
448
449 writel(val, ioaddr + GMAC_VLAN_TAG);
450
451 for (i = 0; i < timeout; i++) {
452 val = readl(ioaddr + GMAC_VLAN_TAG);
453 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
454 return 0;
455 udelay(1);
456 }
457
458 netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
459
460 return -EBUSY;
461 }
462
463 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
464 struct mac_device_info *hw,
465 __be16 proto, u16 vid)
466 {
467 int index = -1;
468 u32 val = 0;
469 int i, ret;
470
471 if (vid > 4095)
472 return -EINVAL;
473
474 if (hw->promisc) {
475 netdev_err(dev,
476 "Adding VLAN in promisc mode not supported\n");
477 return -EPERM;
478 }
479
480 /* Single Rx VLAN Filter */
481 if (hw->num_vlan == 1) {
482 /* For single VLAN filter, VID 0 means VLAN promiscuous */
483 if (vid == 0) {
484 netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
485 return -EPERM;
486 }
487
488 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
489 netdev_err(dev, "Only single VLAN ID supported\n");
490 return -EPERM;
491 }
492
493 hw->vlan_filter[0] = vid;
494 dwmac4_write_single_vlan(dev, vid);
495
496 return 0;
497 }
498
499 /* Extended Rx VLAN Filter Enable */
500 val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
501
502 for (i = 0; i < hw->num_vlan; i++) {
503 if (hw->vlan_filter[i] == val)
504 return 0;
505 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
506 index = i;
507 }
508
509 if (index == -1) {
510 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
511 hw->num_vlan);
512 return -EPERM;
513 }
514
515 ret = dwmac4_write_vlan_filter(dev, hw, index, val);
516
517 if (!ret)
518 hw->vlan_filter[index] = val;
519
520 return ret;
521 }
522
523 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
524 struct mac_device_info *hw,
525 __be16 proto, u16 vid)
526 {
527 int i, ret = 0;
528
529 if (hw->promisc) {
530 netdev_err(dev,
531 "Deleting VLAN in promisc mode not supported\n");
532 return -EPERM;
533 }
534
535 /* Single Rx VLAN Filter */
536 if (hw->num_vlan == 1) {
537 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
538 hw->vlan_filter[0] = 0;
539 dwmac4_write_single_vlan(dev, 0);
540 }
541 return 0;
542 }
543
544 /* Extended Rx VLAN Filter Enable */
545 for (i = 0; i < hw->num_vlan; i++) {
546 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
547 ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
548
549 if (!ret)
550 hw->vlan_filter[i] = 0;
551 else
552 return ret;
553 }
554 }
555
556 return ret;
557 }
558
559 static void dwmac4_vlan_promisc_enable(struct net_device *dev,
560 struct mac_device_info *hw)
561 {
562 void __iomem *ioaddr = hw->pcsr;
563 u32 value;
564 u32 hash;
565 u32 val;
566 int i;
567
568 /* Single Rx VLAN Filter */
569 if (hw->num_vlan == 1) {
570 dwmac4_write_single_vlan(dev, 0);
571 return;
572 }
573
574 /* Extended Rx VLAN Filter Enable */
575 for (i = 0; i < hw->num_vlan; i++) {
576 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
577 val = hw->vlan_filter[i] & ~GMAC_VLAN_TAG_DATA_VEN;
578 dwmac4_write_vlan_filter(dev, hw, i, val);
579 }
580 }
581
582 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
583 if (hash & GMAC_VLAN_VLHT) {
584 value = readl(ioaddr + GMAC_VLAN_TAG);
585 if (value & GMAC_VLAN_VTHM) {
586 value &= ~GMAC_VLAN_VTHM;
587 writel(value, ioaddr + GMAC_VLAN_TAG);
588 }
589 }
590 }
591
592 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
593 struct mac_device_info *hw)
594 {
595 void __iomem *ioaddr = hw->pcsr;
596 u32 value;
597 u32 hash;
598 u32 val;
599 int i;
600
601 /* Single Rx VLAN Filter */
602 if (hw->num_vlan == 1) {
603 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
604 return;
605 }
606
607 /* Extended Rx VLAN Filter Enable */
608 for (i = 0; i < hw->num_vlan; i++) {
609 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
610 val = hw->vlan_filter[i];
611 dwmac4_write_vlan_filter(dev, hw, i, val);
612 }
613 }
614
615 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
616 if (hash & GMAC_VLAN_VLHT) {
617 value = readl(ioaddr + GMAC_VLAN_TAG);
618 value |= GMAC_VLAN_VTHM;
619 writel(value, ioaddr + GMAC_VLAN_TAG);
620 }
621 }
622
623 static void dwmac4_set_filter(struct mac_device_info *hw,
624 struct net_device *dev)
625 {
626 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
627 int numhashregs = (hw->multicast_filter_bins >> 5);
628 int mcbitslog2 = hw->mcast_bits_log2;
629 unsigned int value;
630 u32 mc_filter[8];
631 int i;
632
633 memset(mc_filter, 0, sizeof(mc_filter));
634
635 value = readl(ioaddr + GMAC_PACKET_FILTER);
636 value &= ~GMAC_PACKET_FILTER_HMC;
637 value &= ~GMAC_PACKET_FILTER_HPF;
638 value &= ~GMAC_PACKET_FILTER_PCF;
639 value &= ~GMAC_PACKET_FILTER_PM;
640 value &= ~GMAC_PACKET_FILTER_PR;
641 if (dev->flags & IFF_PROMISC) {
642 /* VLAN Tag Filter Fail Packets Queuing */
643 if (hw->vlan_fail_q_en) {
644 value = readl(ioaddr + GMAC_RXQ_CTRL4);
645 value &= ~GMAC_RXQCTRL_VFFQ_MASK;
646 value |= GMAC_RXQCTRL_VFFQE |
647 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
648 writel(value, ioaddr + GMAC_RXQ_CTRL4);
649 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
650 } else {
651 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
652 }
653
654 } else if ((dev->flags & IFF_ALLMULTI) ||
655 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
656 /* Pass all multi */
657 value |= GMAC_PACKET_FILTER_PM;
658 /* Set all the bits of the HASH tab */
659 memset(mc_filter, 0xff, sizeof(mc_filter));
660 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
661 struct netdev_hw_addr *ha;
662
663 /* Hash filter for multicast */
664 value |= GMAC_PACKET_FILTER_HMC;
665
666 netdev_for_each_mc_addr(ha, dev) {
667 /* The upper n bits of the calculated CRC are used to
668 * index the contents of the hash table. The number of
669 * bits used depends on the hardware configuration
670 * selected at core configuration time.
671 */
672 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
673 ETH_ALEN)) >> (32 - mcbitslog2);
674 /* The most significant bit determines the register to
675 * use (H/L) while the other 5 bits determine the bit
676 * within the register.
677 */
678 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
679 }
680 }
681
682 for (i = 0; i < numhashregs; i++)
683 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
684
685 value |= GMAC_PACKET_FILTER_HPF;
686
687 /* Handle multiple unicast addresses */
688 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
689 /* Switch to promiscuous mode if more than 128 addrs
690 * are required
691 */
692 value |= GMAC_PACKET_FILTER_PR;
693 } else {
694 struct netdev_hw_addr *ha;
695 int reg = 1;
696
697 netdev_for_each_uc_addr(ha, dev) {
698 dwmac4_set_umac_addr(hw, ha->addr, reg);
699 reg++;
700 }
701
702 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
703 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
704 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
705 reg++;
706 }
707 }
708
709 /* VLAN filtering */
710 if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
711 value |= GMAC_PACKET_FILTER_VTFE;
712
713 writel(value, ioaddr + GMAC_PACKET_FILTER);
714
715 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) {
716 if (!hw->promisc) {
717 hw->promisc = 1;
718 dwmac4_vlan_promisc_enable(dev, hw);
719 }
720 } else {
721 if (hw->promisc) {
722 hw->promisc = 0;
723 dwmac4_restore_hw_vlan_rx_fltr(dev, hw);
724 }
725 }
726 }
727
728 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
729 unsigned int fc, unsigned int pause_time,
730 u32 tx_cnt)
731 {
732 void __iomem *ioaddr = hw->pcsr;
733 unsigned int flow = 0;
734 u32 queue = 0;
735
736 pr_debug("GMAC Flow-Control:\n");
737 if (fc & FLOW_RX) {
738 pr_debug("\tReceive Flow-Control ON\n");
739 flow |= GMAC_RX_FLOW_CTRL_RFE;
740 }
741 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
742
743 if (fc & FLOW_TX) {
744 pr_debug("\tTransmit Flow-Control ON\n");
745
746 if (duplex)
747 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
748
749 for (queue = 0; queue < tx_cnt; queue++) {
750 flow = GMAC_TX_FLOW_CTRL_TFE;
751
752 if (duplex)
753 flow |=
754 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
755
756 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
757 }
758 } else {
759 for (queue = 0; queue < tx_cnt; queue++)
760 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
761 }
762 }
763
764 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
765 bool loopback)
766 {
767 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
768 }
769
770 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
771 {
772 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
773 }
774
775 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
776 {
777 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
778 }
779
780 /* RGMII or SMII interface */
781 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
782 {
783 u32 status;
784
785 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
786 x->irq_rgmii_n++;
787
788 /* Check the link status */
789 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
790 int speed_value;
791
792 x->pcs_link = 1;
793
794 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
795 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
796 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
797 x->pcs_speed = SPEED_1000;
798 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
799 x->pcs_speed = SPEED_100;
800 else
801 x->pcs_speed = SPEED_10;
802
803 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
804
805 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
806 x->pcs_duplex ? "Full" : "Half");
807 } else {
808 x->pcs_link = 0;
809 pr_info("Link is Down\n");
810 }
811 }
812
813 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
814 {
815 void __iomem *ioaddr = hw->pcsr;
816 u32 mtl_int_qx_status;
817 int ret = 0;
818
819 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
820
821 /* Check MTL Interrupt */
822 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
823 /* read Queue x Interrupt status */
824 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
825
826 if (status & MTL_RX_OVERFLOW_INT) {
827 /* clear Interrupt */
828 writel(status | MTL_RX_OVERFLOW_INT,
829 ioaddr + MTL_CHAN_INT_CTRL(chan));
830 ret = CORE_IRQ_MTL_RX_OVERFLOW;
831 }
832 }
833
834 return ret;
835 }
836
837 static int dwmac4_irq_status(struct mac_device_info *hw,
838 struct stmmac_extra_stats *x)
839 {
840 void __iomem *ioaddr = hw->pcsr;
841 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
842 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
843 int ret = 0;
844
845 /* Discard disabled bits */
846 intr_status &= intr_enable;
847
848 /* Not used events (e.g. MMC interrupts) are not handled. */
849 if ((intr_status & mmc_tx_irq))
850 x->mmc_tx_irq_n++;
851 if (unlikely(intr_status & mmc_rx_irq))
852 x->mmc_rx_irq_n++;
853 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
854 x->mmc_rx_csum_offload_irq_n++;
855 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
856 if (unlikely(intr_status & pmt_irq)) {
857 readl(ioaddr + GMAC_PMT);
858 x->irq_receive_pmt_irq_n++;
859 }
860
861 /* MAC tx/rx EEE LPI entry/exit interrupts */
862 if (intr_status & lpi_irq) {
863 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
864 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
865
866 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
867 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
868 x->irq_tx_path_in_lpi_mode_n++;
869 }
870 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
871 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
872 x->irq_tx_path_exit_lpi_mode_n++;
873 }
874 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
875 x->irq_rx_path_in_lpi_mode_n++;
876 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
877 x->irq_rx_path_exit_lpi_mode_n++;
878 }
879
880 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
881 if (intr_status & PCS_RGSMIIIS_IRQ)
882 dwmac4_phystatus(ioaddr, x);
883
884 return ret;
885 }
886
887 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
888 u32 rx_queues, u32 tx_queues)
889 {
890 u32 value;
891 u32 queue;
892
893 for (queue = 0; queue < tx_queues; queue++) {
894 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
895
896 if (value & MTL_DEBUG_TXSTSFSTS)
897 x->mtl_tx_status_fifo_full++;
898 if (value & MTL_DEBUG_TXFSTS)
899 x->mtl_tx_fifo_not_empty++;
900 if (value & MTL_DEBUG_TWCSTS)
901 x->mmtl_fifo_ctrl++;
902 if (value & MTL_DEBUG_TRCSTS_MASK) {
903 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
904 >> MTL_DEBUG_TRCSTS_SHIFT;
905 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
906 x->mtl_tx_fifo_read_ctrl_write++;
907 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
908 x->mtl_tx_fifo_read_ctrl_wait++;
909 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
910 x->mtl_tx_fifo_read_ctrl_read++;
911 else
912 x->mtl_tx_fifo_read_ctrl_idle++;
913 }
914 if (value & MTL_DEBUG_TXPAUSED)
915 x->mac_tx_in_pause++;
916 }
917
918 for (queue = 0; queue < rx_queues; queue++) {
919 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
920
921 if (value & MTL_DEBUG_RXFSTS_MASK) {
922 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
923 >> MTL_DEBUG_RRCSTS_SHIFT;
924
925 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
926 x->mtl_rx_fifo_fill_level_full++;
927 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
928 x->mtl_rx_fifo_fill_above_thresh++;
929 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
930 x->mtl_rx_fifo_fill_below_thresh++;
931 else
932 x->mtl_rx_fifo_fill_level_empty++;
933 }
934 if (value & MTL_DEBUG_RRCSTS_MASK) {
935 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
936 MTL_DEBUG_RRCSTS_SHIFT;
937
938 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
939 x->mtl_rx_fifo_read_ctrl_flush++;
940 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
941 x->mtl_rx_fifo_read_ctrl_read_data++;
942 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
943 x->mtl_rx_fifo_read_ctrl_status++;
944 else
945 x->mtl_rx_fifo_read_ctrl_idle++;
946 }
947 if (value & MTL_DEBUG_RWCSTS)
948 x->mtl_rx_fifo_ctrl_active++;
949 }
950
951 /* GMAC debug */
952 value = readl(ioaddr + GMAC_DEBUG);
953
954 if (value & GMAC_DEBUG_TFCSTS_MASK) {
955 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
956 >> GMAC_DEBUG_TFCSTS_SHIFT;
957
958 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
959 x->mac_tx_frame_ctrl_xfer++;
960 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
961 x->mac_tx_frame_ctrl_pause++;
962 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
963 x->mac_tx_frame_ctrl_wait++;
964 else
965 x->mac_tx_frame_ctrl_idle++;
966 }
967 if (value & GMAC_DEBUG_TPESTS)
968 x->mac_gmii_tx_proto_engine++;
969 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
970 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
971 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
972 if (value & GMAC_DEBUG_RPESTS)
973 x->mac_gmii_rx_proto_engine++;
974 }
975
976 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
977 {
978 u32 value = readl(ioaddr + GMAC_CONFIG);
979
980 if (enable)
981 value |= GMAC_CONFIG_LM;
982 else
983 value &= ~GMAC_CONFIG_LM;
984
985 writel(value, ioaddr + GMAC_CONFIG);
986 }
987
988 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
989 __le16 perfect_match, bool is_double)
990 {
991 void __iomem *ioaddr = hw->pcsr;
992 u32 value;
993
994 writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
995
996 value = readl(ioaddr + GMAC_VLAN_TAG);
997
998 if (hash) {
999 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
1000 if (is_double) {
1001 value |= GMAC_VLAN_EDVLP;
1002 value |= GMAC_VLAN_ESVL;
1003 value |= GMAC_VLAN_DOVLTC;
1004 }
1005
1006 writel(value, ioaddr + GMAC_VLAN_TAG);
1007 } else if (perfect_match) {
1008 u32 value = GMAC_VLAN_ETV;
1009
1010 if (is_double) {
1011 value |= GMAC_VLAN_EDVLP;
1012 value |= GMAC_VLAN_ESVL;
1013 value |= GMAC_VLAN_DOVLTC;
1014 }
1015
1016 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
1017 } else {
1018 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
1019 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
1020 value &= ~GMAC_VLAN_DOVLTC;
1021 value &= ~GMAC_VLAN_VID;
1022
1023 writel(value, ioaddr + GMAC_VLAN_TAG);
1024 }
1025 }
1026
1027 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
1028 {
1029 u32 value = readl(ioaddr + GMAC_CONFIG);
1030
1031 value &= ~GMAC_CONFIG_SARC;
1032 value |= val << GMAC_CONFIG_SARC_SHIFT;
1033
1034 writel(value, ioaddr + GMAC_CONFIG);
1035 }
1036
1037 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1038 {
1039 void __iomem *ioaddr = hw->pcsr;
1040 u32 value;
1041
1042 value = readl(ioaddr + GMAC_VLAN_INCL);
1043 value |= GMAC_VLAN_VLTI;
1044 value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
1045 value &= ~GMAC_VLAN_VLC;
1046 value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1047 writel(value, ioaddr + GMAC_VLAN_INCL);
1048 }
1049
1050 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1051 u32 addr)
1052 {
1053 void __iomem *ioaddr = hw->pcsr;
1054 u32 value;
1055
1056 writel(addr, ioaddr + GMAC_ARP_ADDR);
1057
1058 value = readl(ioaddr + GMAC_CONFIG);
1059 if (en)
1060 value |= GMAC_CONFIG_ARPEN;
1061 else
1062 value &= ~GMAC_CONFIG_ARPEN;
1063 writel(value, ioaddr + GMAC_CONFIG);
1064 }
1065
1066 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1067 bool en, bool ipv6, bool sa, bool inv,
1068 u32 match)
1069 {
1070 void __iomem *ioaddr = hw->pcsr;
1071 u32 value;
1072
1073 value = readl(ioaddr + GMAC_PACKET_FILTER);
1074 value |= GMAC_PACKET_FILTER_IPFE;
1075 writel(value, ioaddr + GMAC_PACKET_FILTER);
1076
1077 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1078
1079 /* For IPv6 not both SA/DA filters can be active */
1080 if (ipv6) {
1081 value |= GMAC_L3PEN0;
1082 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1083 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1084 if (sa) {
1085 value |= GMAC_L3SAM0;
1086 if (inv)
1087 value |= GMAC_L3SAIM0;
1088 } else {
1089 value |= GMAC_L3DAM0;
1090 if (inv)
1091 value |= GMAC_L3DAIM0;
1092 }
1093 } else {
1094 value &= ~GMAC_L3PEN0;
1095 if (sa) {
1096 value |= GMAC_L3SAM0;
1097 if (inv)
1098 value |= GMAC_L3SAIM0;
1099 } else {
1100 value |= GMAC_L3DAM0;
1101 if (inv)
1102 value |= GMAC_L3DAIM0;
1103 }
1104 }
1105
1106 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1107
1108 if (sa) {
1109 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1110 } else {
1111 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1112 }
1113
1114 if (!en)
1115 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1116
1117 return 0;
1118 }
1119
1120 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1121 bool en, bool udp, bool sa, bool inv,
1122 u32 match)
1123 {
1124 void __iomem *ioaddr = hw->pcsr;
1125 u32 value;
1126
1127 value = readl(ioaddr + GMAC_PACKET_FILTER);
1128 value |= GMAC_PACKET_FILTER_IPFE;
1129 writel(value, ioaddr + GMAC_PACKET_FILTER);
1130
1131 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1132 if (udp) {
1133 value |= GMAC_L4PEN0;
1134 } else {
1135 value &= ~GMAC_L4PEN0;
1136 }
1137
1138 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1139 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1140 if (sa) {
1141 value |= GMAC_L4SPM0;
1142 if (inv)
1143 value |= GMAC_L4SPIM0;
1144 } else {
1145 value |= GMAC_L4DPM0;
1146 if (inv)
1147 value |= GMAC_L4DPIM0;
1148 }
1149
1150 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1151
1152 if (sa) {
1153 value = match & GMAC_L4SP0;
1154 } else {
1155 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1156 }
1157
1158 writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1159
1160 if (!en)
1161 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1162
1163 return 0;
1164 }
1165
1166 const struct stmmac_ops dwmac4_ops = {
1167 .core_init = dwmac4_core_init,
1168 .set_mac = stmmac_set_mac,
1169 .rx_ipc = dwmac4_rx_ipc_enable,
1170 .rx_queue_enable = dwmac4_rx_queue_enable,
1171 .rx_queue_prio = dwmac4_rx_queue_priority,
1172 .tx_queue_prio = dwmac4_tx_queue_priority,
1173 .rx_queue_routing = dwmac4_rx_queue_routing,
1174 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1175 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1176 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1177 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1178 .config_cbs = dwmac4_config_cbs,
1179 .dump_regs = dwmac4_dump_regs,
1180 .host_irq_status = dwmac4_irq_status,
1181 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1182 .flow_ctrl = dwmac4_flow_ctrl,
1183 .pmt = dwmac4_pmt,
1184 .set_umac_addr = dwmac4_set_umac_addr,
1185 .get_umac_addr = dwmac4_get_umac_addr,
1186 .set_eee_mode = dwmac4_set_eee_mode,
1187 .reset_eee_mode = dwmac4_reset_eee_mode,
1188 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1189 .set_eee_timer = dwmac4_set_eee_timer,
1190 .set_eee_pls = dwmac4_set_eee_pls,
1191 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1192 .pcs_rane = dwmac4_rane,
1193 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1194 .debug = dwmac4_debug,
1195 .set_filter = dwmac4_set_filter,
1196 .set_mac_loopback = dwmac4_set_mac_loopback,
1197 .update_vlan_hash = dwmac4_update_vlan_hash,
1198 .sarc_configure = dwmac4_sarc_configure,
1199 .enable_vlan = dwmac4_enable_vlan,
1200 .set_arp_offload = dwmac4_set_arp_offload,
1201 .config_l3_filter = dwmac4_config_l3_filter,
1202 .config_l4_filter = dwmac4_config_l4_filter,
1203 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1204 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1205 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1206 };
1207
1208 const struct stmmac_ops dwmac410_ops = {
1209 .core_init = dwmac4_core_init,
1210 .set_mac = stmmac_dwmac4_set_mac,
1211 .rx_ipc = dwmac4_rx_ipc_enable,
1212 .rx_queue_enable = dwmac4_rx_queue_enable,
1213 .rx_queue_prio = dwmac4_rx_queue_priority,
1214 .tx_queue_prio = dwmac4_tx_queue_priority,
1215 .rx_queue_routing = dwmac4_rx_queue_routing,
1216 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1217 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1218 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1219 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1220 .config_cbs = dwmac4_config_cbs,
1221 .dump_regs = dwmac4_dump_regs,
1222 .host_irq_status = dwmac4_irq_status,
1223 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1224 .flow_ctrl = dwmac4_flow_ctrl,
1225 .pmt = dwmac4_pmt,
1226 .set_umac_addr = dwmac4_set_umac_addr,
1227 .get_umac_addr = dwmac4_get_umac_addr,
1228 .set_eee_mode = dwmac4_set_eee_mode,
1229 .reset_eee_mode = dwmac4_reset_eee_mode,
1230 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1231 .set_eee_timer = dwmac4_set_eee_timer,
1232 .set_eee_pls = dwmac4_set_eee_pls,
1233 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1234 .pcs_rane = dwmac4_rane,
1235 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1236 .debug = dwmac4_debug,
1237 .set_filter = dwmac4_set_filter,
1238 .flex_pps_config = dwmac5_flex_pps_config,
1239 .set_mac_loopback = dwmac4_set_mac_loopback,
1240 .update_vlan_hash = dwmac4_update_vlan_hash,
1241 .sarc_configure = dwmac4_sarc_configure,
1242 .enable_vlan = dwmac4_enable_vlan,
1243 .set_arp_offload = dwmac4_set_arp_offload,
1244 .config_l3_filter = dwmac4_config_l3_filter,
1245 .config_l4_filter = dwmac4_config_l4_filter,
1246 .est_configure = dwmac5_est_configure,
1247 .fpe_configure = dwmac5_fpe_configure,
1248 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1249 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1250 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1251 };
1252
1253 const struct stmmac_ops dwmac510_ops = {
1254 .core_init = dwmac4_core_init,
1255 .set_mac = stmmac_dwmac4_set_mac,
1256 .rx_ipc = dwmac4_rx_ipc_enable,
1257 .rx_queue_enable = dwmac4_rx_queue_enable,
1258 .rx_queue_prio = dwmac4_rx_queue_priority,
1259 .tx_queue_prio = dwmac4_tx_queue_priority,
1260 .rx_queue_routing = dwmac4_rx_queue_routing,
1261 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1262 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1263 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1264 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1265 .config_cbs = dwmac4_config_cbs,
1266 .dump_regs = dwmac4_dump_regs,
1267 .host_irq_status = dwmac4_irq_status,
1268 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1269 .flow_ctrl = dwmac4_flow_ctrl,
1270 .pmt = dwmac4_pmt,
1271 .set_umac_addr = dwmac4_set_umac_addr,
1272 .get_umac_addr = dwmac4_get_umac_addr,
1273 .set_eee_mode = dwmac4_set_eee_mode,
1274 .reset_eee_mode = dwmac4_reset_eee_mode,
1275 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1276 .set_eee_timer = dwmac4_set_eee_timer,
1277 .set_eee_pls = dwmac4_set_eee_pls,
1278 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1279 .pcs_rane = dwmac4_rane,
1280 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1281 .debug = dwmac4_debug,
1282 .set_filter = dwmac4_set_filter,
1283 .safety_feat_config = dwmac5_safety_feat_config,
1284 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1285 .safety_feat_dump = dwmac5_safety_feat_dump,
1286 .rxp_config = dwmac5_rxp_config,
1287 .flex_pps_config = dwmac5_flex_pps_config,
1288 .set_mac_loopback = dwmac4_set_mac_loopback,
1289 .update_vlan_hash = dwmac4_update_vlan_hash,
1290 .sarc_configure = dwmac4_sarc_configure,
1291 .enable_vlan = dwmac4_enable_vlan,
1292 .set_arp_offload = dwmac4_set_arp_offload,
1293 .config_l3_filter = dwmac4_config_l3_filter,
1294 .config_l4_filter = dwmac4_config_l4_filter,
1295 .est_configure = dwmac5_est_configure,
1296 .fpe_configure = dwmac5_fpe_configure,
1297 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1298 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1299 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1300 };
1301
1302 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1303 {
1304 u32 val, num_vlan;
1305
1306 val = readl(ioaddr + GMAC_HW_FEATURE3);
1307 switch (val & GMAC_HW_FEAT_NRVF) {
1308 case 0:
1309 num_vlan = 1;
1310 break;
1311 case 1:
1312 num_vlan = 4;
1313 break;
1314 case 2:
1315 num_vlan = 8;
1316 break;
1317 case 3:
1318 num_vlan = 16;
1319 break;
1320 case 4:
1321 num_vlan = 24;
1322 break;
1323 case 5:
1324 num_vlan = 32;
1325 break;
1326 default:
1327 num_vlan = 1;
1328 }
1329
1330 return num_vlan;
1331 }
1332
1333 int dwmac4_setup(struct stmmac_priv *priv)
1334 {
1335 struct mac_device_info *mac = priv->hw;
1336
1337 dev_info(priv->device, "\tDWMAC4/5\n");
1338
1339 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1340 mac->pcsr = priv->ioaddr;
1341 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1342 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1343 mac->mcast_bits_log2 = 0;
1344
1345 if (mac->multicast_filter_bins)
1346 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1347
1348 mac->link.duplex = GMAC_CONFIG_DM;
1349 mac->link.speed10 = GMAC_CONFIG_PS;
1350 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1351 mac->link.speed1000 = 0;
1352 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1353 mac->mii.addr = GMAC_MDIO_ADDR;
1354 mac->mii.data = GMAC_MDIO_DATA;
1355 mac->mii.addr_shift = 21;
1356 mac->mii.addr_mask = GENMASK(25, 21);
1357 mac->mii.reg_shift = 16;
1358 mac->mii.reg_mask = GENMASK(20, 16);
1359 mac->mii.clk_csr_shift = 8;
1360 mac->mii.clk_csr_mask = GENMASK(11, 8);
1361 mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1362
1363 return 0;
1364 }
Linux with added FPC-III support