WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / stmicro / stmmac / dwxgmac2_dma.c
blob77308c5c5d2947dc71b9d495f1b24202f909fd52
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
5 */
7 #include <linux/iopoll.h>
8 #include "stmmac.h"
9 #include "dwxgmac2.h"
11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE);
15 /* DMA SW reset */
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
19 !(value & XGMAC_SWR), 0, 100000);
22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
23 struct stmmac_dma_cfg *dma_cfg, int atds)
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
27 if (dma_cfg->aal)
28 value |= XGMAC_AAL;
30 if (dma_cfg->eame)
31 value |= XGMAC_EAME;
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
36 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
37 struct stmmac_dma_cfg *dma_cfg, u32 chan)
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
41 if (dma_cfg->pblx8)
42 value |= XGMAC_PBLx8;
44 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
45 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
48 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
49 struct stmmac_dma_cfg *dma_cfg,
50 dma_addr_t phy, u32 chan)
52 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
53 u32 value;
55 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
56 value &= ~XGMAC_RxPBL;
57 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
58 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
60 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
61 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
64 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
65 struct stmmac_dma_cfg *dma_cfg,
66 dma_addr_t phy, u32 chan)
68 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
69 u32 value;
71 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
72 value &= ~XGMAC_TxPBL;
73 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
74 value |= XGMAC_OSP;
75 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
77 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
78 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
81 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
83 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
84 int i;
86 if (axi->axi_lpi_en)
87 value |= XGMAC_EN_LPI;
88 if (axi->axi_xit_frm)
89 value |= XGMAC_LPI_XIT_PKT;
91 value &= ~XGMAC_WR_OSR_LMT;
92 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
93 XGMAC_WR_OSR_LMT;
95 value &= ~XGMAC_RD_OSR_LMT;
96 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
97 XGMAC_RD_OSR_LMT;
99 if (!axi->axi_fb)
100 value |= XGMAC_UNDEF;
102 value &= ~XGMAC_BLEN;
103 for (i = 0; i < AXI_BLEN; i++) {
104 switch (axi->axi_blen[i]) {
105 case 256:
106 value |= XGMAC_BLEN256;
107 break;
108 case 128:
109 value |= XGMAC_BLEN128;
110 break;
111 case 64:
112 value |= XGMAC_BLEN64;
113 break;
114 case 32:
115 value |= XGMAC_BLEN32;
116 break;
117 case 16:
118 value |= XGMAC_BLEN16;
119 break;
120 case 8:
121 value |= XGMAC_BLEN8;
122 break;
123 case 4:
124 value |= XGMAC_BLEN4;
125 break;
129 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
130 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
131 writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
134 static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space)
136 int i;
138 for (i = (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++)
139 reg_space[i] = readl(ioaddr + i * 4);
142 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
143 u32 channel, int fifosz, u8 qmode)
145 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
146 unsigned int rqs = fifosz / 256 - 1;
148 if (mode == SF_DMA_MODE) {
149 value |= XGMAC_RSF;
150 } else {
151 value &= ~XGMAC_RSF;
152 value &= ~XGMAC_RTC;
154 if (mode <= 64)
155 value |= 0x0 << XGMAC_RTC_SHIFT;
156 else if (mode <= 96)
157 value |= 0x2 << XGMAC_RTC_SHIFT;
158 else
159 value |= 0x3 << XGMAC_RTC_SHIFT;
162 value &= ~XGMAC_RQS;
163 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
165 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
166 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
167 unsigned int rfd, rfa;
169 value |= XGMAC_EHFC;
171 /* Set Threshold for Activating Flow Control to min 2 frames,
172 * i.e. 1500 * 2 = 3000 bytes.
174 * Set Threshold for Deactivating Flow Control to min 1 frame,
175 * i.e. 1500 bytes.
177 switch (fifosz) {
178 case 4096:
179 /* This violates the above formula because of FIFO size
180 * limit therefore overflow may occur in spite of this.
182 rfd = 0x03; /* Full-2.5K */
183 rfa = 0x01; /* Full-1.5K */
184 break;
186 default:
187 rfd = 0x07; /* Full-4.5K */
188 rfa = 0x04; /* Full-3K */
189 break;
192 flow &= ~XGMAC_RFD;
193 flow |= rfd << XGMAC_RFD_SHIFT;
195 flow &= ~XGMAC_RFA;
196 flow |= rfa << XGMAC_RFA_SHIFT;
198 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
201 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
203 /* Enable MTL RX overflow */
204 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
205 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
208 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
209 u32 channel, int fifosz, u8 qmode)
211 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
212 unsigned int tqs = fifosz / 256 - 1;
214 if (mode == SF_DMA_MODE) {
215 value |= XGMAC_TSF;
216 } else {
217 value &= ~XGMAC_TSF;
218 value &= ~XGMAC_TTC;
220 if (mode <= 64)
221 value |= 0x0 << XGMAC_TTC_SHIFT;
222 else if (mode <= 96)
223 value |= 0x2 << XGMAC_TTC_SHIFT;
224 else if (mode <= 128)
225 value |= 0x3 << XGMAC_TTC_SHIFT;
226 else if (mode <= 192)
227 value |= 0x4 << XGMAC_TTC_SHIFT;
228 else if (mode <= 256)
229 value |= 0x5 << XGMAC_TTC_SHIFT;
230 else if (mode <= 384)
231 value |= 0x6 << XGMAC_TTC_SHIFT;
232 else
233 value |= 0x7 << XGMAC_TTC_SHIFT;
236 /* Use static TC to Queue mapping */
237 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
239 value &= ~XGMAC_TXQEN;
240 if (qmode != MTL_QUEUE_AVB)
241 value |= 0x2 << XGMAC_TXQEN_SHIFT;
242 else
243 value |= 0x1 << XGMAC_TXQEN_SHIFT;
245 value &= ~XGMAC_TQS;
246 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
248 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
251 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan,
252 bool rx, bool tx)
254 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
256 if (rx)
257 value |= XGMAC_DMA_INT_DEFAULT_RX;
258 if (tx)
259 value |= XGMAC_DMA_INT_DEFAULT_TX;
261 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
264 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan,
265 bool rx, bool tx)
267 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
269 if (rx)
270 value &= ~XGMAC_DMA_INT_DEFAULT_RX;
271 if (tx)
272 value &= ~XGMAC_DMA_INT_DEFAULT_TX;
274 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
277 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
279 u32 value;
281 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
282 value |= XGMAC_TXST;
283 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
285 value = readl(ioaddr + XGMAC_TX_CONFIG);
286 value |= XGMAC_CONFIG_TE;
287 writel(value, ioaddr + XGMAC_TX_CONFIG);
290 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
292 u32 value;
294 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
295 value &= ~XGMAC_TXST;
296 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
298 value = readl(ioaddr + XGMAC_TX_CONFIG);
299 value &= ~XGMAC_CONFIG_TE;
300 writel(value, ioaddr + XGMAC_TX_CONFIG);
303 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
305 u32 value;
307 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
308 value |= XGMAC_RXST;
309 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
311 value = readl(ioaddr + XGMAC_RX_CONFIG);
312 value |= XGMAC_CONFIG_RE;
313 writel(value, ioaddr + XGMAC_RX_CONFIG);
316 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
318 u32 value;
320 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
321 value &= ~XGMAC_RXST;
322 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
325 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
326 struct stmmac_extra_stats *x, u32 chan)
328 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
329 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
330 int ret = 0;
332 /* ABNORMAL interrupts */
333 if (unlikely(intr_status & XGMAC_AIS)) {
334 if (unlikely(intr_status & XGMAC_RBU)) {
335 x->rx_buf_unav_irq++;
336 ret |= handle_rx;
338 if (unlikely(intr_status & XGMAC_TPS)) {
339 x->tx_process_stopped_irq++;
340 ret |= tx_hard_error;
342 if (unlikely(intr_status & XGMAC_FBE)) {
343 x->fatal_bus_error_irq++;
344 ret |= tx_hard_error;
348 /* TX/RX NORMAL interrupts */
349 if (likely(intr_status & XGMAC_NIS)) {
350 x->normal_irq_n++;
352 if (likely(intr_status & XGMAC_RI)) {
353 x->rx_normal_irq_n++;
354 ret |= handle_rx;
356 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
357 x->tx_normal_irq_n++;
358 ret |= handle_tx;
362 /* Clear interrupts */
363 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
365 return ret;
368 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
369 struct dma_features *dma_cap)
371 u32 hw_cap;
373 /* MAC HW feature 0 */
374 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
375 dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27;
376 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
377 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
378 dma_cap->eee = (hw_cap & XGMAC_HWFEAT_EEESEL) >> 13;
379 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
380 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
381 dma_cap->av &= !((hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10);
382 dma_cap->arpoffsel = (hw_cap & XGMAC_HWFEAT_ARPOFFSEL) >> 9;
383 dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
384 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
385 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
386 dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4;
387 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
389 /* MAC HW feature 1 */
390 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
391 dma_cap->l3l4fnum = (hw_cap & XGMAC_HWFEAT_L3L4FNUM) >> 27;
392 dma_cap->hash_tb_sz = (hw_cap & XGMAC_HWFEAT_HASHTBLSZ) >> 24;
393 dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20;
394 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
395 dma_cap->sphen = (hw_cap & XGMAC_HWFEAT_SPHEN) >> 17;
397 dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
398 switch (dma_cap->addr64) {
399 case 0:
400 dma_cap->addr64 = 32;
401 break;
402 case 1:
403 dma_cap->addr64 = 40;
404 break;
405 case 2:
406 dma_cap->addr64 = 48;
407 break;
408 default:
409 dma_cap->addr64 = 32;
410 break;
413 dma_cap->tx_fifo_size =
414 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
415 dma_cap->rx_fifo_size =
416 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
418 /* MAC HW feature 2 */
419 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
420 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
421 dma_cap->number_tx_channel =
422 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
423 dma_cap->number_rx_channel =
424 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
425 dma_cap->number_tx_queues =
426 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
427 dma_cap->number_rx_queues =
428 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
430 /* MAC HW feature 3 */
431 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
432 dma_cap->tbssel = (hw_cap & XGMAC_HWFEAT_TBSSEL) >> 27;
433 dma_cap->fpesel = (hw_cap & XGMAC_HWFEAT_FPESEL) >> 26;
434 dma_cap->estwid = (hw_cap & XGMAC_HWFEAT_ESTWID) >> 23;
435 dma_cap->estdep = (hw_cap & XGMAC_HWFEAT_ESTDEP) >> 20;
436 dma_cap->estsel = (hw_cap & XGMAC_HWFEAT_ESTSEL) >> 19;
437 dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
438 dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13;
439 dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11;
440 dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9;
441 dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3;
444 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
446 u32 i;
448 for (i = 0; i < nchan; i++)
449 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
452 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
454 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
457 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
459 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
462 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
464 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
467 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
469 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
472 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
474 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
476 if (en)
477 value |= XGMAC_TSE;
478 else
479 value &= ~XGMAC_TSE;
481 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
484 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
486 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
487 u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);
489 value &= ~XGMAC_TXQEN;
490 if (qmode != MTL_QUEUE_AVB) {
491 value |= 0x2 << XGMAC_TXQEN_SHIFT;
492 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
493 } else {
494 value |= 0x1 << XGMAC_TXQEN_SHIFT;
495 writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
498 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
501 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
503 u32 value;
505 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
506 value &= ~XGMAC_RBSZ;
507 value |= bfsize << XGMAC_RBSZ_SHIFT;
508 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
511 static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
513 u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
515 value &= ~XGMAC_CONFIG_HDSMS;
516 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
517 writel(value, ioaddr + XGMAC_RX_CONFIG);
519 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
520 if (en)
521 value |= XGMAC_SPH;
522 else
523 value &= ~XGMAC_SPH;
524 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
527 static int dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
529 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
531 if (en)
532 value |= XGMAC_EDSE;
533 else
534 value &= ~XGMAC_EDSE;
536 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
538 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;
539 if (en && !value)
540 return -EIO;
542 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);
543 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);
544 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);
545 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);
546 return 0;
549 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
550 .reset = dwxgmac2_dma_reset,
551 .init = dwxgmac2_dma_init,
552 .init_chan = dwxgmac2_dma_init_chan,
553 .init_rx_chan = dwxgmac2_dma_init_rx_chan,
554 .init_tx_chan = dwxgmac2_dma_init_tx_chan,
555 .axi = dwxgmac2_dma_axi,
556 .dump_regs = dwxgmac2_dma_dump_regs,
557 .dma_rx_mode = dwxgmac2_dma_rx_mode,
558 .dma_tx_mode = dwxgmac2_dma_tx_mode,
559 .enable_dma_irq = dwxgmac2_enable_dma_irq,
560 .disable_dma_irq = dwxgmac2_disable_dma_irq,
561 .start_tx = dwxgmac2_dma_start_tx,
562 .stop_tx = dwxgmac2_dma_stop_tx,
563 .start_rx = dwxgmac2_dma_start_rx,
564 .stop_rx = dwxgmac2_dma_stop_rx,
565 .dma_interrupt = dwxgmac2_dma_interrupt,
566 .get_hw_feature = dwxgmac2_get_hw_feature,
567 .rx_watchdog = dwxgmac2_rx_watchdog,
568 .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
569 .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
570 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
571 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
572 .enable_tso = dwxgmac2_enable_tso,
573 .qmode = dwxgmac2_qmode,
574 .set_bfsize = dwxgmac2_set_bfsize,
575 .enable_sph = dwxgmac2_enable_sph,
576 .enable_tbs = dwxgmac2_enable_tbs,