drivers/net/ethernet/tehuti/tehuti.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Tehuti Networks(R) Network Driver
   4  * ethtool interface implementation
   5  * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
   6  */
   7
   8 /*
   9  * RX HW/SW interaction overview
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  * There are 2 types of RX communication channels between driver and NIC.
  12  * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
  13  * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
  14  * info about buffer's location, size and ID. An ID field is used to identify a
  15  * buffer when it's returned with data via RXD Fifo (see below)
  16  * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
  17  * filled by HW and is readen by SW. Each descriptor holds status and ID.
  18  * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
  19  * via dma moves it into host memory, builds new RXD descriptor with same ID,
  20  * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
  21  *
  22  * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
  23  * One holds 1.5K packets and another - 26K packets. Depending on incoming
  24  * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
  25  * filled with data, HW builds new RXD descriptor for it and push it into single
  26  * RXD Fifo.
  27  *
  28  * RX SW Data Structures
  29  * ~~~~~~~~~~~~~~~~~~~~~
  30  * skb db - used to keep track of all skbs owned by SW and their dma addresses.
  31  * For RX case, ownership lasts from allocating new empty skb for RXF until
  32  * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
  33  * skb db. Implemented as array with bitmask.
  34  * fifo - keeps info about fifo's size and location, relevant HW registers,
  35  * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
  36  * Implemented as simple struct.
  37  *
  38  * RX SW Execution Flow
  39  * ~~~~~~~~~~~~~~~~~~~~
  40  * Upon initialization (ifconfig up) driver creates RX fifos and initializes
  41  * relevant registers. At the end of init phase, driver enables interrupts.
  42  * NIC sees that there is no RXF buffers and raises
  43  * RD_INTR interrupt, isr fills skbs and Rx begins.
  44  * Driver has two receive operation modes:
  45  *    NAPI - interrupt-driven mixed with polling
  46  *    interrupt-driven only
  47  *
  48  * Interrupt-driven only flow is following. When buffer is ready, HW raises
  49  * interrupt and isr is called. isr collects all available packets
  50  * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
  51
  52  * Rx buffer allocation note
  53  * ~~~~~~~~~~~~~~~~~~~~~~~~~
  54  * Driver cares to feed such amount of RxF descriptors that respective amount of
  55  * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
  56  * overflow check in Bordeaux for RxD fifo free/used size.
  57  * FIXME: this is NOT fully implemented, more work should be done
  58  *
  59  */
  60
  61 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  62
  63 #include "tehuti.h"
  64
  65 static const struct pci_device_id bdx_pci_tbl[] = {
  66         { PCI_VDEVICE(TEHUTI, 0x3009), },
  67         { PCI_VDEVICE(TEHUTI, 0x3010), },
  68         { PCI_VDEVICE(TEHUTI, 0x3014), },
  69         { 0 }
  70 };
  71
  72 MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
  73
  74 /* Definitions needed by ISR or NAPI functions */
  75 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
  76 static void bdx_tx_cleanup(struct bdx_priv *priv);
  77 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
  78
  79 /* Definitions needed by FW loading */
  80 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
  81
  82 /* Definitions needed by hw_start */
  83 static int bdx_tx_init(struct bdx_priv *priv);
  84 static int bdx_rx_init(struct bdx_priv *priv);
  85
  86 /* Definitions needed by bdx_close */
  87 static void bdx_rx_free(struct bdx_priv *priv);
  88 static void bdx_tx_free(struct bdx_priv *priv);
  89
  90 /* Definitions needed by bdx_probe */
  91 static void bdx_set_ethtool_ops(struct net_device *netdev);
  92
  93 /*************************************************************************
  94  *    Print Info                                                         *
  95  *************************************************************************/
  96
  97 static void print_hw_id(struct pci_dev *pdev)
  98 {
  99         struct pci_nic *nic = pci_get_drvdata(pdev);
 100         u16 pci_link_status = 0;
 101         u16 pci_ctrl = 0;
 102
 103         pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
 104         pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
 105
 106         pr_info("%s%s\n", BDX_NIC_NAME,
 107                 nic->port_num == 1 ? "" : ", 2-Port");
 108         pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
 109                 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
 110                 readl(nic->regs + FPGA_SEED),
 111                 GET_LINK_STATUS_LANES(pci_link_status),
 112                 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
 113 }
 114
 115 static void print_fw_id(struct pci_nic *nic)
 116 {
 117         pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
 118 }
 119
 120 static void print_eth_id(struct net_device *ndev)
 121 {
 122         netdev_info(ndev, "%s, Port %c\n",
 123                     BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
 124
 125 }
 126
 127 /*************************************************************************
 128  *    Code                                                               *
 129  *************************************************************************/
 130
 131 #define bdx_enable_interrupts(priv)     \
 132         do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
 133 #define bdx_disable_interrupts(priv)    \
 134         do { WRITE_REG(priv, regIMR, 0); } while (0)
 135
 136 /**
 137  * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication.
 138  * @priv: NIC private structure
 139  * @f: fifo to initialize
 140  * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
 141  * @reg_CFG0: offsets of registers relative to base address
 142  * @reg_CFG1: offsets of registers relative to base address
 143  * @reg_RPTR: offsets of registers relative to base address
 144  * @reg_WPTR: offsets of registers relative to base address
 145  *
 146  * 1K extra space is allocated at the end of the fifo to simplify
 147  * processing of descriptors that wraps around fifo's end
 148  *
 149  * Returns 0 on success, negative value on failure
 150  *
 151  */
 152 static int
 153 bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
 154               u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
 155 {
 156         u16 memsz = FIFO_SIZE * (1 << fsz_type);
 157
 158         memset(f, 0, sizeof(struct fifo));
 159         /* dma_alloc_coherent gives us 4k-aligned memory */
 160         f->va = dma_alloc_coherent(&priv->pdev->dev, memsz + FIFO_EXTRA_SPACE,
 161                                    &f->da, GFP_ATOMIC);
 162         if (!f->va) {
 163                 pr_err("dma_alloc_coherent failed\n");
 164                 RET(-ENOMEM);
 165         }
 166         f->reg_CFG0 = reg_CFG0;
 167         f->reg_CFG1 = reg_CFG1;
 168         f->reg_RPTR = reg_RPTR;
 169         f->reg_WPTR = reg_WPTR;
 170         f->rptr = 0;
 171         f->wptr = 0;
 172         f->memsz = memsz;
 173         f->size_mask = memsz - 1;
 174         WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
 175         WRITE_REG(priv, reg_CFG1, H32_64(f->da));
 176
 177         RET(0);
 178 }
 179
 180 /**
 181  * bdx_fifo_free - free all resources used by fifo
 182  * @priv: NIC private structure
 183  * @f: fifo to release
 184  */
 185 static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
 186 {
 187         ENTER;
 188         if (f->va) {
 189                 dma_free_coherent(&priv->pdev->dev,
 190                                   f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
 191                 f->va = NULL;
 192         }
 193         RET();
 194 }
 195
 196 /**
 197  * bdx_link_changed - notifies OS about hw link state.
 198  * @priv: hw adapter structure
 199  */
 200 static void bdx_link_changed(struct bdx_priv *priv)
 201 {
 202         u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
 203
 204         if (!link) {
 205                 if (netif_carrier_ok(priv->ndev)) {
 206                         netif_stop_queue(priv->ndev);
 207                         netif_carrier_off(priv->ndev);
 208                         netdev_err(priv->ndev, "Link Down\n");
 209                 }
 210         } else {
 211                 if (!netif_carrier_ok(priv->ndev)) {
 212                         netif_wake_queue(priv->ndev);
 213                         netif_carrier_on(priv->ndev);
 214                         netdev_err(priv->ndev, "Link Up\n");
 215                 }
 216         }
 217 }
 218
 219 static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
 220 {
 221         if (isr & IR_RX_FREE_0) {
 222                 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
 223                 DBG("RX_FREE_0\n");
 224         }
 225
 226         if (isr & IR_LNKCHG0)
 227                 bdx_link_changed(priv);
 228
 229         if (isr & IR_PCIE_LINK)
 230                 netdev_err(priv->ndev, "PCI-E Link Fault\n");
 231
 232         if (isr & IR_PCIE_TOUT)
 233                 netdev_err(priv->ndev, "PCI-E Time Out\n");
 234
 235 }
 236
 237 /**
 238  * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC
 239  * @irq: interrupt number
 240  * @dev: network device
 241  *
 242  * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
 243  *
 244  * It reads ISR register to know interrupt reasons, and proceed them one by one.
 245  * Reasons of interest are:
 246  *    RX_DESC - new packet has arrived and RXD fifo holds its descriptor
 247  *    RX_FREE - number of free Rx buffers in RXF fifo gets low
 248  *    TX_FREE - packet was transmited and RXF fifo holds its descriptor
 249  */
 250
 251 static irqreturn_t bdx_isr_napi(int irq, void *dev)
 252 {
 253         struct net_device *ndev = dev;
 254         struct bdx_priv *priv = netdev_priv(ndev);
 255         u32 isr;
 256
 257         ENTER;
 258         isr = (READ_REG(priv, regISR) & IR_RUN);
 259         if (unlikely(!isr)) {
 260                 bdx_enable_interrupts(priv);
 261                 return IRQ_NONE;        /* Not our interrupt */
 262         }
 263
 264         if (isr & IR_EXTRA)
 265                 bdx_isr_extra(priv, isr);
 266
 267         if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
 268                 if (likely(napi_schedule_prep(&priv->napi))) {
 269                         __napi_schedule(&priv->napi);
 270                         RET(IRQ_HANDLED);
 271                 } else {
 272                         /* NOTE: we get here if intr has slipped into window
 273                          * between these lines in bdx_poll:
 274                          *    bdx_enable_interrupts(priv);
 275                          *    return 0;
 276                          * currently intrs are disabled (since we read ISR),
 277                          * and we have failed to register next poll.
 278                          * so we read the regs to trigger chip
 279                          * and allow further interupts. */
 280                         READ_REG(priv, regTXF_WPTR_0);
 281                         READ_REG(priv, regRXD_WPTR_0);
 282                 }
 283         }
 284
 285         bdx_enable_interrupts(priv);
 286         RET(IRQ_HANDLED);
 287 }
 288
 289 static int bdx_poll(struct napi_struct *napi, int budget)
 290 {
 291         struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
 292         int work_done;
 293
 294         ENTER;
 295         bdx_tx_cleanup(priv);
 296         work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
 297         if ((work_done < budget) ||
 298             (priv->napi_stop++ >= 30)) {
 299                 DBG("rx poll is done. backing to isr-driven\n");
 300
 301                 /* from time to time we exit to let NAPI layer release
 302                  * device lock and allow waiting tasks (eg rmmod) to advance) */
 303                 priv->napi_stop = 0;
 304
 305                 napi_complete_done(napi, work_done);
 306                 bdx_enable_interrupts(priv);
 307         }
 308         return work_done;
 309 }
 310
 311 /**
 312  * bdx_fw_load - loads firmware to NIC
 313  * @priv: NIC private structure
 314  *
 315  * Firmware is loaded via TXD fifo, so it must be initialized first.
 316  * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
 317  * can have few of them). So all drivers use semaphore register to choose one
 318  * that will actually load FW to NIC.
 319  */
 320
 321 static int bdx_fw_load(struct bdx_priv *priv)
 322 {
 323         const struct firmware *fw = NULL;
 324         int master, i;
 325         int rc;
 326
 327         ENTER;
 328         master = READ_REG(priv, regINIT_SEMAPHORE);
 329         if (!READ_REG(priv, regINIT_STATUS) && master) {
 330                 rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
 331                 if (rc)
 332                         goto out;
 333                 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
 334                 mdelay(100);
 335         }
 336         for (i = 0; i < 200; i++) {
 337                 if (READ_REG(priv, regINIT_STATUS)) {
 338                         rc = 0;
 339                         goto out;
 340                 }
 341                 mdelay(2);
 342         }
 343         rc = -EIO;
 344 out:
 345         if (master)
 346                 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
 347
 348         release_firmware(fw);
 349
 350         if (rc) {
 351                 netdev_err(priv->ndev, "firmware loading failed\n");
 352                 if (rc == -EIO)
 353                         DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
 354                             READ_REG(priv, regVPC),
 355                             READ_REG(priv, regVIC),
 356                             READ_REG(priv, regINIT_STATUS), i);
 357                 RET(rc);
 358         } else {
 359                 DBG("%s: firmware loading success\n", priv->ndev->name);
 360                 RET(0);
 361         }
 362 }
 363
 364 static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
 365 {
 366         u32 val;
 367
 368         ENTER;
 369         DBG("mac0=%x mac1=%x mac2=%x\n",
 370             READ_REG(priv, regUNC_MAC0_A),
 371             READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
 372
 373         val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
 374         WRITE_REG(priv, regUNC_MAC2_A, val);
 375         val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
 376         WRITE_REG(priv, regUNC_MAC1_A, val);
 377         val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
 378         WRITE_REG(priv, regUNC_MAC0_A, val);
 379
 380         DBG("mac0=%x mac1=%x mac2=%x\n",
 381             READ_REG(priv, regUNC_MAC0_A),
 382             READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
 383         RET();
 384 }
 385
 386 /**
 387  * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
 388  * @priv: NIC private structure
 389  */
 390 static int bdx_hw_start(struct bdx_priv *priv)
 391 {
 392         int rc = -EIO;
 393         struct net_device *ndev = priv->ndev;
 394
 395         ENTER;
 396         bdx_link_changed(priv);
 397
 398         /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
 399         WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
 400         WRITE_REG(priv, regPAUSE_QUANT, 0x96);
 401         WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
 402         WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
 403         WRITE_REG(priv, regRX_FULLNESS, 0);
 404         WRITE_REG(priv, regTX_FULLNESS, 0);
 405         WRITE_REG(priv, regCTRLST,
 406                   regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
 407
 408         WRITE_REG(priv, regVGLB, 0);
 409         WRITE_REG(priv, regMAX_FRAME_A,
 410                   priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
 411
 412         DBG("RDINTCM=%08x\n", priv->rdintcm);   /*NOTE: test script uses this */
 413         WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
 414         WRITE_REG(priv, regRDINTCM2, 0);        /*cpu_to_le32(rcm.val)); */
 415
 416         DBG("TDINTCM=%08x\n", priv->tdintcm);   /*NOTE: test script uses this */
 417         WRITE_REG(priv, regTDINTCM0, priv->tdintcm);    /* old val = 0x300064 */
 418
 419         /* Enable timer interrupt once in 2 secs. */
 420         /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
 421         bdx_restore_mac(priv->ndev, priv);
 422
 423         WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
 424                   GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
 425
 426 #define BDX_IRQ_TYPE    ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
 427
 428         rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
 429                          ndev->name, ndev);
 430         if (rc)
 431                 goto err_irq;
 432         bdx_enable_interrupts(priv);
 433
 434         RET(0);
 435
 436 err_irq:
 437         RET(rc);
 438 }
 439
 440 static void bdx_hw_stop(struct bdx_priv *priv)
 441 {
 442         ENTER;
 443         bdx_disable_interrupts(priv);
 444         free_irq(priv->pdev->irq, priv->ndev);
 445
 446         netif_carrier_off(priv->ndev);
 447         netif_stop_queue(priv->ndev);
 448
 449         RET();
 450 }
 451
 452 static int bdx_hw_reset_direct(void __iomem *regs)
 453 {
 454         u32 val, i;
 455         ENTER;
 456
 457         /* reset sequences: read, write 1, read, write 0 */
 458         val = readl(regs + regCLKPLL);
 459         writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
 460         udelay(50);
 461         val = readl(regs + regCLKPLL);
 462         writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
 463
 464         /* check that the PLLs are locked and reset ended */
 465         for (i = 0; i < 70; i++, mdelay(10))
 466                 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
 467                         /* do any PCI-E read transaction */
 468                         readl(regs + regRXD_CFG0_0);
 469                         return 0;
 470                 }
 471         pr_err("HW reset failed\n");
 472         return 1;               /* failure */
 473 }
 474
 475 static int bdx_hw_reset(struct bdx_priv *priv)
 476 {
 477         u32 val, i;
 478         ENTER;
 479
 480         if (priv->port == 0) {
 481                 /* reset sequences: read, write 1, read, write 0 */
 482                 val = READ_REG(priv, regCLKPLL);
 483                 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
 484                 udelay(50);
 485                 val = READ_REG(priv, regCLKPLL);
 486                 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
 487         }
 488         /* check that the PLLs are locked and reset ended */
 489         for (i = 0; i < 70; i++, mdelay(10))
 490                 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
 491                         /* do any PCI-E read transaction */
 492                         READ_REG(priv, regRXD_CFG0_0);
 493                         return 0;
 494                 }
 495         pr_err("HW reset failed\n");
 496         return 1;               /* failure */
 497 }
 498
 499 static int bdx_sw_reset(struct bdx_priv *priv)
 500 {
 501         int i;
 502
 503         ENTER;
 504         /* 1. load MAC (obsolete) */
 505         /* 2. disable Rx (and Tx) */
 506         WRITE_REG(priv, regGMAC_RXF_A, 0);
 507         mdelay(100);
 508         /* 3. disable port */
 509         WRITE_REG(priv, regDIS_PORT, 1);
 510         /* 4. disable queue */
 511         WRITE_REG(priv, regDIS_QU, 1);
 512         /* 5. wait until hw is disabled */
 513         for (i = 0; i < 50; i++) {
 514                 if (READ_REG(priv, regRST_PORT) & 1)
 515                         break;
 516                 mdelay(10);
 517         }
 518         if (i == 50)
 519                 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
 520
 521         /* 6. disable intrs */
 522         WRITE_REG(priv, regRDINTCM0, 0);
 523         WRITE_REG(priv, regTDINTCM0, 0);
 524         WRITE_REG(priv, regIMR, 0);
 525         READ_REG(priv, regISR);
 526
 527         /* 7. reset queue */
 528         WRITE_REG(priv, regRST_QU, 1);
 529         /* 8. reset port */
 530         WRITE_REG(priv, regRST_PORT, 1);
 531         /* 9. zero all read and write pointers */
 532         for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
 533                 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
 534         for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
 535                 WRITE_REG(priv, i, 0);
 536         /* 10. unseet port disable */
 537         WRITE_REG(priv, regDIS_PORT, 0);
 538         /* 11. unset queue disable */
 539         WRITE_REG(priv, regDIS_QU, 0);
 540         /* 12. unset queue reset */
 541         WRITE_REG(priv, regRST_QU, 0);
 542         /* 13. unset port reset */
 543         WRITE_REG(priv, regRST_PORT, 0);
 544         /* 14. enable Rx */
 545         /* skiped. will be done later */
 546         /* 15. save MAC (obsolete) */
 547         for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
 548                 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
 549
 550         RET(0);
 551 }
 552
 553 /* bdx_reset - performs right type of reset depending on hw type */
 554 static int bdx_reset(struct bdx_priv *priv)
 555 {
 556         ENTER;
 557         RET((priv->pdev->device == 0x3009)
 558             ? bdx_hw_reset(priv)
 559             : bdx_sw_reset(priv));
 560 }
 561
 562 /**
 563  * bdx_close - Disables a network interface
 564  * @ndev: network interface device structure
 565  *
 566  * Returns 0, this is not allowed to fail
 567  *
 568  * The close entry point is called when an interface is de-activated
 569  * by the OS.  The hardware is still under the drivers control, but
 570  * needs to be disabled.  A global MAC reset is issued to stop the
 571  * hardware, and all transmit and receive resources are freed.
 572  **/
 573 static int bdx_close(struct net_device *ndev)
 574 {
 575         struct bdx_priv *priv = NULL;
 576
 577         ENTER;
 578         priv = netdev_priv(ndev);
 579
 580         napi_disable(&priv->napi);
 581
 582         bdx_reset(priv);
 583         bdx_hw_stop(priv);
 584         bdx_rx_free(priv);
 585         bdx_tx_free(priv);
 586         RET(0);
 587 }
 588
 589 /**
 590  * bdx_open - Called when a network interface is made active
 591  * @ndev: network interface device structure
 592  *
 593  * Returns 0 on success, negative value on failure
 594  *
 595  * The open entry point is called when a network interface is made
 596  * active by the system (IFF_UP).  At this point all resources needed
 597  * for transmit and receive operations are allocated, the interrupt
 598  * handler is registered with the OS, the watchdog timer is started,
 599  * and the stack is notified that the interface is ready.
 600  **/
 601 static int bdx_open(struct net_device *ndev)
 602 {
 603         struct bdx_priv *priv;
 604         int rc;
 605
 606         ENTER;
 607         priv = netdev_priv(ndev);
 608         bdx_reset(priv);
 609         if (netif_running(ndev))
 610                 netif_stop_queue(priv->ndev);
 611
 612         if ((rc = bdx_tx_init(priv)) ||
 613             (rc = bdx_rx_init(priv)) ||
 614             (rc = bdx_fw_load(priv)))
 615                 goto err;
 616
 617         bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
 618
 619         rc = bdx_hw_start(priv);
 620         if (rc)
 621                 goto err;
 622
 623         napi_enable(&priv->napi);
 624
 625         print_fw_id(priv->nic);
 626
 627         RET(0);
 628
 629 err:
 630         bdx_close(ndev);
 631         RET(rc);
 632 }
 633
 634 static int bdx_range_check(struct bdx_priv *priv, u32 offset)
 635 {
 636         return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
 637                 -EINVAL : 0;
 638 }
 639
 640 static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
 641 {
 642         struct bdx_priv *priv = netdev_priv(ndev);
 643         u32 data[3];
 644         int error;
 645
 646         ENTER;
 647
 648         DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
 649         if (cmd != SIOCDEVPRIVATE) {
 650                 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
 651                 if (error) {
 652                         pr_err("can't copy from user\n");
 653                         RET(-EFAULT);
 654                 }
 655                 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
 656         } else {
 657                 return -EOPNOTSUPP;
 658         }
 659
 660         if (!capable(CAP_SYS_RAWIO))
 661                 return -EPERM;
 662
 663         switch (data[0]) {
 664
 665         case BDX_OP_READ:
 666                 error = bdx_range_check(priv, data[1]);
 667                 if (error < 0)
 668                         return error;
 669                 data[2] = READ_REG(priv, data[1]);
 670                 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
 671                     data[2]);
 672                 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
 673                 if (error)
 674                         RET(-EFAULT);
 675                 break;
 676
 677         case BDX_OP_WRITE:
 678                 error = bdx_range_check(priv, data[1]);
 679                 if (error < 0)
 680                         return error;
 681                 WRITE_REG(priv, data[1], data[2]);
 682                 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
 683                 break;
 684
 685         default:
 686                 RET(-EOPNOTSUPP);
 687         }
 688         return 0;
 689 }
 690
 691 static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
 692 {
 693         ENTER;
 694         if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
 695                 RET(bdx_ioctl_priv(ndev, ifr, cmd));
 696         else
 697                 RET(-EOPNOTSUPP);
 698 }
 699
 700 /**
 701  * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
 702  * @ndev: network device
 703  * @vid:  VLAN vid
 704  * @enable: enable or disable vlan
 705  *
 706  * Passes VLAN filter table to hardware
 707  */
 708 static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
 709 {
 710         struct bdx_priv *priv = netdev_priv(ndev);
 711         u32 reg, bit, val;
 712
 713         ENTER;
 714         DBG2("vid=%d value=%d\n", (int)vid, enable);
 715         if (unlikely(vid >= 4096)) {
 716                 pr_err("invalid VID: %u (> 4096)\n", vid);
 717                 RET();
 718         }
 719         reg = regVLAN_0 + (vid / 32) * 4;
 720         bit = 1 << vid % 32;
 721         val = READ_REG(priv, reg);
 722         DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
 723         if (enable)
 724                 val |= bit;
 725         else
 726                 val &= ~bit;
 727         DBG2("new val %x\n", val);
 728         WRITE_REG(priv, reg, val);
 729         RET();
 730 }
 731
 732 /**
 733  * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
 734  * @ndev: network device
 735  * @proto: unused
 736  * @vid:  VLAN vid to add
 737  */
 738 static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
 739 {
 740         __bdx_vlan_rx_vid(ndev, vid, 1);
 741         return 0;
 742 }
 743
 744 /**
 745  * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
 746  * @ndev: network device
 747  * @proto: unused
 748  * @vid:  VLAN vid to kill
 749  */
 750 static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
 751 {
 752         __bdx_vlan_rx_vid(ndev, vid, 0);
 753         return 0;
 754 }
 755
 756 /**
 757  * bdx_change_mtu - Change the Maximum Transfer Unit
 758  * @ndev: network interface device structure
 759  * @new_mtu: new value for maximum frame size
 760  *
 761  * Returns 0 on success, negative on failure
 762  */
 763 static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
 764 {
 765         ENTER;
 766
 767         ndev->mtu = new_mtu;
 768         if (netif_running(ndev)) {
 769                 bdx_close(ndev);
 770                 bdx_open(ndev);
 771         }
 772         RET(0);
 773 }
 774
 775 static void bdx_setmulti(struct net_device *ndev)
 776 {
 777         struct bdx_priv *priv = netdev_priv(ndev);
 778
 779         u32 rxf_val =
 780             GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
 781         int i;
 782
 783         ENTER;
 784         /* IMF - imperfect (hash) rx multicat filter */
 785         /* PMF - perfect rx multicat filter */
 786
 787         /* FIXME: RXE(OFF) */
 788         if (ndev->flags & IFF_PROMISC) {
 789                 rxf_val |= GMAC_RX_FILTER_PRM;
 790         } else if (ndev->flags & IFF_ALLMULTI) {
 791                 /* set IMF to accept all multicast frmaes */
 792                 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
 793                         WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
 794         } else if (!netdev_mc_empty(ndev)) {
 795                 u8 hash;
 796                 struct netdev_hw_addr *ha;
 797                 u32 reg, val;
 798
 799                 /* set IMF to deny all multicast frames */
 800                 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
 801                         WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
 802                 /* set PMF to deny all multicast frames */
 803                 for (i = 0; i < MAC_MCST_NUM; i++) {
 804                         WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
 805                         WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
 806                 }
 807
 808                 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
 809                 /* TBD: sort addresses and write them in ascending order
 810                  * into RX_MAC_MCST regs. we skip this phase now and accept ALL
 811                  * multicast frames throu IMF */
 812                 /* accept the rest of addresses throu IMF */
 813                 netdev_for_each_mc_addr(ha, ndev) {
 814                         hash = 0;
 815                         for (i = 0; i < ETH_ALEN; i++)
 816                                 hash ^= ha->addr[i];
 817                         reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
 818                         val = READ_REG(priv, reg);
 819                         val |= (1 << (hash % 32));
 820                         WRITE_REG(priv, reg, val);
 821                 }
 822
 823         } else {
 824                 DBG("only own mac %d\n", netdev_mc_count(ndev));
 825                 rxf_val |= GMAC_RX_FILTER_AB;
 826         }
 827         WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
 828         /* enable RX */
 829         /* FIXME: RXE(ON) */
 830         RET();
 831 }
 832
 833 static int bdx_set_mac(struct net_device *ndev, void *p)
 834 {
 835         struct bdx_priv *priv = netdev_priv(ndev);
 836         struct sockaddr *addr = p;
 837
 838         ENTER;
 839         /*
 840            if (netif_running(dev))
 841            return -EBUSY
 842          */
 843         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
 844         bdx_restore_mac(ndev, priv);
 845         RET(0);
 846 }
 847
 848 static int bdx_read_mac(struct bdx_priv *priv)
 849 {
 850         u16 macAddress[3], i;
 851         ENTER;
 852
 853         macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
 854         macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
 855         macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
 856         macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
 857         macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
 858         macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
 859         for (i = 0; i < 3; i++) {
 860                 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
 861                 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
 862         }
 863         RET(0);
 864 }
 865
 866 static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
 867 {
 868         u64 val;
 869
 870         val = READ_REG(priv, reg);
 871         val |= ((u64) READ_REG(priv, reg + 8)) << 32;
 872         return val;
 873 }
 874
 875 /*Do the statistics-update work*/
 876 static void bdx_update_stats(struct bdx_priv *priv)
 877 {
 878         struct bdx_stats *stats = &priv->hw_stats;
 879         u64 *stats_vector = (u64 *) stats;
 880         int i;
 881         int addr;
 882
 883         /*Fill HW structure */
 884         addr = 0x7200;
 885         /*First 12 statistics - 0x7200 - 0x72B0 */
 886         for (i = 0; i < 12; i++) {
 887                 stats_vector[i] = bdx_read_l2stat(priv, addr);
 888                 addr += 0x10;
 889         }
 890         BDX_ASSERT(addr != 0x72C0);
 891         /* 0x72C0-0x72E0 RSRV */
 892         addr = 0x72F0;
 893         for (; i < 16; i++) {
 894                 stats_vector[i] = bdx_read_l2stat(priv, addr);
 895                 addr += 0x10;
 896         }
 897         BDX_ASSERT(addr != 0x7330);
 898         /* 0x7330-0x7360 RSRV */
 899         addr = 0x7370;
 900         for (; i < 19; i++) {
 901                 stats_vector[i] = bdx_read_l2stat(priv, addr);
 902                 addr += 0x10;
 903         }
 904         BDX_ASSERT(addr != 0x73A0);
 905         /* 0x73A0-0x73B0 RSRV */
 906         addr = 0x73C0;
 907         for (; i < 23; i++) {
 908                 stats_vector[i] = bdx_read_l2stat(priv, addr);
 909                 addr += 0x10;
 910         }
 911         BDX_ASSERT(addr != 0x7400);
 912         BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
 913 }
 914
 915 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
 916                        u16 rxd_vlan);
 917 static void print_rxfd(struct rxf_desc *rxfd);
 918
 919 /*************************************************************************
 920  *     Rx DB                                                             *
 921  *************************************************************************/
 922
 923 static void bdx_rxdb_destroy(struct rxdb *db)
 924 {
 925         vfree(db);
 926 }
 927
 928 static struct rxdb *bdx_rxdb_create(int nelem)
 929 {
 930         struct rxdb *db;
 931         int i;
 932
 933         db = vmalloc(sizeof(struct rxdb)
 934                      + (nelem * sizeof(int))
 935                      + (nelem * sizeof(struct rx_map)));
 936         if (likely(db != NULL)) {
 937                 db->stack = (int *)(db + 1);
 938                 db->elems = (void *)(db->stack + nelem);
 939                 db->nelem = nelem;
 940                 db->top = nelem;
 941                 for (i = 0; i < nelem; i++)
 942                         db->stack[i] = nelem - i - 1;   /* to make first allocs
 943                                                            close to db struct*/
 944         }
 945
 946         return db;
 947 }
 948
 949 static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
 950 {
 951         BDX_ASSERT(db->top <= 0);
 952         return db->stack[--(db->top)];
 953 }
 954
 955 static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
 956 {
 957         BDX_ASSERT((n < 0) || (n >= db->nelem));
 958         return db->elems + n;
 959 }
 960
 961 static inline int bdx_rxdb_available(struct rxdb *db)
 962 {
 963         return db->top;
 964 }
 965
 966 static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
 967 {
 968         BDX_ASSERT((n >= db->nelem) || (n < 0));
 969         db->stack[(db->top)++] = n;
 970 }
 971
 972 /*************************************************************************
 973  *     Rx Init                                                           *
 974  *************************************************************************/
 975
 976 /**
 977  * bdx_rx_init - initialize RX all related HW and SW resources
 978  * @priv: NIC private structure
 979  *
 980  * Returns 0 on success, negative value on failure
 981  *
 982  * It creates rxf and rxd fifos, update relevant HW registers, preallocate
 983  * skb for rx. It assumes that Rx is desabled in HW
 984  * funcs are grouped for better cache usage
 985  *
 986  * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
 987  * filled and packets will be dropped by nic without getting into host or
 988  * cousing interrupt. Anyway, in that condition, host has no chance to process
 989  * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
 990  */
 991
 992 /* TBD: ensure proper packet size */
 993
 994 static int bdx_rx_init(struct bdx_priv *priv)
 995 {
 996         ENTER;
 997
 998         if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
 999                           regRXD_CFG0_0, regRXD_CFG1_0,
1000                           regRXD_RPTR_0, regRXD_WPTR_0))
1001                 goto err_mem;
1002         if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1003                           regRXF_CFG0_0, regRXF_CFG1_0,
1004                           regRXF_RPTR_0, regRXF_WPTR_0))
1005                 goto err_mem;
1006         priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1007                                      sizeof(struct rxf_desc));
1008         if (!priv->rxdb)
1009                 goto err_mem;
1010
1011         priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1012         return 0;
1013
1014 err_mem:
1015         netdev_err(priv->ndev, "Rx init failed\n");
1016         return -ENOMEM;
1017 }
1018
1019 /**
1020  * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1021  * @priv: NIC private structure
1022  * @f: RXF fifo
1023  */
1024 static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1025 {
1026         struct rx_map *dm;
1027         struct rxdb *db = priv->rxdb;
1028         u16 i;
1029
1030         ENTER;
1031         DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1032             db->nelem - bdx_rxdb_available(db));
1033         while (bdx_rxdb_available(db) > 0) {
1034                 i = bdx_rxdb_alloc_elem(db);
1035                 dm = bdx_rxdb_addr_elem(db, i);
1036                 dm->dma = 0;
1037         }
1038         for (i = 0; i < db->nelem; i++) {
1039                 dm = bdx_rxdb_addr_elem(db, i);
1040                 if (dm->dma) {
1041                         dma_unmap_single(&priv->pdev->dev, dm->dma,
1042                                          f->m.pktsz, DMA_FROM_DEVICE);
1043                         dev_kfree_skb(dm->skb);
1044                 }
1045         }
1046 }
1047
1048 /**
1049  * bdx_rx_free - release all Rx resources
1050  * @priv: NIC private structure
1051  *
1052  * It assumes that Rx is desabled in HW
1053  */
1054 static void bdx_rx_free(struct bdx_priv *priv)
1055 {
1056         ENTER;
1057         if (priv->rxdb) {
1058                 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1059                 bdx_rxdb_destroy(priv->rxdb);
1060                 priv->rxdb = NULL;
1061         }
1062         bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1063         bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1064
1065         RET();
1066 }
1067
1068 /*************************************************************************
1069  *     Rx Engine                                                         *
1070  *************************************************************************/
1071
1072 /**
1073  * bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1074  * @priv: nic's private structure
1075  * @f: RXF fifo that needs skbs
1076  *
1077  * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1078  * skb's virtual and physical addresses are stored in skb db.
1079  * To calculate free space, func uses cached values of RPTR and WPTR
1080  * When needed, it also updates RPTR and WPTR.
1081  */
1082
1083 /* TBD: do not update WPTR if no desc were written */
1084
1085 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1086 {
1087         struct sk_buff *skb;
1088         struct rxf_desc *rxfd;
1089         struct rx_map *dm;
1090         int dno, delta, idx;
1091         struct rxdb *db = priv->rxdb;
1092
1093         ENTER;
1094         dno = bdx_rxdb_available(db) - 1;
1095         while (dno > 0) {
1096                 skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
1097                 if (!skb)
1098                         break;
1099
1100                 skb_reserve(skb, NET_IP_ALIGN);
1101
1102                 idx = bdx_rxdb_alloc_elem(db);
1103                 dm = bdx_rxdb_addr_elem(db, idx);
1104                 dm->dma = dma_map_single(&priv->pdev->dev, skb->data,
1105                                          f->m.pktsz, DMA_FROM_DEVICE);
1106                 dm->skb = skb;
1107                 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1108                 rxfd->info = CPU_CHIP_SWAP32(0x10003);  /* INFO=1 BC=3 */
1109                 rxfd->va_lo = idx;
1110                 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1111                 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1112                 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1113                 print_rxfd(rxfd);
1114
1115                 f->m.wptr += sizeof(struct rxf_desc);
1116                 delta = f->m.wptr - f->m.memsz;
1117                 if (unlikely(delta >= 0)) {
1118                         f->m.wptr = delta;
1119                         if (delta > 0) {
1120                                 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1121                                 DBG("wrapped descriptor\n");
1122                         }
1123                 }
1124                 dno--;
1125         }
1126         /*TBD: to do - delayed rxf wptr like in txd */
1127         WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1128         RET();
1129 }
1130
1131 static inline void
1132 NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1133              struct sk_buff *skb)
1134 {
1135         ENTER;
1136         DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
1137         if (GET_RXD_VTAG(rxd_val1)) {
1138                 DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
1139                     priv->ndev->name,
1140                     GET_RXD_VLAN_ID(rxd_vlan),
1141                     GET_RXD_VTAG(rxd_val1));
1142                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
1143         }
1144         netif_receive_skb(skb);
1145 }
1146
1147 static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1148 {
1149         struct rxf_desc *rxfd;
1150         struct rx_map *dm;
1151         struct rxf_fifo *f;
1152         struct rxdb *db;
1153         int delta;
1154
1155         ENTER;
1156         DBG("priv=%p rxdd=%p\n", priv, rxdd);
1157         f = &priv->rxf_fifo0;
1158         db = priv->rxdb;
1159         DBG("db=%p f=%p\n", db, f);
1160         dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1161         DBG("dm=%p\n", dm);
1162         rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1163         rxfd->info = CPU_CHIP_SWAP32(0x10003);  /* INFO=1 BC=3 */
1164         rxfd->va_lo = rxdd->va_lo;
1165         rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1166         rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1167         rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1168         print_rxfd(rxfd);
1169
1170         f->m.wptr += sizeof(struct rxf_desc);
1171         delta = f->m.wptr - f->m.memsz;
1172         if (unlikely(delta >= 0)) {
1173                 f->m.wptr = delta;
1174                 if (delta > 0) {
1175                         memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1176                         DBG("wrapped descriptor\n");
1177                 }
1178         }
1179         RET();
1180 }
1181
1182 /**
1183  * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS
1184  * NOTE: a special treatment is given to non-continuous descriptors
1185  * that start near the end, wraps around and continue at the beginning. a second
1186  * part is copied right after the first, and then descriptor is interpreted as
1187  * normal. fifo has an extra space to allow such operations
1188  * @priv: nic's private structure
1189  * @f: RXF fifo that needs skbs
1190  * @budget: maximum number of packets to receive
1191  */
1192
1193 /* TBD: replace memcpy func call by explicite inline asm */
1194
1195 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1196 {
1197         struct net_device *ndev = priv->ndev;
1198         struct sk_buff *skb, *skb2;
1199         struct rxd_desc *rxdd;
1200         struct rx_map *dm;
1201         struct rxf_fifo *rxf_fifo;
1202         int tmp_len, size;
1203         int done = 0;
1204         int max_done = BDX_MAX_RX_DONE;
1205         struct rxdb *db = NULL;
1206         /* Unmarshalled descriptor - copy of descriptor in host order */
1207         u32 rxd_val1;
1208         u16 len;
1209         u16 rxd_vlan;
1210
1211         ENTER;
1212         max_done = budget;
1213
1214         f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1215
1216         size = f->m.wptr - f->m.rptr;
1217         if (size < 0)
1218                 size = f->m.memsz + size;       /* size is negative :-) */
1219
1220         while (size > 0) {
1221
1222                 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1223                 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1224
1225                 len = CPU_CHIP_SWAP16(rxdd->len);
1226
1227                 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1228
1229                 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1230
1231                 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1232                 BDX_ASSERT(tmp_len <= 0);
1233                 size -= tmp_len;
1234                 if (size < 0)   /* test for partially arrived descriptor */
1235                         break;
1236
1237                 f->m.rptr += tmp_len;
1238
1239                 tmp_len = f->m.rptr - f->m.memsz;
1240                 if (unlikely(tmp_len >= 0)) {
1241                         f->m.rptr = tmp_len;
1242                         if (tmp_len > 0) {
1243                                 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1244                                     f->m.rptr, tmp_len);
1245                                 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1246                         }
1247                 }
1248
1249                 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1250                         DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1251                         ndev->stats.rx_errors++;
1252                         bdx_recycle_skb(priv, rxdd);
1253                         continue;
1254                 }
1255
1256                 rxf_fifo = &priv->rxf_fifo0;
1257                 db = priv->rxdb;
1258                 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1259                 skb = dm->skb;
1260
1261                 if (len < BDX_COPYBREAK &&
1262                     (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
1263                         skb_reserve(skb2, NET_IP_ALIGN);
1264                         /*skb_put(skb2, len); */
1265                         dma_sync_single_for_cpu(&priv->pdev->dev, dm->dma,
1266                                                 rxf_fifo->m.pktsz,
1267                                                 DMA_FROM_DEVICE);
1268                         memcpy(skb2->data, skb->data, len);
1269                         bdx_recycle_skb(priv, rxdd);
1270                         skb = skb2;
1271                 } else {
1272                         dma_unmap_single(&priv->pdev->dev, dm->dma,
1273                                          rxf_fifo->m.pktsz, DMA_FROM_DEVICE);
1274                         bdx_rxdb_free_elem(db, rxdd->va_lo);
1275                 }
1276
1277                 ndev->stats.rx_bytes += len;
1278
1279                 skb_put(skb, len);
1280                 skb->protocol = eth_type_trans(skb, ndev);
1281
1282                 /* Non-IP packets aren't checksum-offloaded */
1283                 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1284                         skb_checksum_none_assert(skb);
1285                 else
1286                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1287
1288                 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1289
1290                 if (++done >= max_done)
1291                         break;
1292         }
1293
1294         ndev->stats.rx_packets += done;
1295
1296         /* FIXME: do smth to minimize pci accesses    */
1297         WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1298
1299         bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1300
1301         RET(done);
1302 }
1303
1304 /*************************************************************************
1305  * Debug / Temprorary Code                                               *
1306  *************************************************************************/
1307 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1308                        u16 rxd_vlan)
1309 {
1310         DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1311             GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1312             GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1313             GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1314             GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1315             GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1316             rxdd->va_hi);
1317 }
1318
1319 static void print_rxfd(struct rxf_desc *rxfd)
1320 {
1321         DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
1322             "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1323             rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1324 }
1325
1326 /*
1327  * TX HW/SW interaction overview
1328  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1329  * There are 2 types of TX communication channels between driver and NIC.
1330  * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1331  * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1332  *
1333  * Currently NIC supports TSO, checksuming and gather DMA
1334  * UFO and IP fragmentation is on the way
1335  *
1336  * RX SW Data Structures
1337  * ~~~~~~~~~~~~~~~~~~~~~
1338  * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1339  * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1340  * acknowledges sent by TXF descriptors.
1341  * Implemented as cyclic buffer.
1342  * fifo - keeps info about fifo's size and location, relevant HW registers,
1343  * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1344  * Implemented as simple struct.
1345  *
1346  * TX SW Execution Flow
1347  * ~~~~~~~~~~~~~~~~~~~~
1348  * OS calls driver's hard_xmit method with packet to sent.
1349  * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1350  * by updating TXD WPTR.
1351  * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1352  * To prevent TXD fifo overflow without reading HW registers every time,
1353  * SW deploys "tx level" technique.
1354  * Upon strart up, tx level is initialized to TXD fifo length.
1355  * For every sent packet, SW gets its TXD descriptor sizei
1356  * (from precalculated array) and substructs it from tx level.
1357  * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1358  * original TXD descriptor from txdb and adds it to tx level.
1359  * When Tx level drops under some predefined treshhold, the driver
1360  * stops the TX queue. When TX level rises above that level,
1361  * the tx queue is enabled again.
1362  *
1363  * This technique avoids eccessive reading of RPTR and WPTR registers.
1364  * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1365  */
1366
1367 /**
1368  * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap
1369  * @db: tx data base
1370  * @pptr: read or write pointer
1371  */
1372 static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1373 {
1374         BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1375
1376         BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1377                    *pptr != db->wptr);  /* or write pointer */
1378
1379         BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1380                    *pptr >= db->end);   /* in range */
1381
1382         ++*pptr;
1383         if (unlikely(*pptr == db->end))
1384                 *pptr = db->start;
1385 }
1386
1387 /**
1388  * bdx_tx_db_inc_rptr - increment read pointer
1389  * @db: tx data base
1390  */
1391 static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1392 {
1393         BDX_ASSERT(db->rptr == db->wptr);       /* can't read from empty db */
1394         __bdx_tx_db_ptr_next(db, &db->rptr);
1395 }
1396
1397 /**
1398  * bdx_tx_db_inc_wptr - increment write pointer
1399  * @db: tx data base
1400  */
1401 static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1402 {
1403         __bdx_tx_db_ptr_next(db, &db->wptr);
1404         BDX_ASSERT(db->rptr == db->wptr);       /* we can not get empty db as
1405                                                    a result of write */
1406 }
1407
1408 /**
1409  * bdx_tx_db_init - creates and initializes tx db
1410  * @d: tx data base
1411  * @sz_type: size of tx fifo
1412  *
1413  * Returns 0 on success, error code otherwise
1414  */
1415 static int bdx_tx_db_init(struct txdb *d, int sz_type)
1416 {
1417         int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1418
1419         d->start = vmalloc(memsz);
1420         if (!d->start)
1421                 return -ENOMEM;
1422
1423         /*
1424          * In order to differentiate between db is empty and db is full
1425          * states at least one element should always be empty in order to
1426          * avoid rptr == wptr which means db is empty
1427          */
1428         d->size = memsz / sizeof(struct tx_map) - 1;
1429         d->end = d->start + d->size + 1;        /* just after last element */
1430
1431         /* all dbs are created equally empty */
1432         d->rptr = d->start;
1433         d->wptr = d->start;
1434
1435         return 0;
1436 }
1437
1438 /**
1439  * bdx_tx_db_close - closes tx db and frees all memory
1440  * @d: tx data base
1441  */
1442 static void bdx_tx_db_close(struct txdb *d)
1443 {
1444         BDX_ASSERT(d == NULL);
1445
1446         vfree(d->start);
1447         d->start = NULL;
1448 }
1449
1450 /*************************************************************************
1451  *     Tx Engine                                                         *
1452  *************************************************************************/
1453
1454 /* sizes of tx desc (including padding if needed) as function
1455  * of skb's frag number */
1456 static struct {
1457         u16 bytes;
1458         u16 qwords;             /* qword = 64 bit */
1459 } txd_sizes[MAX_SKB_FRAGS + 1];
1460
1461 /**
1462  * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks
1463  * @priv: NIC private structure
1464  * @skb: socket buffer to map
1465  * @txdd: TX descriptor to use
1466  *
1467  * It makes dma mappings for skb's data blocks and writes them to PBL of
1468  * new tx descriptor. It also stores them in the tx db, so they could be
1469  * unmaped after data was sent. It is reponsibility of a caller to make
1470  * sure that there is enough space in the tx db. Last element holds pointer
1471  * to skb itself and marked with zero length
1472  */
1473 static inline void
1474 bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1475                struct txd_desc *txdd)
1476 {
1477         struct txdb *db = &priv->txdb;
1478         struct pbl *pbl = &txdd->pbl[0];
1479         int nr_frags = skb_shinfo(skb)->nr_frags;
1480         int i;
1481
1482         db->wptr->len = skb_headlen(skb);
1483         db->wptr->addr.dma = dma_map_single(&priv->pdev->dev, skb->data,
1484                                             db->wptr->len, DMA_TO_DEVICE);
1485         pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1486         pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1487         pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1488         DBG("=== pbl   len: 0x%x ================\n", pbl->len);
1489         DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1490         DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1491         bdx_tx_db_inc_wptr(db);
1492
1493         for (i = 0; i < nr_frags; i++) {
1494                 const skb_frag_t *frag;
1495
1496                 frag = &skb_shinfo(skb)->frags[i];
1497                 db->wptr->len = skb_frag_size(frag);
1498                 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
1499                                                       0, skb_frag_size(frag),
1500                                                       DMA_TO_DEVICE);
1501
1502                 pbl++;
1503                 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1504                 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1505                 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1506                 bdx_tx_db_inc_wptr(db);
1507         }
1508
1509         /* add skb clean up info. */
1510         db->wptr->len = -txd_sizes[nr_frags].bytes;
1511         db->wptr->addr.skb = skb;
1512         bdx_tx_db_inc_wptr(db);
1513 }
1514
1515 /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1516  * number of frags is used as index to fetch correct descriptors size,
1517  * instead of calculating it each time */
1518 static void __init init_txd_sizes(void)
1519 {
1520         int i, lwords;
1521
1522         /* 7 - is number of lwords in txd with one phys buffer
1523          * 3 - is number of lwords used for every additional phys buffer */
1524         for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1525                 lwords = 7 + (i * 3);
1526                 if (lwords & 1)
1527                         lwords++;       /* pad it with 1 lword */
1528                 txd_sizes[i].qwords = lwords >> 1;
1529                 txd_sizes[i].bytes = lwords << 2;
1530         }
1531 }
1532
1533 /* bdx_tx_init - initialize all Tx related stuff.
1534  * Namely, TXD and TXF fifos, database etc */
1535 static int bdx_tx_init(struct bdx_priv *priv)
1536 {
1537         if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1538                           regTXD_CFG0_0,
1539                           regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1540                 goto err_mem;
1541         if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1542                           regTXF_CFG0_0,
1543                           regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1544                 goto err_mem;
1545
1546         /* The TX db has to keep mappings for all packets sent (on TxD)
1547          * and not yet reclaimed (on TxF) */
1548         if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1549                 goto err_mem;
1550
1551         priv->tx_level = BDX_MAX_TX_LEVEL;
1552 #ifdef BDX_DELAY_WPTR
1553         priv->tx_update_mark = priv->tx_level - 1024;
1554 #endif
1555         return 0;
1556
1557 err_mem:
1558         netdev_err(priv->ndev, "Tx init failed\n");
1559         return -ENOMEM;
1560 }
1561
1562 /**
1563  * bdx_tx_space - calculates available space in TX fifo
1564  * @priv: NIC private structure
1565  *
1566  * Returns available space in TX fifo in bytes
1567  */
1568 static inline int bdx_tx_space(struct bdx_priv *priv)
1569 {
1570         struct txd_fifo *f = &priv->txd_fifo0;
1571         int fsize;
1572
1573         f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1574         fsize = f->m.rptr - f->m.wptr;
1575         if (fsize <= 0)
1576                 fsize = f->m.memsz + fsize;
1577         return fsize;
1578 }
1579
1580 /**
1581  * bdx_tx_transmit - send packet to NIC
1582  * @skb: packet to send
1583  * @ndev: network device assigned to NIC
1584  * Return codes:
1585  * o NETDEV_TX_OK everything ok.
1586  * o NETDEV_TX_BUSY Cannot transmit packet, try later
1587  *   Usually a bug, means queue start/stop flow control is broken in
1588  *   the driver. Note: the driver must NOT put the skb in its DMA ring.
1589  */
1590 static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1591                                    struct net_device *ndev)
1592 {
1593         struct bdx_priv *priv = netdev_priv(ndev);
1594         struct txd_fifo *f = &priv->txd_fifo0;
1595         int txd_checksum = 7;   /* full checksum */
1596         int txd_lgsnd = 0;
1597         int txd_vlan_id = 0;
1598         int txd_vtag = 0;
1599         int txd_mss = 0;
1600
1601         int nr_frags = skb_shinfo(skb)->nr_frags;
1602         struct txd_desc *txdd;
1603         int len;
1604         unsigned long flags;
1605
1606         ENTER;
1607         local_irq_save(flags);
1608         spin_lock(&priv->tx_lock);
1609
1610         /* build tx descriptor */
1611         BDX_ASSERT(f->m.wptr >= f->m.memsz);    /* started with valid wptr */
1612         txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1613         if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1614                 txd_checksum = 0;
1615
1616         if (skb_shinfo(skb)->gso_size) {
1617                 txd_mss = skb_shinfo(skb)->gso_size;
1618                 txd_lgsnd = 1;
1619                 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1620                     txd_mss);
1621         }
1622
1623         if (skb_vlan_tag_present(skb)) {
1624                 /*Cut VLAN ID to 12 bits */
1625                 txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
1626                 txd_vtag = 1;
1627         }
1628
1629         txdd->length = CPU_CHIP_SWAP16(skb->len);
1630         txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1631         txdd->txd_val1 =
1632             CPU_CHIP_SWAP32(TXD_W1_VAL
1633                             (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1634                              txd_lgsnd, txd_vlan_id));
1635         DBG("=== TxD desc =====================\n");
1636         DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1637         DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1638
1639         bdx_tx_map_skb(priv, skb, txdd);
1640
1641         /* increment TXD write pointer. In case of
1642            fifo wrapping copy reminder of the descriptor
1643            to the beginning */
1644         f->m.wptr += txd_sizes[nr_frags].bytes;
1645         len = f->m.wptr - f->m.memsz;
1646         if (unlikely(len >= 0)) {
1647                 f->m.wptr = len;
1648                 if (len > 0) {
1649                         BDX_ASSERT(len > f->m.memsz);
1650                         memcpy(f->m.va, f->m.va + f->m.memsz, len);
1651                 }
1652         }
1653         BDX_ASSERT(f->m.wptr >= f->m.memsz);    /* finished with valid wptr */
1654
1655         priv->tx_level -= txd_sizes[nr_frags].bytes;
1656         BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1657 #ifdef BDX_DELAY_WPTR
1658         if (priv->tx_level > priv->tx_update_mark) {
1659                 /* Force memory writes to complete before letting h/w
1660                    know there are new descriptors to fetch.
1661                    (might be needed on platforms like IA64)
1662                    wmb(); */
1663                 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1664         } else {
1665                 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1666                         priv->tx_noupd = 0;
1667                         WRITE_REG(priv, f->m.reg_WPTR,
1668                                   f->m.wptr & TXF_WPTR_WR_PTR);
1669                 }
1670         }
1671 #else
1672         /* Force memory writes to complete before letting h/w
1673            know there are new descriptors to fetch.
1674            (might be needed on platforms like IA64)
1675            wmb(); */
1676         WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1677
1678 #endif
1679 #ifdef BDX_LLTX
1680         netif_trans_update(ndev); /* NETIF_F_LLTX driver :( */
1681 #endif
1682         ndev->stats.tx_packets++;
1683         ndev->stats.tx_bytes += skb->len;
1684
1685         if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1686                 DBG("%s: %s: TX Q STOP level %d\n",
1687                     BDX_DRV_NAME, ndev->name, priv->tx_level);
1688                 netif_stop_queue(ndev);
1689         }
1690
1691         spin_unlock_irqrestore(&priv->tx_lock, flags);
1692         return NETDEV_TX_OK;
1693 }
1694
1695 /**
1696  * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1697  * @priv: bdx adapter
1698  *
1699  * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1700  * that those packets were sent
1701  */
1702 static void bdx_tx_cleanup(struct bdx_priv *priv)
1703 {
1704         struct txf_fifo *f = &priv->txf_fifo0;
1705         struct txdb *db = &priv->txdb;
1706         int tx_level = 0;
1707
1708         ENTER;
1709         f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1710         BDX_ASSERT(f->m.rptr >= f->m.memsz);    /* started with valid rptr */
1711
1712         while (f->m.wptr != f->m.rptr) {
1713                 f->m.rptr += BDX_TXF_DESC_SZ;
1714                 f->m.rptr &= f->m.size_mask;
1715
1716                 /* unmap all the fragments */
1717                 /* first has to come tx_maps containing dma */
1718                 BDX_ASSERT(db->rptr->len == 0);
1719                 do {
1720                         BDX_ASSERT(db->rptr->addr.dma == 0);
1721                         dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma,
1722                                        db->rptr->len, DMA_TO_DEVICE);
1723                         bdx_tx_db_inc_rptr(db);
1724                 } while (db->rptr->len > 0);
1725                 tx_level -= db->rptr->len;      /* '-' koz len is negative */
1726
1727                 /* now should come skb pointer - free it */
1728                 dev_consume_skb_irq(db->rptr->addr.skb);
1729                 bdx_tx_db_inc_rptr(db);
1730         }
1731
1732         /* let h/w know which TXF descriptors were cleaned */
1733         BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1734         WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1735
1736         /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1737          * we resume the transmission and use tx_lock to synchronize with xmit.*/
1738         spin_lock(&priv->tx_lock);
1739         priv->tx_level += tx_level;
1740         BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1741 #ifdef BDX_DELAY_WPTR
1742         if (priv->tx_noupd) {
1743                 priv->tx_noupd = 0;
1744                 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1745                           priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1746         }
1747 #endif
1748
1749         if (unlikely(netif_queue_stopped(priv->ndev) &&
1750                      netif_carrier_ok(priv->ndev) &&
1751                      (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1752                 DBG("%s: %s: TX Q WAKE level %d\n",
1753                     BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1754                 netif_wake_queue(priv->ndev);
1755         }
1756         spin_unlock(&priv->tx_lock);
1757 }
1758
1759 /**
1760  * bdx_tx_free_skbs - frees all skbs from TXD fifo.
1761  * @priv: NIC private structure
1762  *
1763  * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1764  */
1765 static void bdx_tx_free_skbs(struct bdx_priv *priv)
1766 {
1767         struct txdb *db = &priv->txdb;
1768
1769         ENTER;
1770         while (db->rptr != db->wptr) {
1771                 if (likely(db->rptr->len))
1772                         dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma,
1773                                        db->rptr->len, DMA_TO_DEVICE);
1774                 else
1775                         dev_kfree_skb(db->rptr->addr.skb);
1776                 bdx_tx_db_inc_rptr(db);
1777         }
1778         RET();
1779 }
1780
1781 /* bdx_tx_free - frees all Tx resources */
1782 static void bdx_tx_free(struct bdx_priv *priv)
1783 {
1784         ENTER;
1785         bdx_tx_free_skbs(priv);
1786         bdx_fifo_free(priv, &priv->txd_fifo0.m);
1787         bdx_fifo_free(priv, &priv->txf_fifo0.m);
1788         bdx_tx_db_close(&priv->txdb);
1789 }
1790
1791 /**
1792  * bdx_tx_push_desc - push descriptor to TxD fifo
1793  * @priv: NIC private structure
1794  * @data: desc's data
1795  * @size: desc's size
1796  *
1797  * Pushes desc to TxD fifo and overlaps it if needed.
1798  * NOTE: this func does not check for available space. this is responsibility
1799  *    of the caller. Neither does it check that data size is smaller than
1800  *    fifo size.
1801  */
1802 static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1803 {
1804         struct txd_fifo *f = &priv->txd_fifo0;
1805         int i = f->m.memsz - f->m.wptr;
1806
1807         if (size == 0)
1808                 return;
1809
1810         if (i > size) {
1811                 memcpy(f->m.va + f->m.wptr, data, size);
1812                 f->m.wptr += size;
1813         } else {
1814                 memcpy(f->m.va + f->m.wptr, data, i);
1815                 f->m.wptr = size - i;
1816                 memcpy(f->m.va, data + i, f->m.wptr);
1817         }
1818         WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1819 }
1820
1821 /**
1822  * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1823  * @priv: NIC private structure
1824  * @data: desc's data
1825  * @size: desc's size
1826  *
1827  * NOTE: this func does check for available space and, if necessary, waits for
1828  *   NIC to read existing data before writing new one.
1829  */
1830 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1831 {
1832         int timer = 0;
1833         ENTER;
1834
1835         while (size > 0) {
1836                 /* we substruct 8 because when fifo is full rptr == wptr
1837                    which also means that fifo is empty, we can understand
1838                    the difference, but could hw do the same ??? :) */
1839                 int avail = bdx_tx_space(priv) - 8;
1840                 if (avail <= 0) {
1841                         if (timer++ > 300) {    /* prevent endless loop */
1842                                 DBG("timeout while writing desc to TxD fifo\n");
1843                                 break;
1844                         }
1845                         udelay(50);     /* give hw a chance to clean fifo */
1846                         continue;
1847                 }
1848                 avail = min(avail, size);
1849                 DBG("about to push  %d bytes starting %p size %d\n", avail,
1850                     data, size);
1851                 bdx_tx_push_desc(priv, data, avail);
1852                 size -= avail;
1853                 data += avail;
1854         }
1855         RET();
1856 }
1857
1858 static const struct net_device_ops bdx_netdev_ops = {
1859         .ndo_open               = bdx_open,
1860         .ndo_stop               = bdx_close,
1861         .ndo_start_xmit         = bdx_tx_transmit,
1862         .ndo_validate_addr      = eth_validate_addr,
1863         .ndo_do_ioctl           = bdx_ioctl,
1864         .ndo_set_rx_mode        = bdx_setmulti,
1865         .ndo_change_mtu         = bdx_change_mtu,
1866         .ndo_set_mac_address    = bdx_set_mac,
1867         .ndo_vlan_rx_add_vid    = bdx_vlan_rx_add_vid,
1868         .ndo_vlan_rx_kill_vid   = bdx_vlan_rx_kill_vid,
1869 };
1870
1871 /**
1872  * bdx_probe - Device Initialization Routine
1873  * @pdev: PCI device information struct
1874  * @ent: entry in bdx_pci_tbl
1875  *
1876  * Returns 0 on success, negative on failure
1877  *
1878  * bdx_probe initializes an adapter identified by a pci_dev structure.
1879  * The OS initialization, configuring of the adapter private structure,
1880  * and a hardware reset occur.
1881  *
1882  * functions and their order used as explained in
1883  * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1884  *
1885  */
1886
1887 /* TBD: netif_msg should be checked and implemented. I disable it for now */
1888 static int
1889 bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1890 {
1891         struct net_device *ndev;
1892         struct bdx_priv *priv;
1893         int err, pci_using_dac, port;
1894         unsigned long pciaddr;
1895         u32 regionSize;
1896         struct pci_nic *nic;
1897
1898         ENTER;
1899
1900         nic = vmalloc(sizeof(*nic));
1901         if (!nic)
1902                 RET(-ENOMEM);
1903
1904     /************** pci *****************/
1905         err = pci_enable_device(pdev);
1906         if (err)                        /* it triggers interrupt, dunno why. */
1907                 goto err_pci;           /* it's not a problem though */
1908
1909         if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) &&
1910             !(err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)))) {
1911                 pci_using_dac = 1;
1912         } else {
1913                 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) ||
1914                     (err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
1915                         pr_err("No usable DMA configuration, aborting\n");
1916                         goto err_dma;
1917                 }
1918                 pci_using_dac = 0;
1919         }
1920
1921         err = pci_request_regions(pdev, BDX_DRV_NAME);
1922         if (err)
1923                 goto err_dma;
1924
1925         pci_set_master(pdev);
1926
1927         pciaddr = pci_resource_start(pdev, 0);
1928         if (!pciaddr) {
1929                 err = -EIO;
1930                 pr_err("no MMIO resource\n");
1931                 goto err_out_res;
1932         }
1933         regionSize = pci_resource_len(pdev, 0);
1934         if (regionSize < BDX_REGS_SIZE) {
1935                 err = -EIO;
1936                 pr_err("MMIO resource (%x) too small\n", regionSize);
1937                 goto err_out_res;
1938         }
1939
1940         nic->regs = ioremap(pciaddr, regionSize);
1941         if (!nic->regs) {
1942                 err = -EIO;
1943                 pr_err("ioremap failed\n");
1944                 goto err_out_res;
1945         }
1946
1947         if (pdev->irq < 2) {
1948                 err = -EIO;
1949                 pr_err("invalid irq (%d)\n", pdev->irq);
1950                 goto err_out_iomap;
1951         }
1952         pci_set_drvdata(pdev, nic);
1953
1954         if (pdev->device == 0x3014)
1955                 nic->port_num = 2;
1956         else
1957                 nic->port_num = 1;
1958
1959         print_hw_id(pdev);
1960
1961         bdx_hw_reset_direct(nic->regs);
1962
1963         nic->irq_type = IRQ_INTX;
1964 #ifdef BDX_MSI
1965         if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1966                 err = pci_enable_msi(pdev);
1967                 if (err)
1968                         pr_err("Can't enable msi. error is %d\n", err);
1969                 else
1970                         nic->irq_type = IRQ_MSI;
1971         } else
1972                 DBG("HW does not support MSI\n");
1973 #endif
1974
1975     /************** netdev **************/
1976         for (port = 0; port < nic->port_num; port++) {
1977                 ndev = alloc_etherdev(sizeof(struct bdx_priv));
1978                 if (!ndev) {
1979                         err = -ENOMEM;
1980                         goto err_out_iomap;
1981                 }
1982
1983                 ndev->netdev_ops = &bdx_netdev_ops;
1984                 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1985
1986                 bdx_set_ethtool_ops(ndev);      /* ethtool interface */
1987
1988                 /* these fields are used for info purposes only
1989                  * so we can have them same for all ports of the board */
1990                 ndev->if_port = port;
1991                 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
1992                     | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1993                     NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
1994                     ;
1995                 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1996                         NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
1997
1998                 if (pci_using_dac)
1999                         ndev->features |= NETIF_F_HIGHDMA;
2000
2001         /************** priv ****************/
2002                 priv = nic->priv[port] = netdev_priv(ndev);
2003
2004                 priv->pBdxRegs = nic->regs + port * 0x8000;
2005                 priv->port = port;
2006                 priv->pdev = pdev;
2007                 priv->ndev = ndev;
2008                 priv->nic = nic;
2009                 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2010
2011                 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2012
2013                 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2014                         DBG("HW statistics not supported\n");
2015                         priv->stats_flag = 0;
2016                 } else {
2017                         priv->stats_flag = 1;
2018                 }
2019
2020                 /* Initialize fifo sizes. */
2021                 priv->txd_size = 2;
2022                 priv->txf_size = 2;
2023                 priv->rxd_size = 2;
2024                 priv->rxf_size = 3;
2025
2026                 /* Initialize the initial coalescing registers. */
2027                 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2028                 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2029
2030                 /* ndev->xmit_lock spinlock is not used.
2031                  * Private priv->tx_lock is used for synchronization
2032                  * between transmit and TX irq cleanup.  In addition
2033                  * set multicast list callback has to use priv->tx_lock.
2034                  */
2035 #ifdef BDX_LLTX
2036                 ndev->features |= NETIF_F_LLTX;
2037 #endif
2038                 /* MTU range: 60 - 16384 */
2039                 ndev->min_mtu = ETH_ZLEN;
2040                 ndev->max_mtu = BDX_MAX_MTU;
2041
2042                 spin_lock_init(&priv->tx_lock);
2043
2044                 /*bdx_hw_reset(priv); */
2045                 if (bdx_read_mac(priv)) {
2046                         pr_err("load MAC address failed\n");
2047                         goto err_out_iomap;
2048                 }
2049                 SET_NETDEV_DEV(ndev, &pdev->dev);
2050                 err = register_netdev(ndev);
2051                 if (err) {
2052                         pr_err("register_netdev failed\n");
2053                         goto err_out_free;
2054                 }
2055                 netif_carrier_off(ndev);
2056                 netif_stop_queue(ndev);
2057
2058                 print_eth_id(ndev);
2059         }
2060         RET(0);
2061
2062 err_out_free:
2063         free_netdev(ndev);
2064 err_out_iomap:
2065         iounmap(nic->regs);
2066 err_out_res:
2067         pci_release_regions(pdev);
2068 err_dma:
2069         pci_disable_device(pdev);
2070 err_pci:
2071         vfree(nic);
2072
2073         RET(err);
2074 }
2075
2076 /****************** Ethtool interface *********************/
2077 /* get strings for statistics counters */
2078 static const char
2079  bdx_stat_names[][ETH_GSTRING_LEN] = {
2080         "InUCast",              /* 0x7200 */
2081         "InMCast",              /* 0x7210 */
2082         "InBCast",              /* 0x7220 */
2083         "InPkts",               /* 0x7230 */
2084         "InErrors",             /* 0x7240 */
2085         "InDropped",            /* 0x7250 */
2086         "FrameTooLong",         /* 0x7260 */
2087         "FrameSequenceErrors",  /* 0x7270 */
2088         "InVLAN",               /* 0x7280 */
2089         "InDroppedDFE",         /* 0x7290 */
2090         "InDroppedIntFull",     /* 0x72A0 */
2091         "InFrameAlignErrors",   /* 0x72B0 */
2092
2093         /* 0x72C0-0x72E0 RSRV */
2094
2095         "OutUCast",             /* 0x72F0 */
2096         "OutMCast",             /* 0x7300 */
2097         "OutBCast",             /* 0x7310 */
2098         "OutPkts",              /* 0x7320 */
2099
2100         /* 0x7330-0x7360 RSRV */
2101
2102         "OutVLAN",              /* 0x7370 */
2103         "InUCastOctects",       /* 0x7380 */
2104         "OutUCastOctects",      /* 0x7390 */
2105
2106         /* 0x73A0-0x73B0 RSRV */
2107
2108         "InBCastOctects",       /* 0x73C0 */
2109         "OutBCastOctects",      /* 0x73D0 */
2110         "InOctects",            /* 0x73E0 */
2111         "OutOctects",           /* 0x73F0 */
2112 };
2113
2114 /*
2115  * bdx_get_link_ksettings - get device-specific settings
2116  * @netdev
2117  * @ecmd
2118  */
2119 static int bdx_get_link_ksettings(struct net_device *netdev,
2120                                   struct ethtool_link_ksettings *ecmd)
2121 {
2122         ethtool_link_ksettings_zero_link_mode(ecmd, supported);
2123         ethtool_link_ksettings_add_link_mode(ecmd, supported,
2124                                              10000baseT_Full);
2125         ethtool_link_ksettings_add_link_mode(ecmd, supported, FIBRE);
2126         ethtool_link_ksettings_zero_link_mode(ecmd, advertising);
2127         ethtool_link_ksettings_add_link_mode(ecmd, advertising,
2128                                              10000baseT_Full);
2129         ethtool_link_ksettings_add_link_mode(ecmd, advertising, FIBRE);
2130
2131         ecmd->base.speed = SPEED_10000;
2132         ecmd->base.duplex = DUPLEX_FULL;
2133         ecmd->base.port = PORT_FIBRE;
2134         ecmd->base.autoneg = AUTONEG_DISABLE;
2135
2136         return 0;
2137 }
2138
2139 /*
2140  * bdx_get_drvinfo - report driver information
2141  * @netdev
2142  * @drvinfo
2143  */
2144 static void
2145 bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2146 {
2147         struct bdx_priv *priv = netdev_priv(netdev);
2148
2149         strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2150         strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2151         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2152         strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
2153                 sizeof(drvinfo->bus_info));
2154 }
2155
2156 /*
2157  * bdx_get_coalesce - get interrupt coalescing parameters
2158  * @netdev
2159  * @ecoal
2160  */
2161 static int
2162 bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2163 {
2164         u32 rdintcm;
2165         u32 tdintcm;
2166         struct bdx_priv *priv = netdev_priv(netdev);
2167
2168         rdintcm = priv->rdintcm;
2169         tdintcm = priv->tdintcm;
2170
2171         /* PCK_TH measures in multiples of FIFO bytes
2172            We translate to packets */
2173         ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2174         ecoal->rx_max_coalesced_frames =
2175             ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2176
2177         ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2178         ecoal->tx_max_coalesced_frames =
2179             ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2180
2181         /* adaptive parameters ignored */
2182         return 0;
2183 }
2184
2185 /*
2186  * bdx_set_coalesce - set interrupt coalescing parameters
2187  * @netdev
2188  * @ecoal
2189  */
2190 static int
2191 bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2192 {
2193         u32 rdintcm;
2194         u32 tdintcm;
2195         struct bdx_priv *priv = netdev_priv(netdev);
2196         int rx_coal;
2197         int tx_coal;
2198         int rx_max_coal;
2199         int tx_max_coal;
2200
2201         /* Check for valid input */
2202         rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2203         tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2204         rx_max_coal = ecoal->rx_max_coalesced_frames;
2205         tx_max_coal = ecoal->tx_max_coalesced_frames;
2206
2207         /* Translate from packets to multiples of FIFO bytes */
2208         rx_max_coal =
2209             (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2210              / PCK_TH_MULT);
2211         tx_max_coal =
2212             (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2213              / PCK_TH_MULT);
2214
2215         if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2216             (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2217                 return -EINVAL;
2218
2219         rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2220                               GET_RXF_TH(priv->rdintcm), rx_max_coal);
2221         tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2222                               tx_max_coal);
2223
2224         priv->rdintcm = rdintcm;
2225         priv->tdintcm = tdintcm;
2226
2227         WRITE_REG(priv, regRDINTCM0, rdintcm);
2228         WRITE_REG(priv, regTDINTCM0, tdintcm);
2229
2230         return 0;
2231 }
2232
2233 /* Convert RX fifo size to number of pending packets */
2234 static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2235 {
2236         return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
2237 }
2238
2239 /* Convert TX fifo size to number of pending packets */
2240 static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2241 {
2242         return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
2243 }
2244
2245 /*
2246  * bdx_get_ringparam - report ring sizes
2247  * @netdev
2248  * @ring
2249  */
2250 static void
2251 bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2252 {
2253         struct bdx_priv *priv = netdev_priv(netdev);
2254
2255         /*max_pending - the maximum-sized FIFO we allow */
2256         ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2257         ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2258         ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2259         ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2260 }
2261
2262 /*
2263  * bdx_set_ringparam - set ring sizes
2264  * @netdev
2265  * @ring
2266  */
2267 static int
2268 bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2269 {
2270         struct bdx_priv *priv = netdev_priv(netdev);
2271         int rx_size = 0;
2272         int tx_size = 0;
2273
2274         for (; rx_size < 4; rx_size++) {
2275                 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2276                         break;
2277         }
2278         if (rx_size == 4)
2279                 rx_size = 3;
2280
2281         for (; tx_size < 4; tx_size++) {
2282                 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2283                         break;
2284         }
2285         if (tx_size == 4)
2286                 tx_size = 3;
2287
2288         /*Is there anything to do? */
2289         if ((rx_size == priv->rxf_size) &&
2290             (tx_size == priv->txd_size))
2291                 return 0;
2292
2293         priv->rxf_size = rx_size;
2294         if (rx_size > 1)
2295                 priv->rxd_size = rx_size - 1;
2296         else
2297                 priv->rxd_size = rx_size;
2298
2299         priv->txf_size = priv->txd_size = tx_size;
2300
2301         if (netif_running(netdev)) {
2302                 bdx_close(netdev);
2303                 bdx_open(netdev);
2304         }
2305         return 0;
2306 }
2307
2308 /*
2309  * bdx_get_strings - return a set of strings that describe the requested objects
2310  * @netdev
2311  * @data
2312  */
2313 static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2314 {
2315         switch (stringset) {
2316         case ETH_SS_STATS:
2317                 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2318                 break;
2319         }
2320 }
2321
2322 /*
2323  * bdx_get_sset_count - return number of statistics or tests
2324  * @netdev
2325  */
2326 static int bdx_get_sset_count(struct net_device *netdev, int stringset)
2327 {
2328         struct bdx_priv *priv = netdev_priv(netdev);
2329
2330         switch (stringset) {
2331         case ETH_SS_STATS:
2332                 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2333                            != sizeof(struct bdx_stats) / sizeof(u64));
2334                 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names)  : 0;
2335         }
2336
2337         return -EINVAL;
2338 }
2339
2340 /*
2341  * bdx_get_ethtool_stats - return device's hardware L2 statistics
2342  * @netdev
2343  * @stats
2344  * @data
2345  */
2346 static void bdx_get_ethtool_stats(struct net_device *netdev,
2347                                   struct ethtool_stats *stats, u64 *data)
2348 {
2349         struct bdx_priv *priv = netdev_priv(netdev);
2350
2351         if (priv->stats_flag) {
2352
2353                 /* Update stats from HW */
2354                 bdx_update_stats(priv);
2355
2356                 /* Copy data to user buffer */
2357                 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2358         }
2359 }
2360
2361 /*
2362  * bdx_set_ethtool_ops - ethtool interface implementation
2363  * @netdev
2364  */
2365 static void bdx_set_ethtool_ops(struct net_device *netdev)
2366 {
2367         static const struct ethtool_ops bdx_ethtool_ops = {
2368                 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2369                                              ETHTOOL_COALESCE_MAX_FRAMES,
2370                 .get_drvinfo = bdx_get_drvinfo,
2371                 .get_link = ethtool_op_get_link,
2372                 .get_coalesce = bdx_get_coalesce,
2373                 .set_coalesce = bdx_set_coalesce,
2374                 .get_ringparam = bdx_get_ringparam,
2375                 .set_ringparam = bdx_set_ringparam,
2376                 .get_strings = bdx_get_strings,
2377                 .get_sset_count = bdx_get_sset_count,
2378                 .get_ethtool_stats = bdx_get_ethtool_stats,
2379                 .get_link_ksettings = bdx_get_link_ksettings,
2380         };
2381
2382         netdev->ethtool_ops = &bdx_ethtool_ops;
2383 }
2384
2385 /**
2386  * bdx_remove - Device Removal Routine
2387  * @pdev: PCI device information struct
2388  *
2389  * bdx_remove is called by the PCI subsystem to alert the driver
2390  * that it should release a PCI device.  The could be caused by a
2391  * Hot-Plug event, or because the driver is going to be removed from
2392  * memory.
2393  **/
2394 static void bdx_remove(struct pci_dev *pdev)
2395 {
2396         struct pci_nic *nic = pci_get_drvdata(pdev);
2397         struct net_device *ndev;
2398         int port;
2399
2400         for (port = 0; port < nic->port_num; port++) {
2401                 ndev = nic->priv[port]->ndev;
2402                 unregister_netdev(ndev);
2403                 free_netdev(ndev);
2404         }
2405
2406         /*bdx_hw_reset_direct(nic->regs); */
2407 #ifdef BDX_MSI
2408         if (nic->irq_type == IRQ_MSI)
2409                 pci_disable_msi(pdev);
2410 #endif
2411
2412         iounmap(nic->regs);
2413         pci_release_regions(pdev);
2414         pci_disable_device(pdev);
2415         vfree(nic);
2416
2417         RET();
2418 }
2419
2420 static struct pci_driver bdx_pci_driver = {
2421         .name = BDX_DRV_NAME,
2422         .id_table = bdx_pci_tbl,
2423         .probe = bdx_probe,
2424         .remove = bdx_remove,
2425 };
2426
2427 /*
2428  * print_driver_id - print parameters of the driver build
2429  */
2430 static void __init print_driver_id(void)
2431 {
2432         pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2433         pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
2434 }
2435
2436 static int __init bdx_module_init(void)
2437 {
2438         ENTER;
2439         init_txd_sizes();
2440         print_driver_id();
2441         RET(pci_register_driver(&bdx_pci_driver));
2442 }
2443
2444 module_init(bdx_module_init);
2445
2446 static void __exit bdx_module_exit(void)
2447 {
2448         ENTER;
2449         pci_unregister_driver(&bdx_pci_driver);
2450         RET();
2451 }
2452
2453 module_exit(bdx_module_exit);
2454
2455 MODULE_LICENSE("GPL");
2456 MODULE_AUTHOR(DRIVER_AUTHOR);
2457 MODULE_DESCRIPTION(BDX_DRV_DESC);
2458 MODULE_FIRMWARE("tehuti/bdx.bin");