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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / toshiba / tc35815.c
blob7a6e5ff8e5d43dd5c368424ff9bec081ef134bbe
1 /*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 *
4 * Based on skelton.c by Donald Becker.
5 *
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 *
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
23 */
24
25 #define DRV_VERSION "1.39"
26 static const char version[] = "tc35815.c:v" DRV_VERSION "\n";
27 #define MODNAME "tc35815"
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/fcntl.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/in.h>
36 #include <linux/if_vlan.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
39 #include <linux/spinlock.h>
40 #include <linux/errno.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/delay.h>
45 #include <linux/pci.h>
46 #include <linux/phy.h>
47 #include <linux/workqueue.h>
48 #include <linux/platform_device.h>
49 #include <linux/prefetch.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52
53 enum tc35815_chiptype {
54 TC35815CF = 0,
55 TC35815_NWU,
56 TC35815_TX4939,
57 };
58
59 /* indexed by tc35815_chiptype, above */
60 static const struct {
61 const char *name;
62 } chip_info[] = {
63 { "TOSHIBA TC35815CF 10/100BaseTX" },
64 { "TOSHIBA TC35815 with Wake on LAN" },
65 { "TOSHIBA TC35815/TX4939" },
66 };
67
68 static const struct pci_device_id tc35815_pci_tbl[] = {
69 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
72 {0,}
73 };
74 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
75
76 /* see MODULE_PARM_DESC */
77 static struct tc35815_options {
78 int speed;
79 int duplex;
80 } options;
81
82 /*
83 * Registers
84 */
85 struct tc35815_regs {
86 __u32 DMA_Ctl; /* 0x00 */
87 __u32 TxFrmPtr;
88 __u32 TxThrsh;
89 __u32 TxPollCtr;
90 __u32 BLFrmPtr;
91 __u32 RxFragSize;
92 __u32 Int_En;
93 __u32 FDA_Bas;
94 __u32 FDA_Lim; /* 0x20 */
95 __u32 Int_Src;
96 __u32 unused0[2];
97 __u32 PauseCnt;
98 __u32 RemPauCnt;
99 __u32 TxCtlFrmStat;
100 __u32 unused1;
101 __u32 MAC_Ctl; /* 0x40 */
102 __u32 CAM_Ctl;
103 __u32 Tx_Ctl;
104 __u32 Tx_Stat;
105 __u32 Rx_Ctl;
106 __u32 Rx_Stat;
107 __u32 MD_Data;
108 __u32 MD_CA;
109 __u32 CAM_Adr; /* 0x60 */
110 __u32 CAM_Data;
111 __u32 CAM_Ena;
112 __u32 PROM_Ctl;
113 __u32 PROM_Data;
114 __u32 Algn_Cnt;
115 __u32 CRC_Cnt;
116 __u32 Miss_Cnt;
117 };
118
119 /*
120 * Bit assignments
121 */
122 /* DMA_Ctl bit assign ------------------------------------------------------- */
123 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
124 #define DMA_RxAlign_1 0x00400000
125 #define DMA_RxAlign_2 0x00800000
126 #define DMA_RxAlign_3 0x00c00000
127 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
128 #define DMA_IntMask 0x00040000 /* 1:Interrupt mask */
129 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
130 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
131 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
132 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
133 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
134 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
135 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
136
137 /* RxFragSize bit assign ---------------------------------------------------- */
138 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
139 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
140
141 /* MAC_Ctl bit assign ------------------------------------------------------- */
142 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
143 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
144 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
145 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
146 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
147 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
148 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
149 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
150 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
151 #define MAC_Reset 0x00000004 /* 1:Software Reset */
152 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
153 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
154
155 /* PROM_Ctl bit assign ------------------------------------------------------ */
156 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
157 #define PROM_Read 0x00004000 /*10:Read operation */
158 #define PROM_Write 0x00002000 /*01:Write operation */
159 #define PROM_Erase 0x00006000 /*11:Erase operation */
160 /*00:Enable or Disable Writting, */
161 /* as specified in PROM_Addr. */
162 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
163 /*00xxxx: disable */
164
165 /* CAM_Ctl bit assign ------------------------------------------------------- */
166 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
167 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
168 /* accept other */
169 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
170 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
171 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
172
173 /* CAM_Ena bit assign ------------------------------------------------------- */
174 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
176 #define CAM_Ena_Bit(index) (1 << (index))
177 #define CAM_ENTRY_DESTINATION 0
178 #define CAM_ENTRY_SOURCE 1
179 #define CAM_ENTRY_MACCTL 20
180
181 /* Tx_Ctl bit assign -------------------------------------------------------- */
182 #define Tx_En 0x00000001 /* 1:Transmit enable */
183 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
184 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
185 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
186 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
187 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
188 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
189 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
190 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
191 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
192 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
193 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
194
195 /* Tx_Stat bit assign ------------------------------------------------------- */
196 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
197 #define Tx_ExColl 0x00000010 /* Excessive Collision */
198 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
199 #define Tx_Paused 0x00000040 /* Transmit Paused */
200 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
201 #define Tx_Under 0x00000100 /* Underrun */
202 #define Tx_Defer 0x00000200 /* Deferral */
203 #define Tx_NCarr 0x00000400 /* No Carrier */
204 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
205 #define Tx_LateColl 0x00001000 /* Late Collision */
206 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
207 #define Tx_Comp 0x00004000 /* Completion */
208 #define Tx_Halted 0x00008000 /* Tx Halted */
209 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
210
211 /* Rx_Ctl bit assign -------------------------------------------------------- */
212 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
213 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
214 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
215 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
216 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
217 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
218 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
219 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
220 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
221 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
222 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
223 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
224
225 /* Rx_Stat bit assign ------------------------------------------------------- */
226 #define Rx_Halted 0x00008000 /* Rx Halted */
227 #define Rx_Good 0x00004000 /* Rx Good */
228 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
229 #define Rx_TypePkt 0x00001000 /* Rx Type Packet */
230 #define Rx_LongErr 0x00000800 /* Rx Long Error */
231 #define Rx_Over 0x00000400 /* Rx Overflow */
232 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
233 #define Rx_Align 0x00000100 /* Rx Alignment Error */
234 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
235 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
236 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
237 #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
238
239 #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
240
241 /* Int_En bit assign -------------------------------------------------------- */
242 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
243 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
244 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
245 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
246 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
247 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
248 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
249 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
250 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
251 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
252 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
253 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
254 /* Exhausted Enable */
255
256 /* Int_Src bit assign ------------------------------------------------------- */
257 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
258 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
259 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
260 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
261 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
262 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
263 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
264 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
265 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
266 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
267 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
268 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
269 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
270 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
271 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
272
273 /* MD_CA bit assign --------------------------------------------------------- */
274 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */
275 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
276 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
277
278
279 /*
280 * Descriptors
281 */
282
283 /* Frame descriptor */
284 struct FDesc {
285 volatile __u32 FDNext;
286 volatile __u32 FDSystem;
287 volatile __u32 FDStat;
288 volatile __u32 FDCtl;
289 };
290
291 /* Buffer descriptor */
292 struct BDesc {
293 volatile __u32 BuffData;
294 volatile __u32 BDCtl;
295 };
296
297 #define FD_ALIGN 16
298
299 /* Frame Descriptor bit assign ---------------------------------------------- */
300 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
301 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
302 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
303 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
304 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
305 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
306 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
307 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
308 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
309 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
310 #define FD_BDCnt_SHIFT 16
311
312 /* Buffer Descriptor bit assign --------------------------------------------- */
313 #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */
314 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
315 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
316 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
317 #define BD_RxBDID_SHIFT 16
318 #define BD_RxBDSeqN_SHIFT 24
319
320
321 /* Some useful constants. */
322
323 #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
324 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
325 Tx_En) /* maybe 0x7b01 */
326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
327 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
328 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
329 #define INT_EN_CMD (Int_NRAbtEn | \
330 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
331 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
332 Int_STargAbtEn | \
333 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
334 #define DMA_CTL_CMD DMA_BURST_SIZE
335 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
336
337 /* Tuning parameters */
338 #define DMA_BURST_SIZE 32
339 #define TX_THRESHOLD 1024
340 /* used threshold with packet max byte for low pci transfer ability.*/
341 #define TX_THRESHOLD_MAX 1536
342 /* setting threshold max value when overrun error occurred this count. */
343 #define TX_THRESHOLD_KEEP_LIMIT 10
344
345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
346 #define FD_PAGE_NUM 4
347 #define RX_BUF_NUM 128 /* < 256 */
348 #define RX_FD_NUM 256 /* >= 32 */
349 #define TX_FD_NUM 128
350 #if RX_CTL_CMD & Rx_LongEn
351 #define RX_BUF_SIZE PAGE_SIZE
352 #elif RX_CTL_CMD & Rx_StripCRC
353 #define RX_BUF_SIZE \
354 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
355 #else
356 #define RX_BUF_SIZE \
357 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
358 #endif
359 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
360 #define NAPI_WEIGHT 16
361
362 struct TxFD {
363 struct FDesc fd;
364 struct BDesc bd;
365 struct BDesc unused;
366 };
367
368 struct RxFD {
369 struct FDesc fd;
370 struct BDesc bd[]; /* variable length */
371 };
372
373 struct FrFD {
374 struct FDesc fd;
375 struct BDesc bd[RX_BUF_NUM];
376 };
377
378
379 #define tc_readl(addr) ioread32(addr)
380 #define tc_writel(d, addr) iowrite32(d, addr)
381
382 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
383
384 /* Information that need to be kept for each controller. */
385 struct tc35815_local {
386 struct pci_dev *pci_dev;
387
388 struct net_device *dev;
389 struct napi_struct napi;
390
391 /* statistics */
392 struct {
393 int max_tx_qlen;
394 int tx_ints;
395 int rx_ints;
396 int tx_underrun;
397 } lstats;
398
399 /* Tx control lock. This protects the transmit buffer ring
400 * state along with the "tx full" state of the driver. This
401 * means all netif_queue flow control actions are protected
402 * by this lock as well.
403 */
404 spinlock_t lock;
405 spinlock_t rx_lock;
406
407 struct mii_bus *mii_bus;
408 int duplex;
409 int speed;
410 int link;
411 struct work_struct restart_work;
412
413 /*
414 * Transmitting: Batch Mode.
415 * 1 BD in 1 TxFD.
416 * Receiving: Non-Packing Mode.
417 * 1 circular FD for Free Buffer List.
418 * RX_BUF_NUM BD in Free Buffer FD.
419 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
420 */
421 void *fd_buf; /* for TxFD, RxFD, FrFD */
422 dma_addr_t fd_buf_dma;
423 struct TxFD *tfd_base;
424 unsigned int tfd_start;
425 unsigned int tfd_end;
426 struct RxFD *rfd_base;
427 struct RxFD *rfd_limit;
428 struct RxFD *rfd_cur;
429 struct FrFD *fbl_ptr;
430 unsigned int fbl_count;
431 struct {
432 struct sk_buff *skb;
433 dma_addr_t skb_dma;
434 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
435 u32 msg_enable;
436 enum tc35815_chiptype chiptype;
437 };
438
439 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
440 {
441 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
442 }
443 #ifdef DEBUG
444 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
445 {
446 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
447 }
448 #endif
449 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
450 struct pci_dev *hwdev,
451 dma_addr_t *dma_handle)
452 {
453 struct sk_buff *skb;
454 skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
455 if (!skb)
456 return NULL;
457 *dma_handle = dma_map_single(&hwdev->dev, skb->data, RX_BUF_SIZE,
458 DMA_FROM_DEVICE);
459 if (dma_mapping_error(&hwdev->dev, *dma_handle)) {
460 dev_kfree_skb_any(skb);
461 return NULL;
462 }
463 skb_reserve(skb, 2); /* make IP header 4byte aligned */
464 return skb;
465 }
466
467 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
468 {
469 dma_unmap_single(&hwdev->dev, dma_handle, RX_BUF_SIZE,
470 DMA_FROM_DEVICE);
471 dev_kfree_skb_any(skb);
472 }
473
474 /* Index to functions, as function prototypes. */
475
476 static int tc35815_open(struct net_device *dev);
477 static netdev_tx_t tc35815_send_packet(struct sk_buff *skb,
478 struct net_device *dev);
479 static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
480 static int tc35815_rx(struct net_device *dev, int limit);
481 static int tc35815_poll(struct napi_struct *napi, int budget);
482 static void tc35815_txdone(struct net_device *dev);
483 static int tc35815_close(struct net_device *dev);
484 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
485 static void tc35815_set_multicast_list(struct net_device *dev);
486 static void tc35815_tx_timeout(struct net_device *dev, unsigned int txqueue);
487 #ifdef CONFIG_NET_POLL_CONTROLLER
488 static void tc35815_poll_controller(struct net_device *dev);
489 #endif
490 static const struct ethtool_ops tc35815_ethtool_ops;
491
492 /* Example routines you must write ;->. */
493 static void tc35815_chip_reset(struct net_device *dev);
494 static void tc35815_chip_init(struct net_device *dev);
495
496 #ifdef DEBUG
497 static void panic_queues(struct net_device *dev);
498 #endif
499
500 static void tc35815_restart_work(struct work_struct *work);
501
502 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
503 {
504 struct net_device *dev = bus->priv;
505 struct tc35815_regs __iomem *tr =
506 (struct tc35815_regs __iomem *)dev->base_addr;
507 unsigned long timeout = jiffies + HZ;
508
509 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
510 udelay(12); /* it takes 32 x 400ns at least */
511 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
512 if (time_after(jiffies, timeout))
513 return -EIO;
514 cpu_relax();
515 }
516 return tc_readl(&tr->MD_Data) & 0xffff;
517 }
518
519 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
520 {
521 struct net_device *dev = bus->priv;
522 struct tc35815_regs __iomem *tr =
523 (struct tc35815_regs __iomem *)dev->base_addr;
524 unsigned long timeout = jiffies + HZ;
525
526 tc_writel(val, &tr->MD_Data);
527 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
528 &tr->MD_CA);
529 udelay(12); /* it takes 32 x 400ns at least */
530 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
531 if (time_after(jiffies, timeout))
532 return -EIO;
533 cpu_relax();
534 }
535 return 0;
536 }
537
538 static void tc_handle_link_change(struct net_device *dev)
539 {
540 struct tc35815_local *lp = netdev_priv(dev);
541 struct phy_device *phydev = dev->phydev;
542 unsigned long flags;
543 int status_change = 0;
544
545 spin_lock_irqsave(&lp->lock, flags);
546 if (phydev->link &&
547 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
548 struct tc35815_regs __iomem *tr =
549 (struct tc35815_regs __iomem *)dev->base_addr;
550 u32 reg;
551
552 reg = tc_readl(&tr->MAC_Ctl);
553 reg |= MAC_HaltReq;
554 tc_writel(reg, &tr->MAC_Ctl);
555 if (phydev->duplex == DUPLEX_FULL)
556 reg |= MAC_FullDup;
557 else
558 reg &= ~MAC_FullDup;
559 tc_writel(reg, &tr->MAC_Ctl);
560 reg &= ~MAC_HaltReq;
561 tc_writel(reg, &tr->MAC_Ctl);
562
563 /*
564 * TX4939 PCFG.SPEEDn bit will be changed on
565 * NETDEV_CHANGE event.
566 */
567 /*
568 * WORKAROUND: enable LostCrS only if half duplex
569 * operation.
570 * (TX4939 does not have EnLCarr)
571 */
572 if (phydev->duplex == DUPLEX_HALF &&
573 lp->chiptype != TC35815_TX4939)
574 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
575 &tr->Tx_Ctl);
576
577 lp->speed = phydev->speed;
578 lp->duplex = phydev->duplex;
579 status_change = 1;
580 }
581
582 if (phydev->link != lp->link) {
583 if (phydev->link) {
584 /* delayed promiscuous enabling */
585 if (dev->flags & IFF_PROMISC)
586 tc35815_set_multicast_list(dev);
587 } else {
588 lp->speed = 0;
589 lp->duplex = -1;
590 }
591 lp->link = phydev->link;
592
593 status_change = 1;
594 }
595 spin_unlock_irqrestore(&lp->lock, flags);
596
597 if (status_change && netif_msg_link(lp)) {
598 phy_print_status(phydev);
599 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
600 dev->name,
601 phy_read(phydev, MII_BMCR),
602 phy_read(phydev, MII_BMSR),
603 phy_read(phydev, MII_LPA));
604 }
605 }
606
607 static int tc_mii_probe(struct net_device *dev)
608 {
609 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
610 struct tc35815_local *lp = netdev_priv(dev);
611 struct phy_device *phydev;
612
613 phydev = phy_find_first(lp->mii_bus);
614 if (!phydev) {
615 printk(KERN_ERR "%s: no PHY found\n", dev->name);
616 return -ENODEV;
617 }
618
619 /* attach the mac to the phy */
620 phydev = phy_connect(dev, phydev_name(phydev),
621 &tc_handle_link_change,
622 lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
623 if (IS_ERR(phydev)) {
624 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
625 return PTR_ERR(phydev);
626 }
627
628 phy_attached_info(phydev);
629
630 /* mask with MAC supported features */
631 phy_set_max_speed(phydev, SPEED_100);
632 if (options.speed == 10) {
633 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
634 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
635 } else if (options.speed == 100) {
636 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
637 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
638 }
639 if (options.duplex == 1) {
640 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
641 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
642 } else if (options.duplex == 2) {
643 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
644 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
645 }
646 linkmode_andnot(phydev->supported, phydev->supported, mask);
647 linkmode_copy(phydev->advertising, phydev->supported);
648
649 lp->link = 0;
650 lp->speed = 0;
651 lp->duplex = -1;
652
653 return 0;
654 }
655
656 static int tc_mii_init(struct net_device *dev)
657 {
658 struct tc35815_local *lp = netdev_priv(dev);
659 int err;
660
661 lp->mii_bus = mdiobus_alloc();
662 if (lp->mii_bus == NULL) {
663 err = -ENOMEM;
664 goto err_out;
665 }
666
667 lp->mii_bus->name = "tc35815_mii_bus";
668 lp->mii_bus->read = tc_mdio_read;
669 lp->mii_bus->write = tc_mdio_write;
670 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
671 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
672 lp->mii_bus->priv = dev;
673 lp->mii_bus->parent = &lp->pci_dev->dev;
674 err = mdiobus_register(lp->mii_bus);
675 if (err)
676 goto err_out_free_mii_bus;
677 err = tc_mii_probe(dev);
678 if (err)
679 goto err_out_unregister_bus;
680 return 0;
681
682 err_out_unregister_bus:
683 mdiobus_unregister(lp->mii_bus);
684 err_out_free_mii_bus:
685 mdiobus_free(lp->mii_bus);
686 err_out:
687 return err;
688 }
689
690 #ifdef CONFIG_CPU_TX49XX
691 /*
692 * Find a platform_device providing a MAC address. The platform code
693 * should provide a "tc35815-mac" device with a MAC address in its
694 * platform_data.
695 */
696 static int tc35815_mac_match(struct device *dev, const void *data)
697 {
698 struct platform_device *plat_dev = to_platform_device(dev);
699 const struct pci_dev *pci_dev = data;
700 unsigned int id = pci_dev->irq;
701 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
702 }
703
704 static int tc35815_read_plat_dev_addr(struct net_device *dev)
705 {
706 struct tc35815_local *lp = netdev_priv(dev);
707 struct device *pd = bus_find_device(&platform_bus_type, NULL,
708 lp->pci_dev, tc35815_mac_match);
709 if (pd) {
710 if (pd->platform_data)
711 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
712 put_device(pd);
713 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
714 }
715 return -ENODEV;
716 }
717 #else
718 static int tc35815_read_plat_dev_addr(struct net_device *dev)
719 {
720 return -ENODEV;
721 }
722 #endif
723
724 static int tc35815_init_dev_addr(struct net_device *dev)
725 {
726 struct tc35815_regs __iomem *tr =
727 (struct tc35815_regs __iomem *)dev->base_addr;
728 int i;
729
730 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
731 ;
732 for (i = 0; i < 6; i += 2) {
733 unsigned short data;
734 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
735 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
736 ;
737 data = tc_readl(&tr->PROM_Data);
738 dev->dev_addr[i] = data & 0xff;
739 dev->dev_addr[i+1] = data >> 8;
740 }
741 if (!is_valid_ether_addr(dev->dev_addr))
742 return tc35815_read_plat_dev_addr(dev);
743 return 0;
744 }
745
746 static const struct net_device_ops tc35815_netdev_ops = {
747 .ndo_open = tc35815_open,
748 .ndo_stop = tc35815_close,
749 .ndo_start_xmit = tc35815_send_packet,
750 .ndo_get_stats = tc35815_get_stats,
751 .ndo_set_rx_mode = tc35815_set_multicast_list,
752 .ndo_tx_timeout = tc35815_tx_timeout,
753 .ndo_do_ioctl = phy_do_ioctl_running,
754 .ndo_validate_addr = eth_validate_addr,
755 .ndo_set_mac_address = eth_mac_addr,
756 #ifdef CONFIG_NET_POLL_CONTROLLER
757 .ndo_poll_controller = tc35815_poll_controller,
758 #endif
759 };
760
761 static int tc35815_init_one(struct pci_dev *pdev,
762 const struct pci_device_id *ent)
763 {
764 void __iomem *ioaddr = NULL;
765 struct net_device *dev;
766 struct tc35815_local *lp;
767 int rc;
768
769 static int printed_version;
770 if (!printed_version++) {
771 printk(version);
772 dev_printk(KERN_DEBUG, &pdev->dev,
773 "speed:%d duplex:%d\n",
774 options.speed, options.duplex);
775 }
776
777 if (!pdev->irq) {
778 dev_warn(&pdev->dev, "no IRQ assigned.\n");
779 return -ENODEV;
780 }
781
782 /* dev zeroed in alloc_etherdev */
783 dev = alloc_etherdev(sizeof(*lp));
784 if (dev == NULL)
785 return -ENOMEM;
786
787 SET_NETDEV_DEV(dev, &pdev->dev);
788 lp = netdev_priv(dev);
789 lp->dev = dev;
790
791 /* enable device (incl. PCI PM wakeup), and bus-mastering */
792 rc = pcim_enable_device(pdev);
793 if (rc)
794 goto err_out;
795 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
796 if (rc)
797 goto err_out;
798 pci_set_master(pdev);
799 ioaddr = pcim_iomap_table(pdev)[1];
800
801 /* Initialize the device structure. */
802 dev->netdev_ops = &tc35815_netdev_ops;
803 dev->ethtool_ops = &tc35815_ethtool_ops;
804 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
805 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
806
807 dev->irq = pdev->irq;
808 dev->base_addr = (unsigned long)ioaddr;
809
810 INIT_WORK(&lp->restart_work, tc35815_restart_work);
811 spin_lock_init(&lp->lock);
812 spin_lock_init(&lp->rx_lock);
813 lp->pci_dev = pdev;
814 lp->chiptype = ent->driver_data;
815
816 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
817 pci_set_drvdata(pdev, dev);
818
819 /* Soft reset the chip. */
820 tc35815_chip_reset(dev);
821
822 /* Retrieve the ethernet address. */
823 if (tc35815_init_dev_addr(dev)) {
824 dev_warn(&pdev->dev, "not valid ether addr\n");
825 eth_hw_addr_random(dev);
826 }
827
828 rc = register_netdev(dev);
829 if (rc)
830 goto err_out;
831
832 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
833 dev->name,
834 chip_info[ent->driver_data].name,
835 dev->base_addr,
836 dev->dev_addr,
837 dev->irq);
838
839 rc = tc_mii_init(dev);
840 if (rc)
841 goto err_out_unregister;
842
843 return 0;
844
845 err_out_unregister:
846 unregister_netdev(dev);
847 err_out:
848 free_netdev(dev);
849 return rc;
850 }
851
852
853 static void tc35815_remove_one(struct pci_dev *pdev)
854 {
855 struct net_device *dev = pci_get_drvdata(pdev);
856 struct tc35815_local *lp = netdev_priv(dev);
857
858 phy_disconnect(dev->phydev);
859 mdiobus_unregister(lp->mii_bus);
860 mdiobus_free(lp->mii_bus);
861 unregister_netdev(dev);
862 free_netdev(dev);
863 }
864
865 static int
866 tc35815_init_queues(struct net_device *dev)
867 {
868 struct tc35815_local *lp = netdev_priv(dev);
869 int i;
870 unsigned long fd_addr;
871
872 if (!lp->fd_buf) {
873 BUG_ON(sizeof(struct FDesc) +
874 sizeof(struct BDesc) * RX_BUF_NUM +
875 sizeof(struct FDesc) * RX_FD_NUM +
876 sizeof(struct TxFD) * TX_FD_NUM >
877 PAGE_SIZE * FD_PAGE_NUM);
878
879 lp->fd_buf = dma_alloc_coherent(&lp->pci_dev->dev,
880 PAGE_SIZE * FD_PAGE_NUM,
881 &lp->fd_buf_dma, GFP_ATOMIC);
882 if (!lp->fd_buf)
883 return -ENOMEM;
884 for (i = 0; i < RX_BUF_NUM; i++) {
885 lp->rx_skbs[i].skb =
886 alloc_rxbuf_skb(dev, lp->pci_dev,
887 &lp->rx_skbs[i].skb_dma);
888 if (!lp->rx_skbs[i].skb) {
889 while (--i >= 0) {
890 free_rxbuf_skb(lp->pci_dev,
891 lp->rx_skbs[i].skb,
892 lp->rx_skbs[i].skb_dma);
893 lp->rx_skbs[i].skb = NULL;
894 }
895 dma_free_coherent(&lp->pci_dev->dev,
896 PAGE_SIZE * FD_PAGE_NUM,
897 lp->fd_buf, lp->fd_buf_dma);
898 lp->fd_buf = NULL;
899 return -ENOMEM;
900 }
901 }
902 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
903 dev->name, lp->fd_buf);
904 printk("\n");
905 } else {
906 for (i = 0; i < FD_PAGE_NUM; i++)
907 clear_page((void *)((unsigned long)lp->fd_buf +
908 i * PAGE_SIZE));
909 }
910 fd_addr = (unsigned long)lp->fd_buf;
911
912 /* Free Descriptors (for Receive) */
913 lp->rfd_base = (struct RxFD *)fd_addr;
914 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
915 for (i = 0; i < RX_FD_NUM; i++)
916 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
917 lp->rfd_cur = lp->rfd_base;
918 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
919
920 /* Transmit Descriptors */
921 lp->tfd_base = (struct TxFD *)fd_addr;
922 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
923 for (i = 0; i < TX_FD_NUM; i++) {
924 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
925 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
926 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
927 }
928 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
929 lp->tfd_start = 0;
930 lp->tfd_end = 0;
931
932 /* Buffer List (for Receive) */
933 lp->fbl_ptr = (struct FrFD *)fd_addr;
934 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
935 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
936 /*
937 * move all allocated skbs to head of rx_skbs[] array.
938 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
939 * tc35815_rx() had failed.
940 */
941 lp->fbl_count = 0;
942 for (i = 0; i < RX_BUF_NUM; i++) {
943 if (lp->rx_skbs[i].skb) {
944 if (i != lp->fbl_count) {
945 lp->rx_skbs[lp->fbl_count].skb =
946 lp->rx_skbs[i].skb;
947 lp->rx_skbs[lp->fbl_count].skb_dma =
948 lp->rx_skbs[i].skb_dma;
949 }
950 lp->fbl_count++;
951 }
952 }
953 for (i = 0; i < RX_BUF_NUM; i++) {
954 if (i >= lp->fbl_count) {
955 lp->fbl_ptr->bd[i].BuffData = 0;
956 lp->fbl_ptr->bd[i].BDCtl = 0;
957 continue;
958 }
959 lp->fbl_ptr->bd[i].BuffData =
960 cpu_to_le32(lp->rx_skbs[i].skb_dma);
961 /* BDID is index of FrFD.bd[] */
962 lp->fbl_ptr->bd[i].BDCtl =
963 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
964 RX_BUF_SIZE);
965 }
966
967 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
968 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
969 return 0;
970 }
971
972 static void
973 tc35815_clear_queues(struct net_device *dev)
974 {
975 struct tc35815_local *lp = netdev_priv(dev);
976 int i;
977
978 for (i = 0; i < TX_FD_NUM; i++) {
979 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
980 struct sk_buff *skb =
981 fdsystem != 0xffffffff ?
982 lp->tx_skbs[fdsystem].skb : NULL;
983 #ifdef DEBUG
984 if (lp->tx_skbs[i].skb != skb) {
985 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
986 panic_queues(dev);
987 }
988 #else
989 BUG_ON(lp->tx_skbs[i].skb != skb);
990 #endif
991 if (skb) {
992 dma_unmap_single(&lp->pci_dev->dev,
993 lp->tx_skbs[i].skb_dma, skb->len,
994 DMA_TO_DEVICE);
995 lp->tx_skbs[i].skb = NULL;
996 lp->tx_skbs[i].skb_dma = 0;
997 dev_kfree_skb_any(skb);
998 }
999 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1000 }
1001
1002 tc35815_init_queues(dev);
1003 }
1004
1005 static void
1006 tc35815_free_queues(struct net_device *dev)
1007 {
1008 struct tc35815_local *lp = netdev_priv(dev);
1009 int i;
1010
1011 if (lp->tfd_base) {
1012 for (i = 0; i < TX_FD_NUM; i++) {
1013 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1014 struct sk_buff *skb =
1015 fdsystem != 0xffffffff ?
1016 lp->tx_skbs[fdsystem].skb : NULL;
1017 #ifdef DEBUG
1018 if (lp->tx_skbs[i].skb != skb) {
1019 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1020 panic_queues(dev);
1021 }
1022 #else
1023 BUG_ON(lp->tx_skbs[i].skb != skb);
1024 #endif
1025 if (skb) {
1026 dma_unmap_single(&lp->pci_dev->dev,
1027 lp->tx_skbs[i].skb_dma,
1028 skb->len, DMA_TO_DEVICE);
1029 dev_kfree_skb(skb);
1030 lp->tx_skbs[i].skb = NULL;
1031 lp->tx_skbs[i].skb_dma = 0;
1032 }
1033 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1034 }
1035 }
1036
1037 lp->rfd_base = NULL;
1038 lp->rfd_limit = NULL;
1039 lp->rfd_cur = NULL;
1040 lp->fbl_ptr = NULL;
1041
1042 for (i = 0; i < RX_BUF_NUM; i++) {
1043 if (lp->rx_skbs[i].skb) {
1044 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1045 lp->rx_skbs[i].skb_dma);
1046 lp->rx_skbs[i].skb = NULL;
1047 }
1048 }
1049 if (lp->fd_buf) {
1050 dma_free_coherent(&lp->pci_dev->dev, PAGE_SIZE * FD_PAGE_NUM,
1051 lp->fd_buf, lp->fd_buf_dma);
1052 lp->fd_buf = NULL;
1053 }
1054 }
1055
1056 static void
1057 dump_txfd(struct TxFD *fd)
1058 {
1059 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1060 le32_to_cpu(fd->fd.FDNext),
1061 le32_to_cpu(fd->fd.FDSystem),
1062 le32_to_cpu(fd->fd.FDStat),
1063 le32_to_cpu(fd->fd.FDCtl));
1064 printk("BD: ");
1065 printk(" %08x %08x",
1066 le32_to_cpu(fd->bd.BuffData),
1067 le32_to_cpu(fd->bd.BDCtl));
1068 printk("\n");
1069 }
1070
1071 static int
1072 dump_rxfd(struct RxFD *fd)
1073 {
1074 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1075 if (bd_count > 8)
1076 bd_count = 8;
1077 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1078 le32_to_cpu(fd->fd.FDNext),
1079 le32_to_cpu(fd->fd.FDSystem),
1080 le32_to_cpu(fd->fd.FDStat),
1081 le32_to_cpu(fd->fd.FDCtl));
1082 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1083 return 0;
1084 printk("BD: ");
1085 for (i = 0; i < bd_count; i++)
1086 printk(" %08x %08x",
1087 le32_to_cpu(fd->bd[i].BuffData),
1088 le32_to_cpu(fd->bd[i].BDCtl));
1089 printk("\n");
1090 return bd_count;
1091 }
1092
1093 #ifdef DEBUG
1094 static void
1095 dump_frfd(struct FrFD *fd)
1096 {
1097 int i;
1098 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1099 le32_to_cpu(fd->fd.FDNext),
1100 le32_to_cpu(fd->fd.FDSystem),
1101 le32_to_cpu(fd->fd.FDStat),
1102 le32_to_cpu(fd->fd.FDCtl));
1103 printk("BD: ");
1104 for (i = 0; i < RX_BUF_NUM; i++)
1105 printk(" %08x %08x",
1106 le32_to_cpu(fd->bd[i].BuffData),
1107 le32_to_cpu(fd->bd[i].BDCtl));
1108 printk("\n");
1109 }
1110
1111 static void
1112 panic_queues(struct net_device *dev)
1113 {
1114 struct tc35815_local *lp = netdev_priv(dev);
1115 int i;
1116
1117 printk("TxFD base %p, start %u, end %u\n",
1118 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1119 printk("RxFD base %p limit %p cur %p\n",
1120 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1121 printk("FrFD %p\n", lp->fbl_ptr);
1122 for (i = 0; i < TX_FD_NUM; i++)
1123 dump_txfd(&lp->tfd_base[i]);
1124 for (i = 0; i < RX_FD_NUM; i++) {
1125 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1126 i += (bd_count + 1) / 2; /* skip BDs */
1127 }
1128 dump_frfd(lp->fbl_ptr);
1129 panic("%s: Illegal queue state.", dev->name);
1130 }
1131 #endif
1132
1133 static void print_eth(const u8 *add)
1134 {
1135 printk(KERN_DEBUG "print_eth(%p)\n", add);
1136 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1137 add + 6, add, add[12], add[13]);
1138 }
1139
1140 static int tc35815_tx_full(struct net_device *dev)
1141 {
1142 struct tc35815_local *lp = netdev_priv(dev);
1143 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1144 }
1145
1146 static void tc35815_restart(struct net_device *dev)
1147 {
1148 struct tc35815_local *lp = netdev_priv(dev);
1149 int ret;
1150
1151 if (dev->phydev) {
1152 ret = phy_init_hw(dev->phydev);
1153 if (ret)
1154 printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
1155 }
1156
1157 spin_lock_bh(&lp->rx_lock);
1158 spin_lock_irq(&lp->lock);
1159 tc35815_chip_reset(dev);
1160 tc35815_clear_queues(dev);
1161 tc35815_chip_init(dev);
1162 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1163 tc35815_set_multicast_list(dev);
1164 spin_unlock_irq(&lp->lock);
1165 spin_unlock_bh(&lp->rx_lock);
1166
1167 netif_wake_queue(dev);
1168 }
1169
1170 static void tc35815_restart_work(struct work_struct *work)
1171 {
1172 struct tc35815_local *lp =
1173 container_of(work, struct tc35815_local, restart_work);
1174 struct net_device *dev = lp->dev;
1175
1176 tc35815_restart(dev);
1177 }
1178
1179 static void tc35815_schedule_restart(struct net_device *dev)
1180 {
1181 struct tc35815_local *lp = netdev_priv(dev);
1182 struct tc35815_regs __iomem *tr =
1183 (struct tc35815_regs __iomem *)dev->base_addr;
1184 unsigned long flags;
1185
1186 /* disable interrupts */
1187 spin_lock_irqsave(&lp->lock, flags);
1188 tc_writel(0, &tr->Int_En);
1189 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1190 schedule_work(&lp->restart_work);
1191 spin_unlock_irqrestore(&lp->lock, flags);
1192 }
1193
1194 static void tc35815_tx_timeout(struct net_device *dev, unsigned int txqueue)
1195 {
1196 struct tc35815_regs __iomem *tr =
1197 (struct tc35815_regs __iomem *)dev->base_addr;
1198
1199 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1200 dev->name, tc_readl(&tr->Tx_Stat));
1201
1202 /* Try to restart the adaptor. */
1203 tc35815_schedule_restart(dev);
1204 dev->stats.tx_errors++;
1205 }
1206
1207 /*
1208 * Open/initialize the controller. This is called (in the current kernel)
1209 * sometime after booting when the 'ifconfig' program is run.
1210 *
1211 * This routine should set everything up anew at each open, even
1212 * registers that "should" only need to be set once at boot, so that
1213 * there is non-reboot way to recover if something goes wrong.
1214 */
1215 static int
1216 tc35815_open(struct net_device *dev)
1217 {
1218 struct tc35815_local *lp = netdev_priv(dev);
1219
1220 /*
1221 * This is used if the interrupt line can turned off (shared).
1222 * See 3c503.c for an example of selecting the IRQ at config-time.
1223 */
1224 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1225 dev->name, dev))
1226 return -EAGAIN;
1227
1228 tc35815_chip_reset(dev);
1229
1230 if (tc35815_init_queues(dev) != 0) {
1231 free_irq(dev->irq, dev);
1232 return -EAGAIN;
1233 }
1234
1235 napi_enable(&lp->napi);
1236
1237 /* Reset the hardware here. Don't forget to set the station address. */
1238 spin_lock_irq(&lp->lock);
1239 tc35815_chip_init(dev);
1240 spin_unlock_irq(&lp->lock);
1241
1242 netif_carrier_off(dev);
1243 /* schedule a link state check */
1244 phy_start(dev->phydev);
1245
1246 /* We are now ready to accept transmit requeusts from
1247 * the queueing layer of the networking.
1248 */
1249 netif_start_queue(dev);
1250
1251 return 0;
1252 }
1253
1254 /* This will only be invoked if your driver is _not_ in XOFF state.
1255 * What this means is that you need not check it, and that this
1256 * invariant will hold if you make sure that the netif_*_queue()
1257 * calls are done at the proper times.
1258 */
1259 static netdev_tx_t
1260 tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1261 {
1262 struct tc35815_local *lp = netdev_priv(dev);
1263 struct TxFD *txfd;
1264 unsigned long flags;
1265
1266 /* If some error occurs while trying to transmit this
1267 * packet, you should return '1' from this function.
1268 * In such a case you _may not_ do anything to the
1269 * SKB, it is still owned by the network queueing
1270 * layer when an error is returned. This means you
1271 * may not modify any SKB fields, you may not free
1272 * the SKB, etc.
1273 */
1274
1275 /* This is the most common case for modern hardware.
1276 * The spinlock protects this code from the TX complete
1277 * hardware interrupt handler. Queue flow control is
1278 * thus managed under this lock as well.
1279 */
1280 spin_lock_irqsave(&lp->lock, flags);
1281
1282 /* failsafe... (handle txdone now if half of FDs are used) */
1283 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1284 TX_FD_NUM / 2)
1285 tc35815_txdone(dev);
1286
1287 if (netif_msg_pktdata(lp))
1288 print_eth(skb->data);
1289 #ifdef DEBUG
1290 if (lp->tx_skbs[lp->tfd_start].skb) {
1291 printk("%s: tx_skbs conflict.\n", dev->name);
1292 panic_queues(dev);
1293 }
1294 #else
1295 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1296 #endif
1297 lp->tx_skbs[lp->tfd_start].skb = skb;
1298 lp->tx_skbs[lp->tfd_start].skb_dma = dma_map_single(&lp->pci_dev->dev,
1299 skb->data,
1300 skb->len,
1301 DMA_TO_DEVICE);
1302
1303 /*add to ring */
1304 txfd = &lp->tfd_base[lp->tfd_start];
1305 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1306 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1307 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1308 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1309
1310 if (lp->tfd_start == lp->tfd_end) {
1311 struct tc35815_regs __iomem *tr =
1312 (struct tc35815_regs __iomem *)dev->base_addr;
1313 /* Start DMA Transmitter. */
1314 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1315 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1316 if (netif_msg_tx_queued(lp)) {
1317 printk("%s: starting TxFD.\n", dev->name);
1318 dump_txfd(txfd);
1319 }
1320 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1321 } else {
1322 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1323 if (netif_msg_tx_queued(lp)) {
1324 printk("%s: queueing TxFD.\n", dev->name);
1325 dump_txfd(txfd);
1326 }
1327 }
1328 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1329
1330 /* If we just used up the very last entry in the
1331 * TX ring on this device, tell the queueing
1332 * layer to send no more.
1333 */
1334 if (tc35815_tx_full(dev)) {
1335 if (netif_msg_tx_queued(lp))
1336 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1337 netif_stop_queue(dev);
1338 }
1339
1340 /* When the TX completion hw interrupt arrives, this
1341 * is when the transmit statistics are updated.
1342 */
1343
1344 spin_unlock_irqrestore(&lp->lock, flags);
1345 return NETDEV_TX_OK;
1346 }
1347
1348 #define FATAL_ERROR_INT \
1349 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1350 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1351 {
1352 static int count;
1353 printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):",
1354 dev->name, status);
1355 if (status & Int_IntPCI)
1356 printk(" IntPCI");
1357 if (status & Int_DmParErr)
1358 printk(" DmParErr");
1359 if (status & Int_IntNRAbt)
1360 printk(" IntNRAbt");
1361 printk("\n");
1362 if (count++ > 100)
1363 panic("%s: Too many fatal errors.", dev->name);
1364 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1365 /* Try to restart the adaptor. */
1366 tc35815_schedule_restart(dev);
1367 }
1368
1369 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1370 {
1371 struct tc35815_local *lp = netdev_priv(dev);
1372 int ret = -1;
1373
1374 /* Fatal errors... */
1375 if (status & FATAL_ERROR_INT) {
1376 tc35815_fatal_error_interrupt(dev, status);
1377 return 0;
1378 }
1379 /* recoverable errors */
1380 if (status & Int_IntFDAEx) {
1381 if (netif_msg_rx_err(lp))
1382 dev_warn(&dev->dev,
1383 "Free Descriptor Area Exhausted (%#x).\n",
1384 status);
1385 dev->stats.rx_dropped++;
1386 ret = 0;
1387 }
1388 if (status & Int_IntBLEx) {
1389 if (netif_msg_rx_err(lp))
1390 dev_warn(&dev->dev,
1391 "Buffer List Exhausted (%#x).\n",
1392 status);
1393 dev->stats.rx_dropped++;
1394 ret = 0;
1395 }
1396 if (status & Int_IntExBD) {
1397 if (netif_msg_rx_err(lp))
1398 dev_warn(&dev->dev,
1399 "Excessive Buffer Descriptors (%#x).\n",
1400 status);
1401 dev->stats.rx_length_errors++;
1402 ret = 0;
1403 }
1404
1405 /* normal notification */
1406 if (status & Int_IntMacRx) {
1407 /* Got a packet(s). */
1408 ret = tc35815_rx(dev, limit);
1409 lp->lstats.rx_ints++;
1410 }
1411 if (status & Int_IntMacTx) {
1412 /* Transmit complete. */
1413 lp->lstats.tx_ints++;
1414 spin_lock_irq(&lp->lock);
1415 tc35815_txdone(dev);
1416 spin_unlock_irq(&lp->lock);
1417 if (ret < 0)
1418 ret = 0;
1419 }
1420 return ret;
1421 }
1422
1423 /*
1424 * The typical workload of the driver:
1425 * Handle the network interface interrupts.
1426 */
1427 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1428 {
1429 struct net_device *dev = dev_id;
1430 struct tc35815_local *lp = netdev_priv(dev);
1431 struct tc35815_regs __iomem *tr =
1432 (struct tc35815_regs __iomem *)dev->base_addr;
1433 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1434
1435 if (!(dmactl & DMA_IntMask)) {
1436 /* disable interrupts */
1437 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1438 if (napi_schedule_prep(&lp->napi))
1439 __napi_schedule(&lp->napi);
1440 else {
1441 printk(KERN_ERR "%s: interrupt taken in poll\n",
1442 dev->name);
1443 BUG();
1444 }
1445 (void)tc_readl(&tr->Int_Src); /* flush */
1446 return IRQ_HANDLED;
1447 }
1448 return IRQ_NONE;
1449 }
1450
1451 #ifdef CONFIG_NET_POLL_CONTROLLER
1452 static void tc35815_poll_controller(struct net_device *dev)
1453 {
1454 disable_irq(dev->irq);
1455 tc35815_interrupt(dev->irq, dev);
1456 enable_irq(dev->irq);
1457 }
1458 #endif
1459
1460 /* We have a good packet(s), get it/them out of the buffers. */
1461 static int
1462 tc35815_rx(struct net_device *dev, int limit)
1463 {
1464 struct tc35815_local *lp = netdev_priv(dev);
1465 unsigned int fdctl;
1466 int i;
1467 int received = 0;
1468
1469 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1470 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1471 int pkt_len = fdctl & FD_FDLength_MASK;
1472 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1473 #ifdef DEBUG
1474 struct RxFD *next_rfd;
1475 #endif
1476 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1477 pkt_len -= ETH_FCS_LEN;
1478 #endif
1479
1480 if (netif_msg_rx_status(lp))
1481 dump_rxfd(lp->rfd_cur);
1482 if (status & Rx_Good) {
1483 struct sk_buff *skb;
1484 unsigned char *data;
1485 int cur_bd;
1486
1487 if (--limit < 0)
1488 break;
1489 BUG_ON(bd_count > 1);
1490 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1491 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1492 #ifdef DEBUG
1493 if (cur_bd >= RX_BUF_NUM) {
1494 printk("%s: invalid BDID.\n", dev->name);
1495 panic_queues(dev);
1496 }
1497 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1498 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1499 if (!lp->rx_skbs[cur_bd].skb) {
1500 printk("%s: NULL skb.\n", dev->name);
1501 panic_queues(dev);
1502 }
1503 #else
1504 BUG_ON(cur_bd >= RX_BUF_NUM);
1505 #endif
1506 skb = lp->rx_skbs[cur_bd].skb;
1507 prefetch(skb->data);
1508 lp->rx_skbs[cur_bd].skb = NULL;
1509 dma_unmap_single(&lp->pci_dev->dev,
1510 lp->rx_skbs[cur_bd].skb_dma,
1511 RX_BUF_SIZE, DMA_FROM_DEVICE);
1512 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN != 0)
1513 memmove(skb->data, skb->data - NET_IP_ALIGN,
1514 pkt_len);
1515 data = skb_put(skb, pkt_len);
1516 if (netif_msg_pktdata(lp))
1517 print_eth(data);
1518 skb->protocol = eth_type_trans(skb, dev);
1519 netif_receive_skb(skb);
1520 received++;
1521 dev->stats.rx_packets++;
1522 dev->stats.rx_bytes += pkt_len;
1523 } else {
1524 dev->stats.rx_errors++;
1525 if (netif_msg_rx_err(lp))
1526 dev_info(&dev->dev, "Rx error (status %x)\n",
1527 status & Rx_Stat_Mask);
1528 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1529 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1530 status &= ~(Rx_LongErr|Rx_CRCErr);
1531 status |= Rx_Over;
1532 }
1533 if (status & Rx_LongErr)
1534 dev->stats.rx_length_errors++;
1535 if (status & Rx_Over)
1536 dev->stats.rx_fifo_errors++;
1537 if (status & Rx_CRCErr)
1538 dev->stats.rx_crc_errors++;
1539 if (status & Rx_Align)
1540 dev->stats.rx_frame_errors++;
1541 }
1542
1543 if (bd_count > 0) {
1544 /* put Free Buffer back to controller */
1545 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1546 unsigned char id =
1547 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1548 #ifdef DEBUG
1549 if (id >= RX_BUF_NUM) {
1550 printk("%s: invalid BDID.\n", dev->name);
1551 panic_queues(dev);
1552 }
1553 #else
1554 BUG_ON(id >= RX_BUF_NUM);
1555 #endif
1556 /* free old buffers */
1557 lp->fbl_count--;
1558 while (lp->fbl_count < RX_BUF_NUM)
1559 {
1560 unsigned char curid =
1561 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1562 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1563 #ifdef DEBUG
1564 bdctl = le32_to_cpu(bd->BDCtl);
1565 if (bdctl & BD_CownsBD) {
1566 printk("%s: Freeing invalid BD.\n",
1567 dev->name);
1568 panic_queues(dev);
1569 }
1570 #endif
1571 /* pass BD to controller */
1572 if (!lp->rx_skbs[curid].skb) {
1573 lp->rx_skbs[curid].skb =
1574 alloc_rxbuf_skb(dev,
1575 lp->pci_dev,
1576 &lp->rx_skbs[curid].skb_dma);
1577 if (!lp->rx_skbs[curid].skb)
1578 break; /* try on next reception */
1579 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1580 }
1581 /* Note: BDLength was modified by chip. */
1582 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1583 (curid << BD_RxBDID_SHIFT) |
1584 RX_BUF_SIZE);
1585 lp->fbl_count++;
1586 }
1587 }
1588
1589 /* put RxFD back to controller */
1590 #ifdef DEBUG
1591 next_rfd = fd_bus_to_virt(lp,
1592 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1593 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1594 printk("%s: RxFD FDNext invalid.\n", dev->name);
1595 panic_queues(dev);
1596 }
1597 #endif
1598 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1599 /* pass FD to controller */
1600 #ifdef DEBUG
1601 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1602 #else
1603 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1604 #endif
1605 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1606 lp->rfd_cur++;
1607 }
1608 if (lp->rfd_cur > lp->rfd_limit)
1609 lp->rfd_cur = lp->rfd_base;
1610 #ifdef DEBUG
1611 if (lp->rfd_cur != next_rfd)
1612 printk("rfd_cur = %p, next_rfd %p\n",
1613 lp->rfd_cur, next_rfd);
1614 #endif
1615 }
1616
1617 return received;
1618 }
1619
1620 static int tc35815_poll(struct napi_struct *napi, int budget)
1621 {
1622 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1623 struct net_device *dev = lp->dev;
1624 struct tc35815_regs __iomem *tr =
1625 (struct tc35815_regs __iomem *)dev->base_addr;
1626 int received = 0, handled;
1627 u32 status;
1628
1629 if (budget <= 0)
1630 return received;
1631
1632 spin_lock(&lp->rx_lock);
1633 status = tc_readl(&tr->Int_Src);
1634 do {
1635 /* BLEx, FDAEx will be cleared later */
1636 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1637 &tr->Int_Src); /* write to clear */
1638
1639 handled = tc35815_do_interrupt(dev, status, budget - received);
1640 if (status & (Int_BLEx | Int_FDAEx))
1641 tc_writel(status & (Int_BLEx | Int_FDAEx),
1642 &tr->Int_Src);
1643 if (handled >= 0) {
1644 received += handled;
1645 if (received >= budget)
1646 break;
1647 }
1648 status = tc_readl(&tr->Int_Src);
1649 } while (status);
1650 spin_unlock(&lp->rx_lock);
1651
1652 if (received < budget) {
1653 napi_complete_done(napi, received);
1654 /* enable interrupts */
1655 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1656 }
1657 return received;
1658 }
1659
1660 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1661
1662 static void
1663 tc35815_check_tx_stat(struct net_device *dev, int status)
1664 {
1665 struct tc35815_local *lp = netdev_priv(dev);
1666 const char *msg = NULL;
1667
1668 /* count collisions */
1669 if (status & Tx_ExColl)
1670 dev->stats.collisions += 16;
1671 if (status & Tx_TxColl_MASK)
1672 dev->stats.collisions += status & Tx_TxColl_MASK;
1673
1674 /* TX4939 does not have NCarr */
1675 if (lp->chiptype == TC35815_TX4939)
1676 status &= ~Tx_NCarr;
1677 /* WORKAROUND: ignore LostCrS in full duplex operation */
1678 if (!lp->link || lp->duplex == DUPLEX_FULL)
1679 status &= ~Tx_NCarr;
1680
1681 if (!(status & TX_STA_ERR)) {
1682 /* no error. */
1683 dev->stats.tx_packets++;
1684 return;
1685 }
1686
1687 dev->stats.tx_errors++;
1688 if (status & Tx_ExColl) {
1689 dev->stats.tx_aborted_errors++;
1690 msg = "Excessive Collision.";
1691 }
1692 if (status & Tx_Under) {
1693 dev->stats.tx_fifo_errors++;
1694 msg = "Tx FIFO Underrun.";
1695 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1696 lp->lstats.tx_underrun++;
1697 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1698 struct tc35815_regs __iomem *tr =
1699 (struct tc35815_regs __iomem *)dev->base_addr;
1700 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1701 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1702 }
1703 }
1704 }
1705 if (status & Tx_Defer) {
1706 dev->stats.tx_fifo_errors++;
1707 msg = "Excessive Deferral.";
1708 }
1709 if (status & Tx_NCarr) {
1710 dev->stats.tx_carrier_errors++;
1711 msg = "Lost Carrier Sense.";
1712 }
1713 if (status & Tx_LateColl) {
1714 dev->stats.tx_aborted_errors++;
1715 msg = "Late Collision.";
1716 }
1717 if (status & Tx_TxPar) {
1718 dev->stats.tx_fifo_errors++;
1719 msg = "Transmit Parity Error.";
1720 }
1721 if (status & Tx_SQErr) {
1722 dev->stats.tx_heartbeat_errors++;
1723 msg = "Signal Quality Error.";
1724 }
1725 if (msg && netif_msg_tx_err(lp))
1726 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1727 }
1728
1729 /* This handles TX complete events posted by the device
1730 * via interrupts.
1731 */
1732 static void
1733 tc35815_txdone(struct net_device *dev)
1734 {
1735 struct tc35815_local *lp = netdev_priv(dev);
1736 struct TxFD *txfd;
1737 unsigned int fdctl;
1738
1739 txfd = &lp->tfd_base[lp->tfd_end];
1740 while (lp->tfd_start != lp->tfd_end &&
1741 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1742 int status = le32_to_cpu(txfd->fd.FDStat);
1743 struct sk_buff *skb;
1744 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1745 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1746
1747 if (netif_msg_tx_done(lp)) {
1748 printk("%s: complete TxFD.\n", dev->name);
1749 dump_txfd(txfd);
1750 }
1751 tc35815_check_tx_stat(dev, status);
1752
1753 skb = fdsystem != 0xffffffff ?
1754 lp->tx_skbs[fdsystem].skb : NULL;
1755 #ifdef DEBUG
1756 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1757 printk("%s: tx_skbs mismatch.\n", dev->name);
1758 panic_queues(dev);
1759 }
1760 #else
1761 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1762 #endif
1763 if (skb) {
1764 dev->stats.tx_bytes += skb->len;
1765 dma_unmap_single(&lp->pci_dev->dev,
1766 lp->tx_skbs[lp->tfd_end].skb_dma,
1767 skb->len, DMA_TO_DEVICE);
1768 lp->tx_skbs[lp->tfd_end].skb = NULL;
1769 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1770 dev_kfree_skb_any(skb);
1771 }
1772 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1773
1774 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1775 txfd = &lp->tfd_base[lp->tfd_end];
1776 #ifdef DEBUG
1777 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1778 printk("%s: TxFD FDNext invalid.\n", dev->name);
1779 panic_queues(dev);
1780 }
1781 #endif
1782 if (fdnext & FD_Next_EOL) {
1783 /* DMA Transmitter has been stopping... */
1784 if (lp->tfd_end != lp->tfd_start) {
1785 struct tc35815_regs __iomem *tr =
1786 (struct tc35815_regs __iomem *)dev->base_addr;
1787 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1788 struct TxFD *txhead = &lp->tfd_base[head];
1789 int qlen = (lp->tfd_start + TX_FD_NUM
1790 - lp->tfd_end) % TX_FD_NUM;
1791
1792 #ifdef DEBUG
1793 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1794 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1795 panic_queues(dev);
1796 }
1797 #endif
1798 /* log max queue length */
1799 if (lp->lstats.max_tx_qlen < qlen)
1800 lp->lstats.max_tx_qlen = qlen;
1801
1802
1803 /* start DMA Transmitter again */
1804 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1805 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1806 if (netif_msg_tx_queued(lp)) {
1807 printk("%s: start TxFD on queue.\n",
1808 dev->name);
1809 dump_txfd(txfd);
1810 }
1811 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1812 }
1813 break;
1814 }
1815 }
1816
1817 /* If we had stopped the queue due to a "tx full"
1818 * condition, and space has now been made available,
1819 * wake up the queue.
1820 */
1821 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1822 netif_wake_queue(dev);
1823 }
1824
1825 /* The inverse routine to tc35815_open(). */
1826 static int
1827 tc35815_close(struct net_device *dev)
1828 {
1829 struct tc35815_local *lp = netdev_priv(dev);
1830
1831 netif_stop_queue(dev);
1832 napi_disable(&lp->napi);
1833 if (dev->phydev)
1834 phy_stop(dev->phydev);
1835 cancel_work_sync(&lp->restart_work);
1836
1837 /* Flush the Tx and disable Rx here. */
1838 tc35815_chip_reset(dev);
1839 free_irq(dev->irq, dev);
1840
1841 tc35815_free_queues(dev);
1842
1843 return 0;
1844
1845 }
1846
1847 /*
1848 * Get the current statistics.
1849 * This may be called with the card open or closed.
1850 */
1851 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1852 {
1853 struct tc35815_regs __iomem *tr =
1854 (struct tc35815_regs __iomem *)dev->base_addr;
1855 if (netif_running(dev))
1856 /* Update the statistics from the device registers. */
1857 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1858
1859 return &dev->stats;
1860 }
1861
1862 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1863 {
1864 struct tc35815_local *lp = netdev_priv(dev);
1865 struct tc35815_regs __iomem *tr =
1866 (struct tc35815_regs __iomem *)dev->base_addr;
1867 int cam_index = index * 6;
1868 u32 cam_data;
1869 u32 saved_addr;
1870
1871 saved_addr = tc_readl(&tr->CAM_Adr);
1872
1873 if (netif_msg_hw(lp))
1874 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1875 dev->name, index, addr);
1876 if (index & 1) {
1877 /* read modify write */
1878 tc_writel(cam_index - 2, &tr->CAM_Adr);
1879 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1880 cam_data |= addr[0] << 8 | addr[1];
1881 tc_writel(cam_data, &tr->CAM_Data);
1882 /* write whole word */
1883 tc_writel(cam_index + 2, &tr->CAM_Adr);
1884 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1885 tc_writel(cam_data, &tr->CAM_Data);
1886 } else {
1887 /* write whole word */
1888 tc_writel(cam_index, &tr->CAM_Adr);
1889 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1890 tc_writel(cam_data, &tr->CAM_Data);
1891 /* read modify write */
1892 tc_writel(cam_index + 4, &tr->CAM_Adr);
1893 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1894 cam_data |= addr[4] << 24 | (addr[5] << 16);
1895 tc_writel(cam_data, &tr->CAM_Data);
1896 }
1897
1898 tc_writel(saved_addr, &tr->CAM_Adr);
1899 }
1900
1901
1902 /*
1903 * Set or clear the multicast filter for this adaptor.
1904 * num_addrs == -1 Promiscuous mode, receive all packets
1905 * num_addrs == 0 Normal mode, clear multicast list
1906 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1907 * and do best-effort filtering.
1908 */
1909 static void
1910 tc35815_set_multicast_list(struct net_device *dev)
1911 {
1912 struct tc35815_regs __iomem *tr =
1913 (struct tc35815_regs __iomem *)dev->base_addr;
1914
1915 if (dev->flags & IFF_PROMISC) {
1916 /* With some (all?) 100MHalf HUB, controller will hang
1917 * if we enabled promiscuous mode before linkup... */
1918 struct tc35815_local *lp = netdev_priv(dev);
1919
1920 if (!lp->link)
1921 return;
1922 /* Enable promiscuous mode */
1923 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1924 } else if ((dev->flags & IFF_ALLMULTI) ||
1925 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1926 /* CAM 0, 1, 20 are reserved. */
1927 /* Disable promiscuous mode, use normal mode. */
1928 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1929 } else if (!netdev_mc_empty(dev)) {
1930 struct netdev_hw_addr *ha;
1931 int i;
1932 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1933
1934 tc_writel(0, &tr->CAM_Ctl);
1935 /* Walk the address list, and load the filter */
1936 i = 0;
1937 netdev_for_each_mc_addr(ha, dev) {
1938 /* entry 0,1 is reserved. */
1939 tc35815_set_cam_entry(dev, i + 2, ha->addr);
1940 ena_bits |= CAM_Ena_Bit(i + 2);
1941 i++;
1942 }
1943 tc_writel(ena_bits, &tr->CAM_Ena);
1944 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1945 } else {
1946 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1947 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1948 }
1949 }
1950
1951 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1952 {
1953 struct tc35815_local *lp = netdev_priv(dev);
1954
1955 strlcpy(info->driver, MODNAME, sizeof(info->driver));
1956 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1957 strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
1958 }
1959
1960 static u32 tc35815_get_msglevel(struct net_device *dev)
1961 {
1962 struct tc35815_local *lp = netdev_priv(dev);
1963 return lp->msg_enable;
1964 }
1965
1966 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
1967 {
1968 struct tc35815_local *lp = netdev_priv(dev);
1969 lp->msg_enable = datum;
1970 }
1971
1972 static int tc35815_get_sset_count(struct net_device *dev, int sset)
1973 {
1974 struct tc35815_local *lp = netdev_priv(dev);
1975
1976 switch (sset) {
1977 case ETH_SS_STATS:
1978 return sizeof(lp->lstats) / sizeof(int);
1979 default:
1980 return -EOPNOTSUPP;
1981 }
1982 }
1983
1984 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
1985 {
1986 struct tc35815_local *lp = netdev_priv(dev);
1987 data[0] = lp->lstats.max_tx_qlen;
1988 data[1] = lp->lstats.tx_ints;
1989 data[2] = lp->lstats.rx_ints;
1990 data[3] = lp->lstats.tx_underrun;
1991 }
1992
1993 static struct {
1994 const char str[ETH_GSTRING_LEN];
1995 } ethtool_stats_keys[] = {
1996 { "max_tx_qlen" },
1997 { "tx_ints" },
1998 { "rx_ints" },
1999 { "tx_underrun" },
2000 };
2001
2002 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2003 {
2004 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2005 }
2006
2007 static const struct ethtool_ops tc35815_ethtool_ops = {
2008 .get_drvinfo = tc35815_get_drvinfo,
2009 .get_link = ethtool_op_get_link,
2010 .get_msglevel = tc35815_get_msglevel,
2011 .set_msglevel = tc35815_set_msglevel,
2012 .get_strings = tc35815_get_strings,
2013 .get_sset_count = tc35815_get_sset_count,
2014 .get_ethtool_stats = tc35815_get_ethtool_stats,
2015 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2016 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2017 };
2018
2019 static void tc35815_chip_reset(struct net_device *dev)
2020 {
2021 struct tc35815_regs __iomem *tr =
2022 (struct tc35815_regs __iomem *)dev->base_addr;
2023 int i;
2024 /* reset the controller */
2025 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2026 udelay(4); /* 3200ns */
2027 i = 0;
2028 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2029 if (i++ > 100) {
2030 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2031 break;
2032 }
2033 mdelay(1);
2034 }
2035 tc_writel(0, &tr->MAC_Ctl);
2036
2037 /* initialize registers to default value */
2038 tc_writel(0, &tr->DMA_Ctl);
2039 tc_writel(0, &tr->TxThrsh);
2040 tc_writel(0, &tr->TxPollCtr);
2041 tc_writel(0, &tr->RxFragSize);
2042 tc_writel(0, &tr->Int_En);
2043 tc_writel(0, &tr->FDA_Bas);
2044 tc_writel(0, &tr->FDA_Lim);
2045 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2046 tc_writel(0, &tr->CAM_Ctl);
2047 tc_writel(0, &tr->Tx_Ctl);
2048 tc_writel(0, &tr->Rx_Ctl);
2049 tc_writel(0, &tr->CAM_Ena);
2050 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2051
2052 /* initialize internal SRAM */
2053 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2054 for (i = 0; i < 0x1000; i += 4) {
2055 tc_writel(i, &tr->CAM_Adr);
2056 tc_writel(0, &tr->CAM_Data);
2057 }
2058 tc_writel(0, &tr->DMA_Ctl);
2059 }
2060
2061 static void tc35815_chip_init(struct net_device *dev)
2062 {
2063 struct tc35815_local *lp = netdev_priv(dev);
2064 struct tc35815_regs __iomem *tr =
2065 (struct tc35815_regs __iomem *)dev->base_addr;
2066 unsigned long txctl = TX_CTL_CMD;
2067
2068 /* load station address to CAM */
2069 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2070
2071 /* Enable CAM (broadcast and unicast) */
2072 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2073 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2074
2075 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2076 if (HAVE_DMA_RXALIGN(lp))
2077 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2078 else
2079 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2080 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2081 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2082 tc_writel(INT_EN_CMD, &tr->Int_En);
2083
2084 /* set queues */
2085 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2086 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2087 &tr->FDA_Lim);
2088 /*
2089 * Activation method:
2090 * First, enable the MAC Transmitter and the DMA Receive circuits.
2091 * Then enable the DMA Transmitter and the MAC Receive circuits.
2092 */
2093 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2094 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2095
2096 /* start MAC transmitter */
2097 /* TX4939 does not have EnLCarr */
2098 if (lp->chiptype == TC35815_TX4939)
2099 txctl &= ~Tx_EnLCarr;
2100 /* WORKAROUND: ignore LostCrS in full duplex operation */
2101 if (!dev->phydev || !lp->link || lp->duplex == DUPLEX_FULL)
2102 txctl &= ~Tx_EnLCarr;
2103 tc_writel(txctl, &tr->Tx_Ctl);
2104 }
2105
2106 #ifdef CONFIG_PM
2107 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2108 {
2109 struct net_device *dev = pci_get_drvdata(pdev);
2110 struct tc35815_local *lp = netdev_priv(dev);
2111 unsigned long flags;
2112
2113 pci_save_state(pdev);
2114 if (!netif_running(dev))
2115 return 0;
2116 netif_device_detach(dev);
2117 if (dev->phydev)
2118 phy_stop(dev->phydev);
2119 spin_lock_irqsave(&lp->lock, flags);
2120 tc35815_chip_reset(dev);
2121 spin_unlock_irqrestore(&lp->lock, flags);
2122 pci_set_power_state(pdev, PCI_D3hot);
2123 return 0;
2124 }
2125
2126 static int tc35815_resume(struct pci_dev *pdev)
2127 {
2128 struct net_device *dev = pci_get_drvdata(pdev);
2129
2130 pci_restore_state(pdev);
2131 if (!netif_running(dev))
2132 return 0;
2133 pci_set_power_state(pdev, PCI_D0);
2134 tc35815_restart(dev);
2135 netif_carrier_off(dev);
2136 if (dev->phydev)
2137 phy_start(dev->phydev);
2138 netif_device_attach(dev);
2139 return 0;
2140 }
2141 #endif /* CONFIG_PM */
2142
2143 static struct pci_driver tc35815_pci_driver = {
2144 .name = MODNAME,
2145 .id_table = tc35815_pci_tbl,
2146 .probe = tc35815_init_one,
2147 .remove = tc35815_remove_one,
2148 #ifdef CONFIG_PM
2149 .suspend = tc35815_suspend,
2150 .resume = tc35815_resume,
2151 #endif
2152 };
2153
2154 module_param_named(speed, options.speed, int, 0);
2155 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2156 module_param_named(duplex, options.duplex, int, 0);
2157 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2158
2159 module_pci_driver(tc35815_pci_driver);
2160 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2161 MODULE_LICENSE("GPL");
Linux with added FPC-III support