1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Driver for Microsemi VSC85xx PHYs
5 * Copyright (C) 2020 Microsemi Corporation
8 #ifndef _MSCC_PHY_FC_BUFFER_H_
9 #define _MSCC_PHY_FC_BUFFER_H_
11 #define MSCC_FCBUF_ENA_CFG 0x00
12 #define MSCC_FCBUF_MODE_CFG 0x01
13 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG 0x02
14 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG 0x03
15 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG 0x04
16 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG 0x05
17 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG 0x06
18 #define MSCC_FCBUF_FC_READ_THRESH_CFG 0x07
19 #define MSCC_FCBUF_TX_FRM_GAP_COMP 0x08
21 #define MSCC_FCBUF_ENA_CFG_TX_ENA BIT(0)
22 #define MSCC_FCBUF_ENA_CFG_RX_ENA BIT(4)
24 #define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR BIT(4)
25 #define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA BIT(8)
26 #define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA BIT(12)
27 #define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA BIT(16)
28 #define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA BIT(20)
29 #define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA BIT(24)
30 #define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN BIT(28)
32 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x) (x)
33 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)
34 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x) ((x) << 16)
35 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M GENMASK(19, 16)
36 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x) ((x) << 20)
37 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M GENMASK(31, 20)
39 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x) (x)
40 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M GENMASK(15, 0)
41 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x) ((x) << 16)
42 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M GENMASK(31, 16)
44 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x) (x)
45 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)
46 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x) ((x) << 16)
47 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)
49 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x) (x)
50 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)
51 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x) ((x) << 16)
52 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)
54 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x) (x)
55 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M GENMASK(15, 0)
56 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x) ((x) << 16)
57 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16)
59 #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x) (x)
60 #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)
61 #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x) ((x) << 16)
62 #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16)
64 #endif /* _MSCC_PHY_FC_BUFFER_H_ */