drivers/net/usb/sr9700.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices
   4  *
   5  * Author : Liu Junliang <liujunliang_ljl@163.com>
   6  */
   7
   8 #ifndef _SR9700_H
   9 #define _SR9700_H
  10
  11 /* sr9700 spec. register table on Linux platform */
  12
  13 /* Network Control Reg */
  14 #define SR_NCR                  0x00
  15 #define         NCR_RST                 (1 << 0)
  16 #define         NCR_LBK                 (3 << 1)
  17 #define         NCR_FDX                 (1 << 3)
  18 #define         NCR_WAKEEN              (1 << 6)
  19 /* Network Status Reg */
  20 #define SR_NSR                  0x01
  21 #define         NSR_RXRDY               (1 << 0)
  22 #define         NSR_RXOV                (1 << 1)
  23 #define         NSR_TX1END              (1 << 2)
  24 #define         NSR_TX2END              (1 << 3)
  25 #define         NSR_TXFULL              (1 << 4)
  26 #define         NSR_WAKEST              (1 << 5)
  27 #define         NSR_LINKST              (1 << 6)
  28 #define         NSR_SPEED               (1 << 7)
  29 /* Tx Control Reg */
  30 #define SR_TCR                  0x02
  31 #define         TCR_CRC_DIS             (1 << 1)
  32 #define         TCR_PAD_DIS             (1 << 2)
  33 #define         TCR_LC_CARE             (1 << 3)
  34 #define         TCR_CRS_CARE    (1 << 4)
  35 #define         TCR_EXCECM              (1 << 5)
  36 #define         TCR_LF_EN               (1 << 6)
  37 /* Tx Status Reg for Packet Index 1 */
  38 #define SR_TSR1         0x03
  39 #define         TSR1_EC                 (1 << 2)
  40 #define         TSR1_COL                (1 << 3)
  41 #define         TSR1_LC                 (1 << 4)
  42 #define         TSR1_NC                 (1 << 5)
  43 #define         TSR1_LOC                (1 << 6)
  44 #define         TSR1_TLF                (1 << 7)
  45 /* Tx Status Reg for Packet Index 2 */
  46 #define SR_TSR2         0x04
  47 #define         TSR2_EC                 (1 << 2)
  48 #define         TSR2_COL                (1 << 3)
  49 #define         TSR2_LC                 (1 << 4)
  50 #define         TSR2_NC                 (1 << 5)
  51 #define         TSR2_LOC                (1 << 6)
  52 #define         TSR2_TLF                (1 << 7)
  53 /* Rx Control Reg*/
  54 #define SR_RCR                  0x05
  55 #define         RCR_RXEN                (1 << 0)
  56 #define         RCR_PRMSC               (1 << 1)
  57 #define         RCR_RUNT                (1 << 2)
  58 #define         RCR_ALL                 (1 << 3)
  59 #define         RCR_DIS_CRC             (1 << 4)
  60 #define         RCR_DIS_LONG    (1 << 5)
  61 /* Rx Status Reg */
  62 #define SR_RSR                  0x06
  63 #define         RSR_AE                  (1 << 2)
  64 #define         RSR_MF                  (1 << 6)
  65 #define         RSR_RF                  (1 << 7)
  66 /* Rx Overflow Counter Reg */
  67 #define SR_ROCR         0x07
  68 #define         ROCR_ROC                (0x7F << 0)
  69 #define         ROCR_RXFU               (1 << 7)
  70 /* Back Pressure Threshold Reg */
  71 #define SR_BPTR         0x08
  72 #define         BPTR_JPT                (0x0F << 0)
  73 #define         BPTR_BPHW               (0x0F << 4)
  74 /* Flow Control Threshold Reg */
  75 #define SR_FCTR         0x09
  76 #define         FCTR_LWOT               (0x0F << 0)
  77 #define         FCTR_HWOT               (0x0F << 4)
  78 /* rx/tx Flow Control Reg */
  79 #define SR_FCR                  0x0A
  80 #define         FCR_FLCE                (1 << 0)
  81 #define         FCR_BKPA                (1 << 4)
  82 #define         FCR_TXPEN               (1 << 5)
  83 #define         FCR_TXPF                (1 << 6)
  84 #define         FCR_TXP0                (1 << 7)
  85 /* Eeprom & Phy Control Reg */
  86 #define SR_EPCR         0x0B
  87 #define         EPCR_ERRE               (1 << 0)
  88 #define         EPCR_ERPRW              (1 << 1)
  89 #define         EPCR_ERPRR              (1 << 2)
  90 #define         EPCR_EPOS               (1 << 3)
  91 #define         EPCR_WEP                (1 << 4)
  92 /* Eeprom & Phy Address Reg */
  93 #define SR_EPAR         0x0C
  94 #define         EPAR_EROA               (0x3F << 0)
  95 #define         EPAR_PHY_ADR_MASK       (0x03 << 6)
  96 #define         EPAR_PHY_ADR            (0x01 << 6)
  97 /* Eeprom &     Phy Data Reg */
  98 #define SR_EPDR         0x0D    /* 0x0D ~ 0x0E for Data Reg Low & High */
  99 /* Wakeup Control Reg */
 100 #define SR_WCR                  0x0F
 101 #define         WCR_MAGICST             (1 << 0)
 102 #define         WCR_LINKST              (1 << 2)
 103 #define         WCR_MAGICEN             (1 << 3)
 104 #define         WCR_LINKEN              (1 << 5)
 105 /* Physical Address Reg */
 106 #define SR_PAR                  0x10    /* 0x10 ~ 0x15 6 bytes for PAR */
 107 /* Multicast Address Reg */
 108 #define SR_MAR                  0x16    /* 0x16 ~ 0x1D 8 bytes for MAR */
 109 /* 0x1e unused */
 110 /* Phy Reset Reg */
 111 #define SR_PRR                  0x1F
 112 #define         PRR_PHY_RST             (1 << 0)
 113 /* Tx sdram Write Pointer Address Low */
 114 #define SR_TWPAL                0x20
 115 /* Tx sdram Write Pointer Address High */
 116 #define SR_TWPAH                0x21
 117 /* Tx sdram Read Pointer Address Low */
 118 #define SR_TRPAL                0x22
 119 /* Tx sdram Read Pointer Address High */
 120 #define SR_TRPAH                0x23
 121 /* Rx sdram Write Pointer Address Low */
 122 #define SR_RWPAL                0x24
 123 /* Rx sdram Write Pointer Address High */
 124 #define SR_RWPAH                0x25
 125 /* Rx sdram Read Pointer Address Low */
 126 #define SR_RRPAL                0x26
 127 /* Rx sdram Read Pointer Address High */
 128 #define SR_RRPAH                0x27
 129 /* Vendor ID register */
 130 #define SR_VID                  0x28    /* 0x28 ~ 0x29 2 bytes for VID */
 131 /* Product ID register */
 132 #define SR_PID                  0x2A    /* 0x2A ~ 0x2B 2 bytes for PID */
 133 /* CHIP Revision register */
 134 #define SR_CHIPR                0x2C
 135 /* 0x2D --> 0xEF unused */
 136 /* USB Device Address */
 137 #define SR_USBDA                0xF0
 138 #define         USBDA_USBFA             (0x7F << 0)
 139 /* RX packet Counter Reg */
 140 #define SR_RXC                  0xF1
 141 /* Tx packet Counter & USB Status Reg */
 142 #define SR_TXC_USBS             0xF2
 143 #define         TXC_USBS_TXC0           (1 << 0)
 144 #define         TXC_USBS_TXC1           (1 << 1)
 145 #define         TXC_USBS_TXC2           (1 << 2)
 146 #define         TXC_USBS_EP1RDY         (1 << 5)
 147 #define         TXC_USBS_SUSFLAG        (1 << 6)
 148 #define         TXC_USBS_RXFAULT        (1 << 7)
 149 /* USB Control register */
 150 #define SR_USBC                 0xF4
 151 #define         USBC_EP3NAK             (1 << 4)
 152 #define         USBC_EP3ACK             (1 << 5)
 153
 154 /* Register access commands and flags */
 155 #define SR_RD_REGS              0x00
 156 #define SR_WR_REGS              0x01
 157 #define SR_WR_REG               0x03
 158 #define SR_REQ_RD_REG   (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
 159 #define SR_REQ_WR_REG   (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
 160
 161 /* parameters */
 162 #define SR_SHARE_TIMEOUT        1000
 163 #define SR_EEPROM_LEN           256
 164 #define SR_MCAST_SIZE           8
 165 #define SR_MCAST_ADDR_FLAG      0x80
 166 #define SR_MCAST_MAX            64
 167 #define SR_TX_OVERHEAD          2       /* 2bytes header */
 168 #define SR_RX_OVERHEAD          7       /* 3bytes header + 4crc tail */
 169
 170 #endif  /* _SR9700_H */