drivers/net/wireless/ath/ath.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH_H
  18 #define ATH_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/skbuff.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/spinlock.h>
  24 #include <net/mac80211.h>
  25
  26 /*
  27  * The key cache is used for h/w cipher state and also for
  28  * tracking station state such as the current tx antenna.
  29  * We also setup a mapping table between key cache slot indices
  30  * and station state to short-circuit node lookups on rx.
  31  * Different parts have different size key caches.  We handle
  32  * up to ATH_KEYMAX entries (could dynamically allocate state).
  33  */
  34 #define ATH_KEYMAX              128     /* max key cache size we handle */
  35
  36 struct ath_ani {
  37         bool caldone;
  38         unsigned int longcal_timer;
  39         unsigned int shortcal_timer;
  40         unsigned int resetcal_timer;
  41         unsigned int checkani_timer;
  42         struct timer_list timer;
  43 };
  44
  45 struct ath_cycle_counters {
  46         u32 cycles;
  47         u32 rx_busy;
  48         u32 rx_frame;
  49         u32 tx_frame;
  50 };
  51
  52 enum ath_device_state {
  53         ATH_HW_UNAVAILABLE,
  54         ATH_HW_INITIALIZED,
  55 };
  56
  57 enum ath_op_flags {
  58         ATH_OP_INVALID,
  59         ATH_OP_BEACONS,
  60         ATH_OP_ANI_RUN,
  61         ATH_OP_PRIM_STA_VIF,
  62         ATH_OP_HW_RESET,
  63         ATH_OP_SCANNING,
  64         ATH_OP_MULTI_CHANNEL,
  65         ATH_OP_WOW_ENABLED,
  66 };
  67
  68 enum ath_bus_type {
  69         ATH_PCI,
  70         ATH_AHB,
  71         ATH_USB,
  72 };
  73
  74 struct reg_dmn_pair_mapping {
  75         u16 reg_domain;
  76         u16 reg_5ghz_ctl;
  77         u16 reg_2ghz_ctl;
  78 };
  79
  80 struct ath_regulatory {
  81         char alpha2[2];
  82         enum nl80211_dfs_regions region;
  83         u16 country_code;
  84         u16 max_power_level;
  85         u16 current_rd;
  86         int16_t power_limit;
  87         struct reg_dmn_pair_mapping *regpair;
  88 };
  89
  90 enum ath_crypt_caps {
  91         ATH_CRYPT_CAP_CIPHER_AESCCM             = BIT(0),
  92         ATH_CRYPT_CAP_MIC_COMBINED              = BIT(1),
  93 };
  94
  95 struct ath_keyval {
  96         u8 kv_type;
  97         u8 kv_pad;
  98         u16 kv_len;
  99         u8 kv_val[16]; /* TK */
 100         u8 kv_mic[8]; /* Michael MIC key */
 101         u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
 102                          * supports both MIC keys in the same key cache entry;
 103                          * in that case, kv_mic is the RX key) */
 104 };
 105
 106 enum ath_cipher {
 107         ATH_CIPHER_WEP = 0,
 108         ATH_CIPHER_AES_OCB = 1,
 109         ATH_CIPHER_AES_CCM = 2,
 110         ATH_CIPHER_CKIP = 3,
 111         ATH_CIPHER_TKIP = 4,
 112         ATH_CIPHER_CLR = 5,
 113         ATH_CIPHER_MIC = 127
 114 };
 115
 116 /**
 117  * struct ath_ops - Register read/write operations
 118  *
 119  * @read: Register read
 120  * @multi_read: Multiple register read
 121  * @write: Register write
 122  * @enable_write_buffer: Enable multiple register writes
 123  * @write_flush: flush buffered register writes and disable buffering
 124  */
 125 struct ath_ops {
 126         unsigned int (*read)(void *, u32 reg_offset);
 127         void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
 128         void (*write)(void *, u32 val, u32 reg_offset);
 129         void (*enable_write_buffer)(void *);
 130         void (*write_flush) (void *);
 131         u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
 132         void (*enable_rmw_buffer)(void *);
 133         void (*rmw_flush) (void *);
 134
 135 };
 136
 137 struct ath_common;
 138 struct ath_bus_ops;
 139
 140 struct ath_ps_ops {
 141         void (*wakeup)(struct ath_common *common);
 142         void (*restore)(struct ath_common *common);
 143 };
 144
 145 struct ath_common {
 146         void *ah;
 147         void *priv;
 148         struct ieee80211_hw *hw;
 149         int debug_mask;
 150         enum ath_device_state state;
 151         unsigned long op_flags;
 152
 153         struct ath_ani ani;
 154
 155         u16 cachelsz;
 156         u16 curaid;
 157         u8 macaddr[ETH_ALEN];
 158         u8 curbssid[ETH_ALEN] __aligned(2);
 159         u8 bssidmask[ETH_ALEN];
 160
 161         u32 rx_bufsize;
 162
 163         u32 keymax;
 164         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 165         DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
 166         DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
 167         enum ath_crypt_caps crypt_caps;
 168
 169         unsigned int clockrate;
 170
 171         spinlock_t cc_lock;
 172         struct ath_cycle_counters cc_ani;
 173         struct ath_cycle_counters cc_survey;
 174
 175         struct ath_regulatory regulatory;
 176         struct ath_regulatory reg_world_copy;
 177         const struct ath_ops *ops;
 178         const struct ath_bus_ops *bus_ops;
 179         const struct ath_ps_ops *ps_ops;
 180
 181         bool btcoex_enabled;
 182         bool disable_ani;
 183         bool bt_ant_diversity;
 184
 185         int last_rssi;
 186         struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
 187 };
 188
 189 static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common)
 190 {
 191         return common->ps_ops;
 192 }
 193
 194 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
 195                                 u32 len,
 196                                 gfp_t gfp_mask);
 197 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);
 198
 199 void ath_hw_setbssidmask(struct ath_common *common);
 200 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
 201 int ath_key_config(struct ath_common *common,
 202                           struct ieee80211_vif *vif,
 203                           struct ieee80211_sta *sta,
 204                           struct ieee80211_key_conf *key);
 205 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
 206 void ath_hw_cycle_counters_update(struct ath_common *common);
 207 int32_t ath_hw_get_listen_time(struct ath_common *common);
 208
 209 __printf(3, 4)
 210 void ath_printk(const char *level, const struct ath_common *common,
 211                 const char *fmt, ...);
 212
 213 #define ath_emerg(common, fmt, ...)                             \
 214         ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
 215 #define ath_alert(common, fmt, ...)                             \
 216         ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
 217 #define ath_crit(common, fmt, ...)                              \
 218         ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
 219 #define ath_err(common, fmt, ...)                               \
 220         ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
 221 #define ath_warn(common, fmt, ...)                              \
 222         ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
 223 #define ath_notice(common, fmt, ...)                            \
 224         ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
 225 #define ath_info(common, fmt, ...)                              \
 226         ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
 227
 228 /**
 229  * enum ath_debug_level - atheros wireless debug level
 230  *
 231  * @ATH_DBG_RESET: reset processing
 232  * @ATH_DBG_QUEUE: hardware queue management
 233  * @ATH_DBG_EEPROM: eeprom processing
 234  * @ATH_DBG_CALIBRATE: periodic calibration
 235  * @ATH_DBG_INTERRUPT: interrupt processing
 236  * @ATH_DBG_REGULATORY: regulatory processing
 237  * @ATH_DBG_ANI: adaptive noise immunitive processing
 238  * @ATH_DBG_XMIT: basic xmit operation
 239  * @ATH_DBG_BEACON: beacon handling
 240  * @ATH_DBG_CONFIG: configuration of the hardware
 241  * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
 242  * @ATH_DBG_PS: power save processing
 243  * @ATH_DBG_HWTIMER: hardware timer handling
 244  * @ATH_DBG_BTCOEX: bluetooth coexistance
 245  * @ATH_DBG_BSTUCK: stuck beacons
 246  * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
 247  *      used exclusively for WLAN-BT coexistence starting from
 248  *      AR9462.
 249  * @ATH_DBG_DFS: radar datection
 250  * @ATH_DBG_WOW: Wake on Wireless
 251  * @ATH_DBG_DYNACK: dynack handling
 252  * @ATH_DBG_SPECTRAL_SCAN: FFT spectral scan
 253  * @ATH_DBG_ANY: enable all debugging
 254  *
 255  * The debug level is used to control the amount and type of debugging output
 256  * we want to see. Each driver has its own method for enabling debugging and
 257  * modifying debug level states -- but this is typically done through a
 258  * module parameter 'debug' along with a respective 'debug' debugfs file
 259  * entry.
 260  */
 261 enum ATH_DEBUG {
 262         ATH_DBG_RESET           = 0x00000001,
 263         ATH_DBG_QUEUE           = 0x00000002,
 264         ATH_DBG_EEPROM          = 0x00000004,
 265         ATH_DBG_CALIBRATE       = 0x00000008,
 266         ATH_DBG_INTERRUPT       = 0x00000010,
 267         ATH_DBG_REGULATORY      = 0x00000020,
 268         ATH_DBG_ANI             = 0x00000040,
 269         ATH_DBG_XMIT            = 0x00000080,
 270         ATH_DBG_BEACON          = 0x00000100,
 271         ATH_DBG_CONFIG          = 0x00000200,
 272         ATH_DBG_FATAL           = 0x00000400,
 273         ATH_DBG_PS              = 0x00000800,
 274         ATH_DBG_BTCOEX          = 0x00001000,
 275         ATH_DBG_WMI             = 0x00002000,
 276         ATH_DBG_BSTUCK          = 0x00004000,
 277         ATH_DBG_MCI             = 0x00008000,
 278         ATH_DBG_DFS             = 0x00010000,
 279         ATH_DBG_WOW             = 0x00020000,
 280         ATH_DBG_CHAN_CTX        = 0x00040000,
 281         ATH_DBG_DYNACK          = 0x00080000,
 282         ATH_DBG_SPECTRAL_SCAN   = 0x00100000,
 283         ATH_DBG_ANY             = 0xffffffff
 284 };
 285
 286 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
 287 #define ATH_DBG_MAX_LEN 512
 288
 289 #ifdef CONFIG_ATH_DEBUG
 290
 291 #define ath_dbg(common, dbg_mask, fmt, ...)                             \
 292 do {                                                                    \
 293         if ((common)->debug_mask & ATH_DBG_##dbg_mask)                  \
 294                 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__);     \
 295 } while (0)
 296
 297 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
 298 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
 299
 300 #else
 301
 302 static inline  __attribute__ ((format (printf, 3, 4)))
 303 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
 304              const char *fmt, ...)
 305 {
 306 }
 307 #define ath_dbg(common, dbg_mask, fmt, ...)                             \
 308         _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
 309
 310 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
 311 #define ATH_DBG_WARN_ON_ONCE(foo) ({                            \
 312         int __ret_warn_once = !!(foo);                          \
 313         unlikely(__ret_warn_once);                              \
 314 })
 315
 316 #endif /* CONFIG_ATH_DEBUG */
 317
 318 /** Returns string describing opmode, or NULL if unknown mode. */
 319 #ifdef CONFIG_ATH_DEBUG
 320 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
 321 #else
 322 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
 323 {
 324         return "UNKNOWN";
 325 }
 326 #endif
 327
 328 extern const char *ath_bus_type_strings[];
 329 static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype)
 330 {
 331         return ath_bus_type_strings[bustype];
 332 }
 333
 334 #endif /* ATH_H */