drivers/net/wireless/ath/ath11k/qmi.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef ATH11K_QMI_H
   7 #define ATH11K_QMI_H
   8
   9 #include <linux/mutex.h>
  10 #include <linux/soc/qcom/qmi.h>
  11
  12 #define ATH11K_HOST_VERSION_STRING              "WIN"
  13 #define ATH11K_QMI_WLANFW_TIMEOUT_MS            5000
  14 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE       64
  15 #define ATH11K_QMI_CALDB_ADDRESS                0x4BA00000
  16 #define ATH11K_QMI_BDF_MAX_SIZE                 (256 * 1024)
  17 #define ATH11K_QMI_CALDATA_OFFSET               (128 * 1024)
  18 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01  128
  19 #define ATH11K_QMI_WLFW_SERVICE_ID_V01          0x45
  20 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01        0x01
  21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01      0x02
  22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390      0x01
  23 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074      0x02
  24 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
  25 #define ATH11K_QMI_RESP_LEN_MAX                 8192
  26 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01   32
  27 #define ATH11K_QMI_CALDB_SIZE                   0x480000
  28 #define ATH11K_QMI_BDF_EXT_STR_LENGTH           0x20
  29
  30 #define QMI_WLFW_REQUEST_MEM_IND_V01            0x0035
  31 #define QMI_WLFW_FW_MEM_READY_IND_V01           0x0037
  32 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01     0x0021
  33 #define QMI_WLFW_FW_READY_IND_V01               0x0038
  34
  35 #define QMI_WLANFW_MAX_DATA_SIZE_V01            6144
  36 #define ATH11K_FIRMWARE_MODE_OFF                4
  37 #define ATH11K_QMI_TARGET_MEM_MODE_DEFAULT      0
  38 #define ATH11K_COLD_BOOT_FW_RESET_DELAY         (40 * HZ)
  39
  40 struct ath11k_base;
  41
  42 enum ath11k_qmi_file_type {
  43         ATH11K_QMI_FILE_TYPE_BDF_GOLDEN,
  44         ATH11K_QMI_FILE_TYPE_CALDATA,
  45         ATH11K_QMI_MAX_FILE_TYPE,
  46 };
  47
  48 enum ath11k_qmi_bdf_type {
  49         ATH11K_QMI_BDF_TYPE_BIN                 = 0,
  50         ATH11K_QMI_BDF_TYPE_ELF                 = 1,
  51 };
  52
  53 enum ath11k_qmi_event_type {
  54         ATH11K_QMI_EVENT_SERVER_ARRIVE,
  55         ATH11K_QMI_EVENT_SERVER_EXIT,
  56         ATH11K_QMI_EVENT_REQUEST_MEM,
  57         ATH11K_QMI_EVENT_FW_MEM_READY,
  58         ATH11K_QMI_EVENT_FW_READY,
  59         ATH11K_QMI_EVENT_COLD_BOOT_CAL_START,
  60         ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE,
  61         ATH11K_QMI_EVENT_REGISTER_DRIVER,
  62         ATH11K_QMI_EVENT_UNREGISTER_DRIVER,
  63         ATH11K_QMI_EVENT_RECOVERY,
  64         ATH11K_QMI_EVENT_FORCE_FW_ASSERT,
  65         ATH11K_QMI_EVENT_POWER_UP,
  66         ATH11K_QMI_EVENT_POWER_DOWN,
  67         ATH11K_QMI_EVENT_MAX,
  68 };
  69
  70 struct ath11k_qmi_driver_event {
  71         struct list_head list;
  72         enum ath11k_qmi_event_type type;
  73         void *data;
  74 };
  75
  76 struct ath11k_qmi_ce_cfg {
  77         const struct ce_pipe_config *tgt_ce;
  78         int tgt_ce_len;
  79         const struct service_to_pipe *svc_to_ce_map;
  80         int svc_to_ce_map_len;
  81         const u8 *shadow_reg;
  82         int shadow_reg_len;
  83         u32 *shadow_reg_v2;
  84         int shadow_reg_v2_len;
  85 };
  86
  87 struct ath11k_qmi_event_msg {
  88         struct list_head list;
  89         enum ath11k_qmi_event_type type;
  90 };
  91
  92 struct target_mem_chunk {
  93         u32 size;
  94         u32 type;
  95         dma_addr_t paddr;
  96         u32 *vaddr;
  97 };
  98
  99 struct target_info {
 100         u32 chip_id;
 101         u32 chip_family;
 102         u32 board_id;
 103         u32 soc_id;
 104         u32 fw_version;
 105         char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
 106         char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
 107         char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH];
 108 };
 109
 110 struct m3_mem_region {
 111         u32 size;
 112         dma_addr_t paddr;
 113         void *vaddr;
 114 };
 115
 116 struct ath11k_qmi {
 117         struct ath11k_base *ab;
 118         struct qmi_handle handle;
 119         struct sockaddr_qrtr sq;
 120         struct work_struct event_work;
 121         struct workqueue_struct *event_wq;
 122         struct list_head event_list;
 123         spinlock_t event_lock; /* spinlock for qmi event list */
 124         struct ath11k_qmi_ce_cfg ce_cfg;
 125         struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 126         u32 mem_seg_count;
 127         u32 target_mem_mode;
 128         bool target_mem_delayed;
 129         u8 cal_done;
 130         struct target_info target;
 131         struct m3_mem_region m3_mem;
 132         unsigned int service_ins_id;
 133         wait_queue_head_t cold_boot_waitq;
 134 };
 135
 136 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN         189
 137 #define QMI_WLANFW_HOST_CAP_REQ_V01                     0x0034
 138 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN        7
 139 #define QMI_WLFW_HOST_CAP_RESP_V01                      0x0034
 140 #define QMI_WLFW_MAX_NUM_GPIO_V01                       32
 141 #define QMI_IPQ8074_FW_MEM_MODE                         0xFF
 142 #define HOST_DDR_REGION_TYPE                            0x1
 143 #define BDF_MEM_REGION_TYPE                             0x2
 144 #define CALDB_MEM_REGION_TYPE                           0x4
 145
 146 struct qmi_wlanfw_host_cap_req_msg_v01 {
 147         u8 num_clients_valid;
 148         u32 num_clients;
 149         u8 wake_msi_valid;
 150         u32 wake_msi;
 151         u8 gpios_valid;
 152         u32 gpios_len;
 153         u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
 154         u8 nm_modem_valid;
 155         u8 nm_modem;
 156         u8 bdf_support_valid;
 157         u8 bdf_support;
 158         u8 bdf_cache_support_valid;
 159         u8 bdf_cache_support;
 160         u8 m3_support_valid;
 161         u8 m3_support;
 162         u8 m3_cache_support_valid;
 163         u8 m3_cache_support;
 164         u8 cal_filesys_support_valid;
 165         u8 cal_filesys_support;
 166         u8 cal_cache_support_valid;
 167         u8 cal_cache_support;
 168         u8 cal_done_valid;
 169         u8 cal_done;
 170         u8 mem_bucket_valid;
 171         u32 mem_bucket;
 172         u8 mem_cfg_mode_valid;
 173         u8 mem_cfg_mode;
 174 };
 175
 176 struct qmi_wlanfw_host_cap_resp_msg_v01 {
 177         struct qmi_response_type_v01 resp;
 178 };
 179
 180 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN             54
 181 #define QMI_WLANFW_IND_REGISTER_REQ_V01                         0x0020
 182 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN            18
 183 #define QMI_WLANFW_IND_REGISTER_RESP_V01                        0x0020
 184 #define QMI_WLANFW_CLIENT_ID                                    0x4b4e454c
 185
 186 struct qmi_wlanfw_ind_register_req_msg_v01 {
 187         u8 fw_ready_enable_valid;
 188         u8 fw_ready_enable;
 189         u8 initiate_cal_download_enable_valid;
 190         u8 initiate_cal_download_enable;
 191         u8 initiate_cal_update_enable_valid;
 192         u8 initiate_cal_update_enable;
 193         u8 msa_ready_enable_valid;
 194         u8 msa_ready_enable;
 195         u8 pin_connect_result_enable_valid;
 196         u8 pin_connect_result_enable;
 197         u8 client_id_valid;
 198         u32 client_id;
 199         u8 request_mem_enable_valid;
 200         u8 request_mem_enable;
 201         u8 fw_mem_ready_enable_valid;
 202         u8 fw_mem_ready_enable;
 203         u8 fw_init_done_enable_valid;
 204         u8 fw_init_done_enable;
 205         u8 rejuvenate_enable_valid;
 206         u32 rejuvenate_enable;
 207         u8 xo_cal_enable_valid;
 208         u8 xo_cal_enable;
 209         u8 cal_done_enable_valid;
 210         u8 cal_done_enable;
 211 };
 212
 213 struct qmi_wlanfw_ind_register_resp_msg_v01 {
 214         struct qmi_response_type_v01 resp;
 215         u8 fw_status_valid;
 216         u64 fw_status;
 217 };
 218
 219 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN      1124
 220 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN      548
 221 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN     7
 222 #define QMI_WLANFW_REQUEST_MEM_IND_V01                  0x0035
 223 #define QMI_WLANFW_RESPOND_MEM_REQ_V01                  0x0036
 224 #define QMI_WLANFW_RESPOND_MEM_RESP_V01                 0x0036
 225 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01                  2
 226
 227 struct qmi_wlanfw_mem_cfg_s_v01 {
 228         u64 offset;
 229         u32 size;
 230         u8 secure_flag;
 231 };
 232
 233 enum qmi_wlanfw_mem_type_enum_v01 {
 234         WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
 235         QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
 236         QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
 237         QMI_WLANFW_MEM_BDF_V01 = 2,
 238         QMI_WLANFW_MEM_M3_V01 = 3,
 239         QMI_WLANFW_MEM_CAL_V01 = 4,
 240         QMI_WLANFW_MEM_DPD_V01 = 5,
 241         WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
 242 };
 243
 244 struct qmi_wlanfw_mem_seg_s_v01 {
 245         u32 size;
 246         enum qmi_wlanfw_mem_type_enum_v01 type;
 247         u32 mem_cfg_len;
 248         struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
 249 };
 250
 251 struct qmi_wlanfw_request_mem_ind_msg_v01 {
 252         u32 mem_seg_len;
 253         struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 254 };
 255
 256 struct qmi_wlanfw_mem_seg_resp_s_v01 {
 257         u64 addr;
 258         u32 size;
 259         enum qmi_wlanfw_mem_type_enum_v01 type;
 260         u8 restore;
 261 };
 262
 263 struct qmi_wlanfw_respond_mem_req_msg_v01 {
 264         u32 mem_seg_len;
 265         struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 266 };
 267
 268 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
 269         struct qmi_response_type_v01 resp;
 270 };
 271
 272 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
 273         char placeholder;
 274 };
 275
 276 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
 277         char placeholder;
 278 };
 279
 280 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 {
 281         char placeholder;
 282 };
 283
 284 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN      0
 285 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN     207
 286 #define QMI_WLANFW_CAP_REQ_V01                  0x0024
 287 #define QMI_WLANFW_CAP_RESP_V01                 0x0024
 288
 289 enum qmi_wlanfw_pipedir_enum_v01 {
 290         QMI_WLFW_PIPEDIR_NONE_V01 = 0,
 291         QMI_WLFW_PIPEDIR_IN_V01 = 1,
 292         QMI_WLFW_PIPEDIR_OUT_V01 = 2,
 293         QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
 294 };
 295
 296 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
 297         __le32 pipe_num;
 298         __le32 pipe_dir;
 299         __le32 nentries;
 300         __le32 nbytes_max;
 301         __le32 flags;
 302 };
 303
 304 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
 305         __le32 service_id;
 306         __le32 pipe_dir;
 307         __le32 pipe_num;
 308 };
 309
 310 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
 311         u16 id;
 312         u16 offset;
 313 };
 314
 315 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 {
 316         u32 addr;
 317 };
 318
 319 struct qmi_wlanfw_memory_region_info_s_v01 {
 320         u64 region_addr;
 321         u32 size;
 322         u8 secure_flag;
 323 };
 324
 325 struct qmi_wlanfw_rf_chip_info_s_v01 {
 326         u32 chip_id;
 327         u32 chip_family;
 328 };
 329
 330 struct qmi_wlanfw_rf_board_info_s_v01 {
 331         u32 board_id;
 332 };
 333
 334 struct qmi_wlanfw_soc_info_s_v01 {
 335         u32 soc_id;
 336 };
 337
 338 struct qmi_wlanfw_fw_version_info_s_v01 {
 339         u32 fw_version;
 340         char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
 341 };
 342
 343 enum qmi_wlanfw_cal_temp_id_enum_v01 {
 344         QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
 345         QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
 346         QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
 347         QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
 348         QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
 349         QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
 350 };
 351
 352 struct qmi_wlanfw_cap_resp_msg_v01 {
 353         struct qmi_response_type_v01 resp;
 354         u8 chip_info_valid;
 355         struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
 356         u8 board_info_valid;
 357         struct qmi_wlanfw_rf_board_info_s_v01 board_info;
 358         u8 soc_info_valid;
 359         struct qmi_wlanfw_soc_info_s_v01 soc_info;
 360         u8 fw_version_info_valid;
 361         struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
 362         u8 fw_build_id_valid;
 363         char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
 364         u8 num_macs_valid;
 365         u8 num_macs;
 366 };
 367
 368 struct qmi_wlanfw_cap_req_msg_v01 {
 369         char placeholder;
 370 };
 371
 372 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN     6182
 373 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN    7
 374 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01                0x0025
 375 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01                 0x0025
 376 /* TODO: Need to check with MCL and FW team that data can be pointer and
 377  * can be last element in structure
 378  */
 379 struct qmi_wlanfw_bdf_download_req_msg_v01 {
 380         u8 valid;
 381         u8 file_id_valid;
 382         enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
 383         u8 total_size_valid;
 384         u32 total_size;
 385         u8 seg_id_valid;
 386         u32 seg_id;
 387         u8 data_valid;
 388         u32 data_len;
 389         u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
 390         u8 end_valid;
 391         u8 end;
 392         u8 bdf_type_valid;
 393         u8 bdf_type;
 394
 395 };
 396
 397 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
 398         struct qmi_response_type_v01 resp;
 399 };
 400
 401 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN      18
 402 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN     7
 403 #define QMI_WLANFW_M3_INFO_RESP_V01             0x003C
 404 #define QMI_WLANFW_M3_INFO_REQ_V01              0x003C
 405
 406 struct qmi_wlanfw_m3_info_req_msg_v01 {
 407         u64 addr;
 408         u32 size;
 409 };
 410
 411 struct qmi_wlanfw_m3_info_resp_msg_v01 {
 412         struct qmi_response_type_v01 resp;
 413 };
 414
 415 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN        11
 416 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN       7
 417 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN         803
 418 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN        7
 419 #define QMI_WLANFW_WLAN_MODE_REQ_V01                    0x0022
 420 #define QMI_WLANFW_WLAN_MODE_RESP_V01                   0x0022
 421 #define QMI_WLANFW_WLAN_CFG_REQ_V01                     0x0023
 422 #define QMI_WLANFW_WLAN_CFG_RESP_V01                    0x0023
 423 #define QMI_WLANFW_MAX_STR_LEN_V01                      16
 424 #define QMI_WLANFW_MAX_NUM_CE_V01                       12
 425 #define QMI_WLANFW_MAX_NUM_SVC_V01                      24
 426 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01               24
 427 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01            36
 428
 429 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
 430         u32 mode;
 431         u8 hw_debug_valid;
 432         u8 hw_debug;
 433 };
 434
 435 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
 436         struct qmi_response_type_v01 resp;
 437 };
 438
 439 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
 440         u8 host_version_valid;
 441         char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
 442         u8  tgt_cfg_valid;
 443         u32  tgt_cfg_len;
 444         struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
 445                         tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
 446         u8  svc_cfg_valid;
 447         u32 svc_cfg_len;
 448         struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
 449                         svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
 450         u8 shadow_reg_valid;
 451         u32 shadow_reg_len;
 452         struct qmi_wlanfw_shadow_reg_cfg_s_v01
 453                 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
 454         u8 shadow_reg_v2_valid;
 455         u32 shadow_reg_v2_len;
 456         struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01
 457                 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01];
 458 };
 459
 460 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
 461         struct qmi_response_type_v01 resp;
 462 };
 463
 464 int ath11k_qmi_firmware_start(struct ath11k_base *ab,
 465                               u32 mode);
 466 void ath11k_qmi_firmware_stop(struct ath11k_base *ab);
 467 void ath11k_qmi_event_work(struct work_struct *work);
 468 void ath11k_qmi_msg_recv_work(struct work_struct *work);
 469 void ath11k_qmi_deinit_service(struct ath11k_base *ab);
 470 int ath11k_qmi_init_service(struct ath11k_base *ab);
 471
 472 #endif