WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / intel / iwlwifi / cfg / 22000.c
blob7220fc8fd9b0dbee1fb2c483fc0394b9f2aab943
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2020 Intel Corporation
5 */
6 #include <linux/module.h>
7 #include <linux/stringify.h>
8 #include "iwl-config.h"
9 #include "iwl-prph.h"
11 /* Highest firmware API version supported */
12 #define IWL_22000_UCODE_API_MAX 59
14 /* Lowest firmware API version supported */
15 #define IWL_22000_UCODE_API_MIN 39
17 /* NVM versions */
18 #define IWL_22000_NVM_VERSION 0x0a1d
20 /* Memory offsets and lengths */
21 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */
22 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */
23 #define IWL_22000_DCCM2_OFFSET 0x880000
24 #define IWL_22000_DCCM2_LEN 0x8000
25 #define IWL_22000_SMEM_OFFSET 0x400000
26 #define IWL_22000_SMEM_LEN 0xD0000
28 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-"
29 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-"
30 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-"
31 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-"
32 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-"
33 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-"
34 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-"
35 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-"
36 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-"
37 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-"
38 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-"
39 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-"
40 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-"
41 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-"
42 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-"
43 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-"
44 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-"
45 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-"
46 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-"
47 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-"
49 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
50 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
51 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \
52 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
53 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
54 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
55 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
56 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
57 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
58 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
59 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
60 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
61 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \
62 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
63 #define IWL_CC_A_MODULE_FIRMWARE(api) \
64 IWL_CC_A_FW_PRE __stringify(api) ".ucode"
65 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
66 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
67 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
68 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
69 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
70 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
71 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
72 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
73 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
74 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
75 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
76 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
77 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
78 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
79 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
80 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
81 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
82 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
83 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
84 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
86 static const struct iwl_base_params iwl_22000_base_params = {
87 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
88 .num_of_queues = 512,
89 .max_tfd_queue_size = 256,
90 .shadow_ram_support = true,
91 .led_compensation = 57,
92 .wd_timeout = IWL_LONG_WD_TIMEOUT,
93 .max_event_log_size = 512,
94 .shadow_reg_enable = true,
95 .pcie_l1_allowed = true,
98 static const struct iwl_base_params iwl_ax210_base_params = {
99 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
100 .num_of_queues = 512,
101 .max_tfd_queue_size = 65536,
102 .shadow_ram_support = true,
103 .led_compensation = 57,
104 .wd_timeout = IWL_LONG_WD_TIMEOUT,
105 .max_event_log_size = 512,
106 .shadow_reg_enable = true,
107 .pcie_l1_allowed = true,
110 static const struct iwl_ht_params iwl_22000_ht_params = {
111 .stbc = true,
112 .ldpc = true,
113 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
114 BIT(NL80211_BAND_6GHZ),
117 #define IWL_DEVICE_22000_COMMON \
118 .ucode_api_max = IWL_22000_UCODE_API_MAX, \
119 .ucode_api_min = IWL_22000_UCODE_API_MIN, \
120 .led_mode = IWL_LED_RF_STATE, \
121 .nvm_hw_section_num = 10, \
122 .non_shared_ant = ANT_B, \
123 .dccm_offset = IWL_22000_DCCM_OFFSET, \
124 .dccm_len = IWL_22000_DCCM_LEN, \
125 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
126 .dccm2_len = IWL_22000_DCCM2_LEN, \
127 .smem_offset = IWL_22000_SMEM_OFFSET, \
128 .smem_len = IWL_22000_SMEM_LEN, \
129 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \
130 .apmg_not_supported = true, \
131 .trans.mq_rx_supported = true, \
132 .vht_mu_mimo_supported = true, \
133 .mac_addr_from_csr = true, \
134 .ht_params = &iwl_22000_ht_params, \
135 .nvm_ver = IWL_22000_NVM_VERSION, \
136 .max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K, \
137 .trans.use_tfh = true, \
138 .trans.rf_id = true, \
139 .trans.gen2 = true, \
140 .nvm_type = IWL_NVM_EXT, \
141 .dbgc_supported = true, \
142 .min_umac_error_event_table = 0x400000, \
143 .d3_debug_data_base_addr = 0x401000, \
144 .d3_debug_data_length = 60 * 1024, \
145 .mon_smem_regs = { \
146 .write_ptr = { \
147 .addr = LDBG_M2S_BUF_WPTR, \
148 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
149 }, \
150 .cycle_cnt = { \
151 .addr = LDBG_M2S_BUF_WRAP_CNT, \
152 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
153 }, \
156 #define IWL_DEVICE_22500 \
157 IWL_DEVICE_22000_COMMON, \
158 .trans.device_family = IWL_DEVICE_FAMILY_22000, \
159 .trans.base_params = &iwl_22000_base_params, \
160 .gp2_reg_addr = 0xa02c68, \
161 .mon_dram_regs = { \
162 .write_ptr = { \
163 .addr = MON_BUFF_WRPTR_VER2, \
164 .mask = 0xffffffff, \
165 }, \
166 .cycle_cnt = { \
167 .addr = MON_BUFF_CYCLE_CNT_VER2, \
168 .mask = 0xffffffff, \
169 }, \
172 #define IWL_DEVICE_AX210 \
173 IWL_DEVICE_22000_COMMON, \
174 .trans.umac_prph_offset = 0x300000, \
175 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \
176 .trans.base_params = &iwl_ax210_base_params, \
177 .min_txq_size = 128, \
178 .gp2_reg_addr = 0xd02c68, \
179 .min_256_ba_txq_size = 1024, \
180 .mon_dram_regs = { \
181 .write_ptr = { \
182 .addr = DBGC_CUR_DBGBUF_STATUS, \
183 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
184 }, \
185 .cycle_cnt = { \
186 .addr = DBGC_DBGBUF_WRAP_AROUND, \
187 .mask = 0xffffffff, \
188 }, \
189 .cur_frag = { \
190 .addr = DBGC_CUR_DBGBUF_STATUS, \
191 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
192 }, \
195 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
196 .mq_rx_supported = true,
197 .use_tfh = true,
198 .rf_id = true,
199 .gen2 = true,
200 .device_family = IWL_DEVICE_FAMILY_22000,
201 .base_params = &iwl_22000_base_params,
204 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
205 .mq_rx_supported = true,
206 .use_tfh = true,
207 .rf_id = true,
208 .gen2 = true,
209 .device_family = IWL_DEVICE_FAMILY_22000,
210 .base_params = &iwl_22000_base_params,
211 .integrated = true,
212 .xtal_latency = 500,
213 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
216 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
217 .mq_rx_supported = true,
218 .use_tfh = true,
219 .rf_id = true,
220 .gen2 = true,
221 .device_family = IWL_DEVICE_FAMILY_22000,
222 .base_params = &iwl_22000_base_params,
223 .integrated = true,
224 .xtal_latency = 1820,
225 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
228 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
229 .mq_rx_supported = true,
230 .use_tfh = true,
231 .rf_id = true,
232 .gen2 = true,
233 .device_family = IWL_DEVICE_FAMILY_22000,
234 .base_params = &iwl_22000_base_params,
235 .integrated = true,
236 .xtal_latency = 12000,
237 .low_latency_xtal = true,
238 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
242 * If the device doesn't support HE, no need to have that many buffers.
243 * 22000 devices can split multiple frames into a single RB, so fewer are
244 * needed; AX210 cannot (but use smaller RBs by default) - these sizes
245 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
246 * additional overhead to account for processing time.
248 #define IWL_NUM_RBDS_NON_HE 512
249 #define IWL_NUM_RBDS_22000_HE 2048
250 #define IWL_NUM_RBDS_AX210_HE 4096
253 * All JF radio modules are part of the 9000 series, but the MAC part
254 * looks more like 22000. That's why this device is here, but called
255 * 9560 nevertheless.
257 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
258 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
259 IWL_DEVICE_22500,
260 .num_rbds = IWL_NUM_RBDS_NON_HE,
263 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
264 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
265 IWL_DEVICE_22500,
266 .num_rbds = IWL_NUM_RBDS_NON_HE,
269 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
270 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
271 IWL_DEVICE_22500,
273 * This device doesn't support receiving BlockAck with a large bitmap
274 * so we need to restrict the size of transmitted aggregation to the
275 * HT size; mac80211 would otherwise pick the HE max (256) by default.
277 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
278 .num_rbds = IWL_NUM_RBDS_NON_HE,
281 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
282 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
283 IWL_DEVICE_22500,
285 * This device doesn't support receiving BlockAck with a large bitmap
286 * so we need to restrict the size of transmitted aggregation to the
287 * HT size; mac80211 would otherwise pick the HE max (256) by default.
289 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
290 .num_rbds = IWL_NUM_RBDS_NON_HE,
293 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
294 .device_family = IWL_DEVICE_FAMILY_22000,
295 .base_params = &iwl_22000_base_params,
296 .mq_rx_supported = true,
297 .use_tfh = true,
298 .rf_id = true,
299 .gen2 = true,
300 .bisr_workaround = 1,
303 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
304 .device_family = IWL_DEVICE_FAMILY_AX210,
305 .base_params = &iwl_ax210_base_params,
306 .mq_rx_supported = true,
307 .use_tfh = true,
308 .rf_id = true,
309 .gen2 = true,
310 .integrated = true,
311 .umac_prph_offset = 0x300000
314 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
315 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
316 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
317 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6 AX211 160MHz";
318 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6 AX411 160MHz";
319 const char iwl_ma_name[] = "Intel(R) Wi-Fi 6";
321 const char iwl_ax200_killer_1650w_name[] =
322 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
323 const char iwl_ax200_killer_1650x_name[] =
324 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
325 const char iwl_ax201_killer_1650s_name[] =
326 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
327 const char iwl_ax201_killer_1650i_name[] =
328 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
330 const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
331 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
332 IWL_DEVICE_22500,
334 * This device doesn't support receiving BlockAck with a large bitmap
335 * so we need to restrict the size of transmitted aggregation to the
336 * HT size; mac80211 would otherwise pick the HE max (256) by default.
338 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
339 .tx_with_siso_diversity = true,
340 .num_rbds = IWL_NUM_RBDS_22000_HE,
343 const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
344 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
345 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
346 IWL_DEVICE_22500,
348 * This device doesn't support receiving BlockAck with a large bitmap
349 * so we need to restrict the size of transmitted aggregation to the
350 * HT size; mac80211 would otherwise pick the HE max (256) by default.
352 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
353 .num_rbds = IWL_NUM_RBDS_22000_HE,
356 const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
357 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
358 IWL_DEVICE_22500,
360 * This device doesn't support receiving BlockAck with a large bitmap
361 * so we need to restrict the size of transmitted aggregation to the
362 * HT size; mac80211 would otherwise pick the HE max (256) by default.
364 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
365 .tx_with_siso_diversity = true,
366 .num_rbds = IWL_NUM_RBDS_22000_HE,
369 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
370 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
371 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
372 IWL_DEVICE_22500,
374 * This device doesn't support receiving BlockAck with a large bitmap
375 * so we need to restrict the size of transmitted aggregation to the
376 * HT size; mac80211 would otherwise pick the HE max (256) by default.
378 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
379 .num_rbds = IWL_NUM_RBDS_22000_HE,
382 const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
383 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
384 IWL_DEVICE_22500,
386 * This device doesn't support receiving BlockAck with a large bitmap
387 * so we need to restrict the size of transmitted aggregation to the
388 * HT size; mac80211 would otherwise pick the HE max (256) by default.
390 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
391 .tx_with_siso_diversity = true,
392 .num_rbds = IWL_NUM_RBDS_22000_HE,
395 const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
396 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
397 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
398 IWL_DEVICE_22500,
400 * This device doesn't support receiving BlockAck with a large bitmap
401 * so we need to restrict the size of transmitted aggregation to the
402 * HT size; mac80211 would otherwise pick the HE max (256) by default.
404 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
405 .num_rbds = IWL_NUM_RBDS_22000_HE,
408 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
409 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
410 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
411 IWL_DEVICE_22500,
413 * This device doesn't support receiving BlockAck with a large bitmap
414 * so we need to restrict the size of transmitted aggregation to the
415 * HT size; mac80211 would otherwise pick the HE max (256) by default.
417 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
418 .num_rbds = IWL_NUM_RBDS_22000_HE,
421 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
422 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
423 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
424 IWL_DEVICE_22500,
426 * This device doesn't support receiving BlockAck with a large bitmap
427 * so we need to restrict the size of transmitted aggregation to the
428 * HT size; mac80211 would otherwise pick the HE max (256) by default.
430 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
431 .num_rbds = IWL_NUM_RBDS_22000_HE,
434 const struct iwl_cfg iwl_ax200_cfg_cc = {
435 .fw_name_pre = IWL_CC_A_FW_PRE,
436 IWL_DEVICE_22500,
438 * This device doesn't support receiving BlockAck with a large bitmap
439 * so we need to restrict the size of transmitted aggregation to the
440 * HT size; mac80211 would otherwise pick the HE max (256) by default.
442 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
443 .num_rbds = IWL_NUM_RBDS_22000_HE,
446 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
447 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
448 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
449 IWL_DEVICE_22500,
451 * This device doesn't support receiving BlockAck with a large bitmap
452 * so we need to restrict the size of transmitted aggregation to the
453 * HT size; mac80211 would otherwise pick the HE max (256) by default.
455 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
456 .num_rbds = IWL_NUM_RBDS_22000_HE,
459 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
460 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
461 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
462 IWL_DEVICE_22500,
464 * This device doesn't support receiving BlockAck with a large bitmap
465 * so we need to restrict the size of transmitted aggregation to the
466 * HT size; mac80211 would otherwise pick the HE max (256) by default.
468 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
469 .num_rbds = IWL_NUM_RBDS_22000_HE,
472 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
473 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
474 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
475 IWL_DEVICE_22500,
477 * This device doesn't support receiving BlockAck with a large bitmap
478 * so we need to restrict the size of transmitted aggregation to the
479 * HT size; mac80211 would otherwise pick the HE max (256) by default.
481 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
482 .num_rbds = IWL_NUM_RBDS_22000_HE,
485 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
486 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
487 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
488 IWL_DEVICE_22500,
490 * This device doesn't support receiving BlockAck with a large bitmap
491 * so we need to restrict the size of transmitted aggregation to the
492 * HT size; mac80211 would otherwise pick the HE max (256) by default.
494 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
495 .num_rbds = IWL_NUM_RBDS_22000_HE,
498 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
499 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
500 IWL_DEVICE_22500,
502 * This device doesn't support receiving BlockAck with a large bitmap
503 * so we need to restrict the size of transmitted aggregation to the
504 * HT size; mac80211 would otherwise pick the HE max (256) by default.
506 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
507 .num_rbds = IWL_NUM_RBDS_22000_HE,
510 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0 = {
511 .name = "Intel(R) Wireless-AC 9560 160MHz",
512 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
513 IWL_DEVICE_AX210,
514 .num_rbds = IWL_NUM_RBDS_NON_HE,
517 const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = {
518 .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
519 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
520 IWL_DEVICE_AX210,
521 .num_rbds = IWL_NUM_RBDS_AX210_HE,
524 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
525 .name = iwl_ax211_name,
526 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
527 .uhb_supported = true,
528 IWL_DEVICE_AX210,
529 .num_rbds = IWL_NUM_RBDS_AX210_HE,
532 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
533 .name = iwl_ax211_name,
534 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
535 .uhb_supported = true,
536 IWL_DEVICE_AX210,
537 .num_rbds = IWL_NUM_RBDS_AX210_HE,
538 .trans.xtal_latency = 12000,
539 .trans.low_latency_xtal = true,
542 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
543 .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
544 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
545 .uhb_supported = true,
546 IWL_DEVICE_AX210,
547 .num_rbds = IWL_NUM_RBDS_AX210_HE,
550 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
551 .name = iwl_ax411_name,
552 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
553 .uhb_supported = true,
554 IWL_DEVICE_AX210,
555 .num_rbds = IWL_NUM_RBDS_AX210_HE,
558 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
559 .name = iwl_ax411_name,
560 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
561 .uhb_supported = true,
562 IWL_DEVICE_AX210,
563 .num_rbds = IWL_NUM_RBDS_AX210_HE,
564 .trans.xtal_latency = 12000,
565 .trans.low_latency_xtal = true,
568 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
569 .name = iwl_ax411_name,
570 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
571 .uhb_supported = true,
572 IWL_DEVICE_AX210,
573 .num_rbds = IWL_NUM_RBDS_AX210_HE,
576 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
577 .name = iwl_ax211_name,
578 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
579 .uhb_supported = true,
580 IWL_DEVICE_AX210,
581 .num_rbds = IWL_NUM_RBDS_AX210_HE,
584 const struct iwl_cfg iwlax201_cfg_snj_hr_b0 = {
585 .name = iwl_ax201_name,
586 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
587 .uhb_supported = true,
588 IWL_DEVICE_AX210,
589 .num_rbds = IWL_NUM_RBDS_AX210_HE,
592 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
593 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
594 .uhb_supported = true,
595 IWL_DEVICE_AX210,
596 .num_rbds = IWL_NUM_RBDS_AX210_HE,
599 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
600 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
601 .uhb_supported = true,
602 IWL_DEVICE_AX210,
603 .num_rbds = IWL_NUM_RBDS_AX210_HE,
606 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
607 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
608 .uhb_supported = true,
609 IWL_DEVICE_AX210,
610 .num_rbds = IWL_NUM_RBDS_AX210_HE,
613 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
614 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
615 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
616 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
617 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
618 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
619 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
620 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
621 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
622 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
623 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
624 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
625 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
626 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
627 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
628 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
629 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
630 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));