1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2019 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #ifndef __iwl_fw_api_config_h__
8 #define __iwl_fw_api_config_h__
11 * struct iwl_dqa_enable_cmd
12 * @cmd_queue: the TXQ number of the command queue
14 struct iwl_dqa_enable_cmd
{
16 } __packed
; /* DQA_CONTROL_CMD_API_S_VER_1 */
19 * struct iwl_tx_ant_cfg_cmd
20 * @valid: valid antenna configuration
22 struct iwl_tx_ant_cfg_cmd
{
27 * struct iwl_calib_ctrl - Calibration control struct.
28 * Sent as part of the phy configuration command.
29 * @flow_trigger: bitmap for which calibrations to perform according to
30 * flow triggers, using &enum iwl_calib_cfg
31 * @event_trigger: bitmap for which calibrations to perform according to
32 * event triggers, using &enum iwl_calib_cfg
34 struct iwl_calib_ctrl
{
39 /* This enum defines the bitmap of various calibrations to enable in both
40 * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
43 IWL_CALIB_CFG_XTAL_IDX
= BIT(0),
44 IWL_CALIB_CFG_TEMPERATURE_IDX
= BIT(1),
45 IWL_CALIB_CFG_VOLTAGE_READ_IDX
= BIT(2),
46 IWL_CALIB_CFG_PAPD_IDX
= BIT(3),
47 IWL_CALIB_CFG_TX_PWR_IDX
= BIT(4),
48 IWL_CALIB_CFG_DC_IDX
= BIT(5),
49 IWL_CALIB_CFG_BB_FILTER_IDX
= BIT(6),
50 IWL_CALIB_CFG_LO_LEAKAGE_IDX
= BIT(7),
51 IWL_CALIB_CFG_TX_IQ_IDX
= BIT(8),
52 IWL_CALIB_CFG_TX_IQ_SKEW_IDX
= BIT(9),
53 IWL_CALIB_CFG_RX_IQ_IDX
= BIT(10),
54 IWL_CALIB_CFG_RX_IQ_SKEW_IDX
= BIT(11),
55 IWL_CALIB_CFG_SENSITIVITY_IDX
= BIT(12),
56 IWL_CALIB_CFG_CHAIN_NOISE_IDX
= BIT(13),
57 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX
= BIT(14),
58 IWL_CALIB_CFG_ANT_COUPLING_IDX
= BIT(15),
59 IWL_CALIB_CFG_DAC_IDX
= BIT(16),
60 IWL_CALIB_CFG_ABS_IDX
= BIT(17),
61 IWL_CALIB_CFG_AGC_IDX
= BIT(18),
65 * struct iwl_phy_specific_cfg - specific PHY filter configuration
67 * Sent as part of the phy configuration command (v3) to configure specific FW
68 * defined PHY filters that can be applied to each antenna.
70 * @filter_cfg_chain_a: filter config id for LMAC1 chain A
71 * @filter_cfg_chain_b: filter config id for LMAC1 chain B
72 * @filter_cfg_chain_c: filter config id for LMAC2 chain A
73 * @filter_cfg_chain_d: filter config id for LMAC2 chain B
74 * values: 0 - no filter; 0xffffffff - reserved; otherwise - filter id
76 struct iwl_phy_specific_cfg
{
77 __le32 filter_cfg_chain_a
;
78 __le32 filter_cfg_chain_b
;
79 __le32 filter_cfg_chain_c
;
80 __le32 filter_cfg_chain_d
;
81 } __packed
; /* PHY_SPECIFIC_CONFIGURATION_API_VER_1*/
84 * struct iwl_phy_cfg_cmd - Phy configuration command
86 * @phy_cfg: PHY configuration value, uses &enum iwl_fw_phy_cfg
87 * @calib_control: calibration control data
89 struct iwl_phy_cfg_cmd_v1
{
91 struct iwl_calib_ctrl calib_control
;
95 * struct iwl_phy_cfg_cmd_v3 - Phy configuration command (v3)
97 * @phy_cfg: PHY configuration value, uses &enum iwl_fw_phy_cfg
98 * @calib_control: calibration control data
99 * @phy_specific_cfg: configure predefined PHY filters
101 struct iwl_phy_cfg_cmd_v3
{
103 struct iwl_calib_ctrl calib_control
;
104 struct iwl_phy_specific_cfg phy_specific_cfg
;
105 } __packed
; /* PHY_CONFIGURATION_CMD_API_S_VER_3 */
108 * enum iwl_dc2dc_config_id - flag ids
110 * Ids of dc2dc configuration flags
112 enum iwl_dc2dc_config_id
{
113 DCDC_LOW_POWER_MODE_MSK_SET
= 0x1, /* not used */
114 DCDC_FREQ_TUNE_SET
= 0x2,
115 }; /* MARKER_ID_API_E_VER_1 */
118 * struct iwl_dc2dc_config_cmd - configure dc2dc values
120 * (DC2DC_CONFIG_CMD = 0x83)
122 * Set/Get & configure dc2dc values.
123 * The command always returns the current dc2dc values.
125 * @flags: set/get dc2dc
126 * @enable_low_power_mode: not used.
127 * @dc2dc_freq_tune0: frequency divider - digital domain
128 * @dc2dc_freq_tune1: frequency divider - analog domain
130 struct iwl_dc2dc_config_cmd
{
132 __le32 enable_low_power_mode
; /* not used */
133 __le32 dc2dc_freq_tune0
;
134 __le32 dc2dc_freq_tune1
;
135 } __packed
; /* DC2DC_CONFIG_CMD_API_S_VER_1 */
138 * struct iwl_dc2dc_config_resp - response for iwl_dc2dc_config_cmd
140 * Current dc2dc values returned by the FW.
142 * @dc2dc_freq_tune0: frequency divider - digital domain
143 * @dc2dc_freq_tune1: frequency divider - analog domain
145 struct iwl_dc2dc_config_resp
{
146 __le32 dc2dc_freq_tune0
;
147 __le32 dc2dc_freq_tune1
;
148 } __packed
; /* DC2DC_CONFIG_RESP_API_S_VER_1 */
150 #endif /* __iwl_fw_api_config_h__ */