1 // SPDX-License-Identifier: ISC
6 void mt7603_rx_poll_complete(struct mt76_dev
*mdev
, enum mt76_rxq_id q
)
8 struct mt7603_dev
*dev
= container_of(mdev
, struct mt7603_dev
, mt76
);
10 mt7603_irq_enable(dev
, MT_INT_RX_DONE(q
));
13 irqreturn_t
mt7603_irq_handler(int irq
, void *dev_instance
)
15 struct mt7603_dev
*dev
= dev_instance
;
18 intr
= mt76_rr(dev
, MT_INT_SOURCE_CSR
);
19 mt76_wr(dev
, MT_INT_SOURCE_CSR
, intr
);
21 if (!test_bit(MT76_STATE_INITIALIZED
, &dev
->mphy
.state
))
24 trace_dev_irq(&dev
->mt76
, intr
, dev
->mt76
.mmio
.irqmask
);
26 intr
&= dev
->mt76
.mmio
.irqmask
;
28 if (intr
& MT_INT_MAC_IRQ3
) {
29 u32 hwintr
= mt76_rr(dev
, MT_HW_INT_STATUS(3));
31 mt76_wr(dev
, MT_HW_INT_STATUS(3), hwintr
);
32 if (hwintr
& MT_HW_INT3_PRE_TBTT0
)
33 tasklet_schedule(&dev
->mt76
.pre_tbtt_tasklet
);
35 if ((hwintr
& MT_HW_INT3_TBTT0
) && dev
->mt76
.csa_complete
)
36 mt76_csa_finish(&dev
->mt76
);
39 if (intr
& MT_INT_TX_DONE_ALL
) {
40 mt7603_irq_disable(dev
, MT_INT_TX_DONE_ALL
);
41 napi_schedule(&dev
->mt76
.tx_napi
);
44 if (intr
& MT_INT_RX_DONE(0)) {
45 mt7603_irq_disable(dev
, MT_INT_RX_DONE(0));
46 napi_schedule(&dev
->mt76
.napi
[0]);
49 if (intr
& MT_INT_RX_DONE(1)) {
50 mt7603_irq_disable(dev
, MT_INT_RX_DONE(1));
51 napi_schedule(&dev
->mt76
.napi
[1]);
57 u32
mt7603_reg_map(struct mt7603_dev
*dev
, u32 addr
)
59 u32 base
= addr
& MT_MCU_PCIE_REMAP_2_BASE
;
60 u32 offset
= addr
& MT_MCU_PCIE_REMAP_2_OFFSET
;
62 dev
->bus_ops
->wr(&dev
->mt76
, MT_MCU_PCIE_REMAP_2
, base
);
64 return MT_PCIE_REMAP_BASE_2
+ offset
;