?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / mediatek / mt76 / mt7615 / mac.c
blob0f360be0b88518d5e0d807a99e4cd83d85d6be46
1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
12 #include "mt7615.h"
13 #include "../trace.h"
14 #include "../dma.h"
15 #include "mt7615_trace.h"
16 #include "mac.h"
17
18 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
19
20 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
21 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
22 .radar_pattern = {
23 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
24 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
25 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
26 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
27 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
28 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
29 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
30 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
31 },
32 };
33
34 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
35 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
36 .radar_pattern = {
37 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
38 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
39 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
40 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
41 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
42 },
43 };
44
45 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
46 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
47 .radar_pattern = {
48 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
49 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
50 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
51 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
52 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
53 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
54 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
55 },
56 };
57
58 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
59 u8 idx, bool unicast)
60 {
61 struct mt7615_sta *sta;
62 struct mt76_wcid *wcid;
63
64 if (idx >= MT7615_WTBL_SIZE)
65 return NULL;
66
67 wcid = rcu_dereference(dev->mt76.wcid[idx]);
68 if (unicast || !wcid)
69 return wcid;
70
71 if (!wcid->sta)
72 return NULL;
73
74 sta = container_of(wcid, struct mt7615_sta, wcid);
75 if (!sta->vif)
76 return NULL;
77
78 return &sta->vif->sta.wcid;
79 }
80
81 void mt7615_mac_reset_counters(struct mt7615_dev *dev)
82 {
83 int i;
84
85 for (i = 0; i < 4; i++) {
86 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
87 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
88 }
89
90 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
91 dev->mt76.phy.survey_time = ktime_get_boottime();
92 if (dev->mt76.phy2)
93 dev->mt76.phy2->survey_time = ktime_get_boottime();
94
95 /* reset airtime counters */
96 mt76_rr(dev, MT_MIB_SDR9(0));
97 mt76_rr(dev, MT_MIB_SDR9(1));
98
99 mt76_rr(dev, MT_MIB_SDR36(0));
100 mt76_rr(dev, MT_MIB_SDR36(1));
101
102 mt76_rr(dev, MT_MIB_SDR37(0));
103 mt76_rr(dev, MT_MIB_SDR37(1));
104
105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
107 }
108
109 void mt7615_mac_set_timing(struct mt7615_phy *phy)
110 {
111 s16 coverage_class = phy->coverage_class;
112 struct mt7615_dev *dev = phy->dev;
113 bool ext_phy = phy != &dev->phy;
114 u32 val, reg_offset;
115 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
116 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
117 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
118 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
119 int sifs, offset;
120 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
121
122 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
123 return;
124
125 if (is_5ghz)
126 sifs = 16;
127 else
128 sifs = 10;
129
130 if (ext_phy) {
131 coverage_class = max_t(s16, dev->phy.coverage_class,
132 coverage_class);
133 mt76_set(dev, MT_ARB_SCR,
134 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
135 } else {
136 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
137
138 if (phy_ext)
139 coverage_class = max_t(s16, phy_ext->coverage_class,
140 coverage_class);
141 mt76_set(dev, MT_ARB_SCR,
142 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
143 }
144 udelay(1);
145
146 offset = 3 * coverage_class;
147 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
149 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
150 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
151
152 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
153 FIELD_PREP(MT_IFS_EIFS, 360) |
154 FIELD_PREP(MT_IFS_RIFS, 2) |
155 FIELD_PREP(MT_IFS_SIFS, sifs) |
156 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
157
158 if (phy->slottime < 20 || is_5ghz)
159 val = MT7615_CFEND_RATE_DEFAULT;
160 else
161 val = MT7615_CFEND_RATE_11B;
162
163 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
164 if (ext_phy)
165 mt76_clear(dev, MT_ARB_SCR,
166 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
167 else
168 mt76_clear(dev, MT_ARB_SCR,
169 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
170
171 }
172
173 static void
174 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
175 struct mt76_rx_status *status, u8 chfreq)
176 {
177 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
178 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
179 !test_bit(MT76_STATE_ROC, &mphy->state)) {
180 status->freq = mphy->chandef.chan->center_freq;
181 status->band = mphy->chandef.chan->band;
182 return;
183 }
184
185 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
186 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
187 }
188
189 static void mt7615_mac_fill_tm_rx(struct mt7615_dev *dev, __le32 *rxv)
190 {
191 #ifdef CONFIG_NL80211_TESTMODE
192 u32 rxv1 = le32_to_cpu(rxv[0]);
193 u32 rxv3 = le32_to_cpu(rxv[2]);
194 u32 rxv4 = le32_to_cpu(rxv[3]);
195 u32 rxv5 = le32_to_cpu(rxv[4]);
196 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1);
197 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1);
198 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5);
199 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000;
200
201 if (!mode) {
202 /* CCK */
203 foe &= ~BIT(11);
204 foe *= 1000;
205 foe >>= 11;
206 } else {
207 if (foe > 2048)
208 foe -= 4096;
209
210 foe = (foe * foe_const) >> 15;
211 }
212
213 dev->test.last_freq_offset = foe;
214 dev->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4);
215 dev->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4);
216 dev->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4);
217 dev->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4);
218 dev->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3);
219 dev->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3);
220 #endif
221 }
222
223 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
224 {
225 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
226 struct mt76_phy *mphy = &dev->mt76.phy;
227 struct mt7615_phy *phy = &dev->phy;
228 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
229 struct ieee80211_supported_band *sband;
230 struct ieee80211_hdr *hdr;
231 __le32 *rxd = (__le32 *)skb->data;
232 u32 rxd0 = le32_to_cpu(rxd[0]);
233 u32 rxd1 = le32_to_cpu(rxd[1]);
234 u32 rxd2 = le32_to_cpu(rxd[2]);
235 __le32 rxd12 = rxd[12];
236 bool unicast, remove_pad, insert_ccmp_hdr = false;
237 int phy_idx;
238 int i, idx;
239 u8 chfreq;
240
241 memset(status, 0, sizeof(*status));
242
243 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
244 if (!phy2)
245 phy_idx = 0;
246 else if (phy2->chfreq == phy->chfreq)
247 phy_idx = -1;
248 else if (phy->chfreq == chfreq)
249 phy_idx = 0;
250 else if (phy2->chfreq == chfreq)
251 phy_idx = 1;
252 else
253 phy_idx = -1;
254
255 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
256 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
257 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
258
259 if (status->wcid) {
260 struct mt7615_sta *msta;
261
262 msta = container_of(status->wcid, struct mt7615_sta, wcid);
263 spin_lock_bh(&dev->sta_poll_lock);
264 if (list_empty(&msta->poll_list))
265 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
266 spin_unlock_bh(&dev->sta_poll_lock);
267 }
268
269 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
270 status->flag |= RX_FLAG_FAILED_FCS_CRC;
271
272 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
273 status->flag |= RX_FLAG_MMIC_ERROR;
274
275 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
276 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
277 status->flag |= RX_FLAG_DECRYPTED;
278 status->flag |= RX_FLAG_IV_STRIPPED;
279 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
280 }
281
282 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
283
284 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
285 return -EINVAL;
286
287 rxd += 4;
288 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
289 rxd += 4;
290 if ((u8 *)rxd - skb->data >= skb->len)
291 return -EINVAL;
292 }
293
294 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
295 u8 *data = (u8 *)rxd;
296
297 if (status->flag & RX_FLAG_DECRYPTED) {
298 status->iv[0] = data[5];
299 status->iv[1] = data[4];
300 status->iv[2] = data[3];
301 status->iv[3] = data[2];
302 status->iv[4] = data[1];
303 status->iv[5] = data[0];
304
305 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
306 }
307 rxd += 4;
308 if ((u8 *)rxd - skb->data >= skb->len)
309 return -EINVAL;
310 }
311
312 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
313 rxd += 2;
314 if ((u8 *)rxd - skb->data >= skb->len)
315 return -EINVAL;
316 }
317
318 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
319 u32 rxdg5 = le32_to_cpu(rxd[5]);
320
321 /*
322 * If both PHYs are on the same channel and we don't have a WCID,
323 * we need to figure out which PHY this packet was received on.
324 * On the primary PHY, the noise value for the chains belonging to the
325 * second PHY will be set to the noise value of the last packet from
326 * that PHY.
327 */
328 if (phy_idx < 0) {
329 int first_chain = ffs(phy2->chainmask) - 1;
330
331 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
332 }
333 }
334
335 if (phy_idx == 1 && phy2) {
336 mphy = dev->mt76.phy2;
337 phy = phy2;
338 status->ext_phy = true;
339 }
340
341 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
342 return -EINVAL;
343
344 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
345 if (status->band == NL80211_BAND_5GHZ)
346 sband = &mphy->sband_5g.sband;
347 else
348 sband = &mphy->sband_2g.sband;
349
350 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
351 return -EINVAL;
352
353 if (!sband->channels)
354 return -EINVAL;
355
356 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
357 MT_RXD2_NORMAL_NON_AMPDU))) {
358 status->flag |= RX_FLAG_AMPDU_DETAILS;
359
360 /* all subframes of an A-MPDU have the same timestamp */
361 if (phy->rx_ampdu_ts != rxd12) {
362 if (!++phy->ampdu_ref)
363 phy->ampdu_ref++;
364 }
365 phy->rx_ampdu_ts = rxd12;
366
367 status->ampdu_ref = phy->ampdu_ref;
368 }
369
370 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
371 u32 rxdg0 = le32_to_cpu(rxd[0]);
372 u32 rxdg1 = le32_to_cpu(rxd[1]);
373 u32 rxdg3 = le32_to_cpu(rxd[3]);
374 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
375 bool cck = false;
376
377 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
378 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
379 case MT_PHY_TYPE_CCK:
380 cck = true;
381 fallthrough;
382 case MT_PHY_TYPE_OFDM:
383 i = mt76_get_rate(&dev->mt76, sband, i, cck);
384 break;
385 case MT_PHY_TYPE_HT_GF:
386 case MT_PHY_TYPE_HT:
387 status->encoding = RX_ENC_HT;
388 if (i > 31)
389 return -EINVAL;
390 break;
391 case MT_PHY_TYPE_VHT:
392 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
393 status->encoding = RX_ENC_VHT;
394 break;
395 default:
396 return -EINVAL;
397 }
398 status->rate_idx = i;
399
400 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
401 case MT_PHY_BW_20:
402 break;
403 case MT_PHY_BW_40:
404 status->bw = RATE_INFO_BW_40;
405 break;
406 case MT_PHY_BW_80:
407 status->bw = RATE_INFO_BW_80;
408 break;
409 case MT_PHY_BW_160:
410 status->bw = RATE_INFO_BW_160;
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
417 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
418 if (rxdg0 & MT_RXV1_HT_AD_CODE)
419 status->enc_flags |= RX_ENC_FLAG_LDPC;
420
421 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
422
423 status->chains = mphy->antenna_mask;
424 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
425 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
426 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
427 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
428 status->signal = status->chain_signal[0];
429
430 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
431 if (!(status->chains & BIT(i)))
432 continue;
433
434 status->signal = max(status->signal,
435 status->chain_signal[i]);
436 }
437
438 mt7615_mac_fill_tm_rx(dev, rxd);
439
440 rxd += 6;
441 if ((u8 *)rxd - skb->data >= skb->len)
442 return -EINVAL;
443 }
444
445 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
446
447 if (insert_ccmp_hdr) {
448 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
449
450 mt76_insert_ccmp_hdr(skb, key_id);
451 }
452
453 hdr = (struct ieee80211_hdr *)skb->data;
454 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
455 return 0;
456
457 status->aggr = unicast &&
458 !ieee80211_is_qos_nullfunc(hdr->frame_control);
459 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
460 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
461
462 return 0;
463 }
464
465 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
466 {
467 }
468 EXPORT_SYMBOL_GPL(mt7615_sta_ps);
469
470 static u16
471 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
472 struct mt76_phy *mphy,
473 const struct ieee80211_tx_rate *rate,
474 bool stbc, u8 *bw)
475 {
476 u8 phy, nss, rate_idx;
477 u16 rateval = 0;
478
479 *bw = 0;
480
481 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
482 rate_idx = ieee80211_rate_get_vht_mcs(rate);
483 nss = ieee80211_rate_get_vht_nss(rate);
484 phy = MT_PHY_TYPE_VHT;
485 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
486 *bw = 1;
487 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
488 *bw = 2;
489 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
490 *bw = 3;
491 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
492 rate_idx = rate->idx;
493 nss = 1 + (rate->idx >> 3);
494 phy = MT_PHY_TYPE_HT;
495 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
496 phy = MT_PHY_TYPE_HT_GF;
497 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
498 *bw = 1;
499 } else {
500 const struct ieee80211_rate *r;
501 int band = mphy->chandef.chan->band;
502 u16 val;
503
504 nss = 1;
505 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
506 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
507 val = r->hw_value_short;
508 else
509 val = r->hw_value;
510
511 phy = val >> 8;
512 rate_idx = val & 0xff;
513 }
514
515 if (stbc && nss == 1) {
516 nss++;
517 rateval |= MT_TX_RATE_STBC;
518 }
519
520 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
521 FIELD_PREP(MT_TX_RATE_MODE, phy) |
522 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
523
524 return rateval;
525 }
526
527 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
528 struct sk_buff *skb, struct mt76_wcid *wcid,
529 struct ieee80211_sta *sta, int pid,
530 struct ieee80211_key_conf *key, bool beacon)
531 {
532 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
533 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
534 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
535 struct ieee80211_tx_rate *rate = &info->control.rates[0];
536 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
537 bool multicast = is_multicast_ether_addr(hdr->addr1);
538 struct ieee80211_vif *vif = info->control.vif;
539 bool is_mmio = mt76_is_mmio(&dev->mt76);
540 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE;
541 struct mt76_phy *mphy = &dev->mphy;
542 __le16 fc = hdr->frame_control;
543 int tx_count = 8;
544 u16 seqno = 0;
545
546 if (vif) {
547 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
548
549 omac_idx = mvif->omac_idx;
550 wmm_idx = mvif->wmm_idx;
551 }
552
553 if (sta) {
554 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
555
556 tx_count = msta->rate_count;
557 }
558
559 if (ext_phy && dev->mt76.phy2)
560 mphy = dev->mt76.phy2;
561
562 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
563 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
564
565 if (beacon) {
566 p_fmt = MT_TX_TYPE_FW;
567 q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0;
568 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
569 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
570 q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0;
571 } else {
572 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
573 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
574 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb));
575 }
576
577 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
578 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
579 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
580 txwi[0] = cpu_to_le32(val);
581
582 val = MT_TXD1_LONG_FORMAT |
583 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
584 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
585 FIELD_PREP(MT_TXD1_HDR_INFO,
586 ieee80211_get_hdrlen_from_skb(skb) / 2) |
587 FIELD_PREP(MT_TXD1_TID,
588 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
589 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
590 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
591 txwi[1] = cpu_to_le32(val);
592
593 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
594 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
595 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
596 if (key) {
597 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
598 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
599 val |= MT_TXD2_BIP;
600 txwi[3] = 0;
601 } else {
602 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
603 }
604 } else {
605 txwi[3] = 0;
606 }
607 txwi[2] = cpu_to_le32(val);
608
609 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
610 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
611
612 txwi[4] = 0;
613 txwi[6] = 0;
614
615 if (rate->idx >= 0 && rate->count &&
616 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
617 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
618 u8 bw;
619 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
620 &bw);
621
622 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
623
624 val = MT_TXD6_FIXED_BW |
625 FIELD_PREP(MT_TXD6_BW, bw) |
626 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
627 txwi[6] |= cpu_to_le32(val);
628
629 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
630 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
631
632 if (info->flags & IEEE80211_TX_CTL_LDPC)
633 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
634
635 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
636 IEEE80211_TX_RC_VHT_MCS)))
637 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
638
639 tx_count = rate->count;
640 }
641
642 if (!ieee80211_is_beacon(fc)) {
643 struct ieee80211_hw *hw = mt76_hw(dev);
644
645 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
646 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
647 val |= MT_TXD5_SW_POWER_MGMT;
648 txwi[5] = cpu_to_le32(val);
649 } else {
650 txwi[5] = 0;
651 /* use maximum tx count for beacons */
652 tx_count = 0x1f;
653 }
654
655 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
656 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
657 seqno = le16_to_cpu(hdr->seq_ctrl);
658
659 if (ieee80211_is_back_req(hdr->frame_control)) {
660 struct ieee80211_bar *bar;
661
662 bar = (struct ieee80211_bar *)skb->data;
663 seqno = le16_to_cpu(bar->start_seq_num);
664 }
665
666 val |= MT_TXD3_SN_VALID |
667 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
668 }
669
670 txwi[3] |= cpu_to_le32(val);
671
672 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
673 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
674
675 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
676 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
677 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
678 if (!is_mmio)
679 txwi[8] = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
680 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
681
682 return 0;
683 }
684 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
685
686 static void
687 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp)
688 {
689 int i;
690
691 for (i = 1; i < txp->nbuf; i++)
692 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
693 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
694 }
695
696 static void
697 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp)
698 {
699 u32 last_mask;
700 int i;
701
702 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST;
703
704 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
705 struct mt7615_txp_ptr *ptr = &txp->ptr[i];
706 bool last;
707 u16 len;
708
709 len = le16_to_cpu(ptr->len0);
710 last = len & last_mask;
711 len &= MT_TXD_LEN_MASK;
712 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
713 DMA_TO_DEVICE);
714 if (last)
715 break;
716
717 len = le16_to_cpu(ptr->len1);
718 last = len & last_mask;
719 len &= MT_TXD_LEN_MASK;
720 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
721 DMA_TO_DEVICE);
722 if (last)
723 break;
724 }
725 }
726
727 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
728 struct mt76_txwi_cache *t)
729 {
730 struct mt7615_txp_common *txp;
731
732 txp = mt7615_txwi_to_txp(dev, t);
733 if (is_mt7615(dev))
734 mt7615_txp_skb_unmap_fw(dev, &txp->fw);
735 else
736 mt7615_txp_skb_unmap_hw(dev, &txp->hw);
737 }
738 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap);
739
740 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
741 {
742 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
743 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
744
745 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
746 0, 5000);
747 }
748
749 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
750 {
751 static const u8 ac_to_tid[4] = {
752 [IEEE80211_AC_BE] = 0,
753 [IEEE80211_AC_BK] = 1,
754 [IEEE80211_AC_VI] = 4,
755 [IEEE80211_AC_VO] = 6
756 };
757 static const u8 hw_queue_map[] = {
758 [IEEE80211_AC_BK] = 0,
759 [IEEE80211_AC_BE] = 1,
760 [IEEE80211_AC_VI] = 2,
761 [IEEE80211_AC_VO] = 3,
762 };
763 struct ieee80211_sta *sta;
764 struct mt7615_sta *msta;
765 u32 addr, tx_time[4], rx_time[4];
766 struct list_head sta_poll_list;
767 int i;
768
769 INIT_LIST_HEAD(&sta_poll_list);
770 spin_lock_bh(&dev->sta_poll_lock);
771 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
772 spin_unlock_bh(&dev->sta_poll_lock);
773
774 while (!list_empty(&sta_poll_list)) {
775 bool clear = false;
776
777 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
778 poll_list);
779 list_del_init(&msta->poll_list);
780
781 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
782
783 for (i = 0; i < 4; i++, addr += 8) {
784 u32 tx_last = msta->airtime_ac[i];
785 u32 rx_last = msta->airtime_ac[i + 4];
786
787 msta->airtime_ac[i] = mt76_rr(dev, addr);
788 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
789 tx_time[i] = msta->airtime_ac[i] - tx_last;
790 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
791
792 if ((tx_last | rx_last) & BIT(30))
793 clear = true;
794 }
795
796 if (clear) {
797 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
798 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
799 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
800 }
801
802 if (!msta->wcid.sta)
803 continue;
804
805 sta = container_of((void *)msta, struct ieee80211_sta,
806 drv_priv);
807 for (i = 0; i < 4; i++) {
808 u32 tx_cur = tx_time[i];
809 u32 rx_cur = rx_time[hw_queue_map[i]];
810 u8 tid = ac_to_tid[i];
811
812 if (!tx_cur && !rx_cur)
813 continue;
814
815 ieee80211_sta_register_airtime(sta, tid, tx_cur,
816 rx_cur);
817 }
818 }
819 }
820 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
821
822 static void
823 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
824 struct ieee80211_tx_rate *probe_rate,
825 struct ieee80211_tx_rate *rates,
826 struct mt7615_rate_desc *rd)
827 {
828 struct mt7615_dev *dev = phy->dev;
829 struct mt76_phy *mphy = phy->mt76;
830 struct ieee80211_tx_rate *ref;
831 bool rateset, stbc = false;
832 int n_rates = sta->n_rates;
833 u8 bw, bw_prev;
834 int i, j;
835
836 for (i = n_rates; i < 4; i++)
837 rates[i] = rates[n_rates - 1];
838
839 rateset = !(sta->rate_set_tsf & BIT(0));
840 memcpy(sta->rateset[rateset].rates, rates,
841 sizeof(sta->rateset[rateset].rates));
842 if (probe_rate) {
843 sta->rateset[rateset].probe_rate = *probe_rate;
844 ref = &sta->rateset[rateset].probe_rate;
845 } else {
846 sta->rateset[rateset].probe_rate.idx = -1;
847 ref = &sta->rateset[rateset].rates[0];
848 }
849
850 rates = sta->rateset[rateset].rates;
851 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
852 /*
853 * We don't support switching between short and long GI
854 * within the rate set. For accurate tx status reporting, we
855 * need to make sure that flags match.
856 * For improved performance, avoid duplicate entries by
857 * decrementing the MCS index if necessary
858 */
859 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
860 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
861
862 for (j = 0; j < i; j++) {
863 if (rates[i].idx != rates[j].idx)
864 continue;
865 if ((rates[i].flags ^ rates[j].flags) &
866 (IEEE80211_TX_RC_40_MHZ_WIDTH |
867 IEEE80211_TX_RC_80_MHZ_WIDTH |
868 IEEE80211_TX_RC_160_MHZ_WIDTH))
869 continue;
870
871 if (!rates[i].idx)
872 continue;
873
874 rates[i].idx--;
875 }
876 }
877
878 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
879 bw_prev = bw;
880
881 if (probe_rate) {
882 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
883 stbc, &bw);
884 if (bw)
885 rd->bw_idx = 1;
886 else
887 bw_prev = 0;
888 } else {
889 rd->probe_val = rd->val[0];
890 }
891
892 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
893 if (bw_prev) {
894 rd->bw_idx = 3;
895 bw_prev = bw;
896 }
897
898 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
899 if (bw_prev) {
900 rd->bw_idx = 5;
901 bw_prev = bw;
902 }
903
904 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
905 if (bw_prev)
906 rd->bw_idx = 7;
907
908 rd->rateset = rateset;
909 rd->bw = bw;
910 }
911
912 static int
913 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
914 struct ieee80211_tx_rate *probe_rate,
915 struct ieee80211_tx_rate *rates)
916 {
917 struct mt7615_dev *dev = phy->dev;
918 struct mt7615_wtbl_rate_desc *wrd;
919
920 if (work_pending(&dev->rate_work))
921 return -EBUSY;
922
923 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC);
924 if (!wrd)
925 return -ENOMEM;
926
927 wrd->sta = sta;
928 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
929 &wrd->rate);
930 list_add_tail(&wrd->node, &dev->wrd_head);
931 queue_work(dev->mt76.wq, &dev->rate_work);
932
933 return 0;
934 }
935
936 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid)
937 {
938 u32 addr, val, val2;
939 u8 offset;
940
941 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4;
942
943 offset = tid * 12;
944 addr += 4 * (offset / 32);
945 offset %= 32;
946
947 val = mt76_rr(dev, addr);
948 val >>= (tid % 32);
949
950 if (offset > 20) {
951 addr += 4;
952 val2 = mt76_rr(dev, addr);
953 val |= val2 << (32 - offset);
954 }
955
956 return val & GENMASK(11, 0);
957 }
958
959 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
960 struct ieee80211_tx_rate *probe_rate,
961 struct ieee80211_tx_rate *rates)
962 {
963 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
964 struct mt7615_dev *dev = phy->dev;
965 struct mt7615_rate_desc rd;
966 u32 w5, w27, addr;
967
968 if (!mt76_is_mmio(&dev->mt76)) {
969 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
970 return;
971 }
972
973 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
974 return;
975
976 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
977 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
978
979 addr = mt7615_mac_wtbl_addr(dev, wcid);
980 w27 = mt76_rr(dev, addr + 27 * 4);
981 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
982 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
983
984 w5 = mt76_rr(dev, addr + 5 * 4);
985 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
986 MT_WTBL_W5_MPDU_OK_COUNT |
987 MT_WTBL_W5_MPDU_FAIL_COUNT |
988 MT_WTBL_W5_RATE_IDX);
989 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
990 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
991 rd.bw_idx ? rd.bw_idx - 1 : 7);
992
993 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
994
995 mt76_wr(dev, MT_WTBL_RIUCR1,
996 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
997 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
998 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
999
1000 mt76_wr(dev, MT_WTBL_RIUCR2,
1001 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
1002 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
1003 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
1004 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
1005
1006 mt76_wr(dev, MT_WTBL_RIUCR3,
1007 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
1008 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
1009 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
1010
1011 mt76_wr(dev, MT_WTBL_UPDATE,
1012 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
1013 MT_WTBL_UPDATE_RATE_UPDATE |
1014 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
1015
1016 mt76_wr(dev, addr + 27 * 4, w27);
1017
1018 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
1019 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
1020 sta->rate_set_tsf |= rd.rateset;
1021
1022 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
1023 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
1024
1025 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
1026 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
1027 sta->rate_probe = !!probe_rate;
1028 }
1029 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
1030
1031 static int
1032 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1033 struct ieee80211_key_conf *key,
1034 enum mt7615_cipher_type cipher,
1035 enum set_key_cmd cmd)
1036 {
1037 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
1038 u8 data[32] = {};
1039
1040 if (key->keylen > sizeof(data))
1041 return -EINVAL;
1042
1043 mt76_rr_copy(dev, addr, data, sizeof(data));
1044 if (cmd == SET_KEY) {
1045 if (cipher == MT_CIPHER_TKIP) {
1046 /* Rx/Tx MIC keys are swapped */
1047 memcpy(data, key->key, 16);
1048 memcpy(data + 16, key->key + 24, 8);
1049 memcpy(data + 24, key->key + 16, 8);
1050 } else {
1051 if (cipher != MT_CIPHER_BIP_CMAC_128 && wcid->cipher)
1052 memmove(data + 16, data, 16);
1053 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1054 memcpy(data, key->key, key->keylen);
1055 else if (cipher == MT_CIPHER_BIP_CMAC_128)
1056 memcpy(data + 16, key->key, 16);
1057 }
1058 } else {
1059 if (wcid->cipher & ~BIT(cipher)) {
1060 if (cipher != MT_CIPHER_BIP_CMAC_128)
1061 memmove(data, data + 16, 16);
1062 memset(data + 16, 0, 16);
1063 } else {
1064 memset(data, 0, sizeof(data));
1065 }
1066 }
1067 mt76_wr_copy(dev, addr, data, sizeof(data));
1068
1069 return 0;
1070 }
1071
1072 static int
1073 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1074 enum mt7615_cipher_type cipher,
1075 int keyidx, enum set_key_cmd cmd)
1076 {
1077 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1078
1079 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1080 return -ETIMEDOUT;
1081
1082 w0 = mt76_rr(dev, addr);
1083 w1 = mt76_rr(dev, addr + 4);
1084 if (cmd == SET_KEY) {
1085 w0 |= MT_WTBL_W0_RX_KEY_VALID |
1086 FIELD_PREP(MT_WTBL_W0_RX_IK_VALID,
1087 cipher == MT_CIPHER_BIP_CMAC_128);
1088 if (cipher != MT_CIPHER_BIP_CMAC_128 ||
1089 !wcid->cipher)
1090 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1091 } else {
1092 if (!(wcid->cipher & ~BIT(cipher)))
1093 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID |
1094 MT_WTBL_W0_KEY_IDX);
1095 if (cipher == MT_CIPHER_BIP_CMAC_128)
1096 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1097 }
1098 mt76_wr(dev, MT_WTBL_RICR0, w0);
1099 mt76_wr(dev, MT_WTBL_RICR1, w1);
1100
1101 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1102 MT_WTBL_UPDATE_RXINFO_UPDATE))
1103 return -ETIMEDOUT;
1104
1105 return 0;
1106 }
1107
1108 static void
1109 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1110 enum mt7615_cipher_type cipher,
1111 enum set_key_cmd cmd)
1112 {
1113 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1114
1115 if (cmd == SET_KEY) {
1116 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1117 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1118 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1119 } else {
1120 if (cipher != MT_CIPHER_BIP_CMAC_128 &&
1121 wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128))
1122 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1123 FIELD_PREP(MT_WTBL_W2_KEY_TYPE,
1124 MT_CIPHER_BIP_CMAC_128));
1125 else if (!(wcid->cipher & ~BIT(cipher)))
1126 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1127 }
1128 }
1129
1130 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1131 struct mt76_wcid *wcid,
1132 struct ieee80211_key_conf *key,
1133 enum set_key_cmd cmd)
1134 {
1135 enum mt7615_cipher_type cipher;
1136 int err;
1137
1138 cipher = mt7615_mac_get_cipher(key->cipher);
1139 if (cipher == MT_CIPHER_NONE)
1140 return -EOPNOTSUPP;
1141
1142 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cmd);
1143 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cmd);
1144 if (err < 0)
1145 return err;
1146
1147 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx, cmd);
1148 if (err < 0)
1149 return err;
1150
1151 if (cmd == SET_KEY)
1152 wcid->cipher |= BIT(cipher);
1153 else
1154 wcid->cipher &= ~BIT(cipher);
1155
1156 return 0;
1157 }
1158
1159 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1160 struct mt76_wcid *wcid,
1161 struct ieee80211_key_conf *key,
1162 enum set_key_cmd cmd)
1163 {
1164 int err;
1165
1166 spin_lock_bh(&dev->mt76.lock);
1167 err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd);
1168 spin_unlock_bh(&dev->mt76.lock);
1169
1170 return err;
1171 }
1172
1173 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1174 struct ieee80211_tx_info *info, __le32 *txs_data)
1175 {
1176 struct ieee80211_supported_band *sband;
1177 struct mt7615_rate_set *rs;
1178 struct mt76_phy *mphy;
1179 int first_idx = 0, last_idx;
1180 int i, idx, count;
1181 bool fixed_rate, ack_timeout;
1182 bool probe, ampdu, cck = false;
1183 bool rs_idx;
1184 u32 rate_set_tsf;
1185 u32 final_rate, final_rate_flags, final_nss, txs;
1186
1187 fixed_rate = info->status.rates[0].count;
1188 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1189
1190 txs = le32_to_cpu(txs_data[1]);
1191 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
1192
1193 txs = le32_to_cpu(txs_data[3]);
1194 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1195 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1196
1197 txs = le32_to_cpu(txs_data[0]);
1198 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1199 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1200
1201 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1202 return false;
1203
1204 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1205 return false;
1206
1207 if (!ack_timeout)
1208 info->flags |= IEEE80211_TX_STAT_ACK;
1209
1210 info->status.ampdu_len = 1;
1211 info->status.ampdu_ack_len = !!(info->flags &
1212 IEEE80211_TX_STAT_ACK);
1213
1214 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1215 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1216
1217 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1218
1219 if (fixed_rate && !probe) {
1220 info->status.rates[0].count = count;
1221 i = 0;
1222 goto out;
1223 }
1224
1225 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1226 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
1227 rate_set_tsf) < 1000000);
1228 rs_idx ^= rate_set_tsf & BIT(0);
1229 rs = &sta->rateset[rs_idx];
1230
1231 if (!first_idx && rs->probe_rate.idx >= 0) {
1232 info->status.rates[0] = rs->probe_rate;
1233
1234 spin_lock_bh(&dev->mt76.lock);
1235 if (sta->rate_probe) {
1236 struct mt7615_phy *phy = &dev->phy;
1237
1238 if (sta->wcid.ext_phy && dev->mt76.phy2)
1239 phy = dev->mt76.phy2->priv;
1240
1241 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1242 }
1243 spin_unlock_bh(&dev->mt76.lock);
1244 } else {
1245 info->status.rates[0] = rs->rates[first_idx / 2];
1246 }
1247 info->status.rates[0].count = 0;
1248
1249 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1250 struct ieee80211_tx_rate *cur_rate;
1251 int cur_count;
1252
1253 cur_rate = &rs->rates[idx / 2];
1254 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1255 count -= cur_count;
1256
1257 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1258 cur_rate->flags != info->status.rates[i].flags)) {
1259 i++;
1260 if (i == ARRAY_SIZE(info->status.rates)) {
1261 i--;
1262 break;
1263 }
1264
1265 info->status.rates[i] = *cur_rate;
1266 info->status.rates[i].count = 0;
1267 }
1268
1269 info->status.rates[i].count += cur_count;
1270 }
1271
1272 out:
1273 final_rate_flags = info->status.rates[i].flags;
1274
1275 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1276 case MT_PHY_TYPE_CCK:
1277 cck = true;
1278 fallthrough;
1279 case MT_PHY_TYPE_OFDM:
1280 mphy = &dev->mphy;
1281 if (sta->wcid.ext_phy && dev->mt76.phy2)
1282 mphy = dev->mt76.phy2;
1283
1284 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1285 sband = &mphy->sband_5g.sband;
1286 else
1287 sband = &mphy->sband_2g.sband;
1288 final_rate &= MT_TX_RATE_IDX;
1289 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1290 cck);
1291 final_rate_flags = 0;
1292 break;
1293 case MT_PHY_TYPE_HT_GF:
1294 case MT_PHY_TYPE_HT:
1295 final_rate_flags |= IEEE80211_TX_RC_MCS;
1296 final_rate &= MT_TX_RATE_IDX;
1297 if (final_rate > 31)
1298 return false;
1299 break;
1300 case MT_PHY_TYPE_VHT:
1301 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1302
1303 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1304 final_nss--;
1305
1306 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1307 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1308 break;
1309 default:
1310 return false;
1311 }
1312
1313 info->status.rates[i].idx = final_rate;
1314 info->status.rates[i].flags = final_rate_flags;
1315
1316 return true;
1317 }
1318
1319 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1320 struct mt7615_sta *sta, int pid,
1321 __le32 *txs_data)
1322 {
1323 struct mt76_dev *mdev = &dev->mt76;
1324 struct sk_buff_head list;
1325 struct sk_buff *skb;
1326
1327 if (pid < MT_PACKET_ID_FIRST)
1328 return false;
1329
1330 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1331
1332 mt76_tx_status_lock(mdev, &list);
1333 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1334 if (skb) {
1335 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1336
1337 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1338 ieee80211_tx_info_clear_status(info);
1339 info->status.rates[0].idx = -1;
1340 }
1341
1342 mt76_tx_status_skb_done(mdev, skb, &list);
1343 }
1344 mt76_tx_status_unlock(mdev, &list);
1345
1346 return !!skb;
1347 }
1348
1349 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1350 {
1351 struct ieee80211_tx_info info = {};
1352 struct ieee80211_sta *sta = NULL;
1353 struct mt7615_sta *msta = NULL;
1354 struct mt76_wcid *wcid;
1355 struct mt76_phy *mphy = &dev->mt76.phy;
1356 __le32 *txs_data = data;
1357 u32 txs;
1358 u8 wcidx;
1359 u8 pid;
1360
1361 txs = le32_to_cpu(txs_data[0]);
1362 pid = FIELD_GET(MT_TXS0_PID, txs);
1363 txs = le32_to_cpu(txs_data[2]);
1364 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1365
1366 if (pid == MT_PACKET_ID_NO_ACK)
1367 return;
1368
1369 if (wcidx >= MT7615_WTBL_SIZE)
1370 return;
1371
1372 rcu_read_lock();
1373
1374 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1375 if (!wcid)
1376 goto out;
1377
1378 msta = container_of(wcid, struct mt7615_sta, wcid);
1379 sta = wcid_to_sta(wcid);
1380
1381 spin_lock_bh(&dev->sta_poll_lock);
1382 if (list_empty(&msta->poll_list))
1383 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1384 spin_unlock_bh(&dev->sta_poll_lock);
1385
1386 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1387 goto out;
1388
1389 if (wcidx >= MT7615_WTBL_STA || !sta)
1390 goto out;
1391
1392 if (wcid->ext_phy && dev->mt76.phy2)
1393 mphy = dev->mt76.phy2;
1394
1395 if (mt7615_fill_txs(dev, msta, &info, txs_data))
1396 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1397
1398 out:
1399 rcu_read_unlock();
1400 }
1401
1402 static void
1403 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1404 {
1405 struct mt76_dev *mdev = &dev->mt76;
1406 struct mt76_txwi_cache *txwi;
1407 __le32 *txwi_data;
1408 u32 val;
1409 u8 wcid;
1410
1411 trace_mac_tx_free(dev, token);
1412
1413 spin_lock_bh(&dev->token_lock);
1414 txwi = idr_remove(&dev->token, token);
1415 spin_unlock_bh(&dev->token_lock);
1416
1417 if (!txwi)
1418 return;
1419
1420 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi);
1421 val = le32_to_cpu(txwi_data[1]);
1422 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val);
1423
1424 mt7615_txp_skb_unmap(mdev, txwi);
1425 if (txwi->skb) {
1426 mt76_tx_complete_skb(mdev, wcid, txwi->skb);
1427 txwi->skb = NULL;
1428 }
1429
1430 mt76_put_txwi(mdev, txwi);
1431 }
1432
1433 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1434 {
1435 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1436 u8 i, count;
1437
1438 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1439 if (is_mt7615(&dev->mt76)) {
1440 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1441 } else {
1442 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1443 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
1444 }
1445
1446 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1447 if (is_mt7615(&dev->mt76)) {
1448 __le16 *token = &free->token[0];
1449
1450 for (i = 0; i < count; i++)
1451 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1452 } else {
1453 __le32 *token = (__le32 *)&free->token[0];
1454
1455 for (i = 0; i < count; i++)
1456 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1457 }
1458
1459 dev_kfree_skb(skb);
1460
1461 if (test_bit(MT76_STATE_PM, &dev->phy.mt76->state))
1462 return;
1463
1464 rcu_read_lock();
1465 mt7615_mac_sta_poll(dev);
1466 rcu_read_unlock();
1467
1468 mt7615_pm_power_save_sched(dev);
1469 mt76_worker_schedule(&dev->mt76.tx_worker);
1470 }
1471
1472 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1473 struct sk_buff *skb)
1474 {
1475 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1476 __le32 *rxd = (__le32 *)skb->data;
1477 __le32 *end = (__le32 *)&skb->data[skb->len];
1478 enum rx_pkt_type type;
1479 u16 flag;
1480
1481 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1482 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
1483 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1484 type = PKT_TYPE_NORMAL_MCU;
1485
1486 switch (type) {
1487 case PKT_TYPE_TXS:
1488 for (rxd++; rxd + 7 <= end; rxd += 7)
1489 mt7615_mac_add_txs(dev, rxd);
1490 dev_kfree_skb(skb);
1491 break;
1492 case PKT_TYPE_TXRX_NOTIFY:
1493 mt7615_mac_tx_free(dev, skb);
1494 break;
1495 case PKT_TYPE_RX_EVENT:
1496 mt7615_mcu_rx_event(dev, skb);
1497 break;
1498 case PKT_TYPE_NORMAL_MCU:
1499 case PKT_TYPE_NORMAL:
1500 if (!mt7615_mac_fill_rx(dev, skb)) {
1501 mt76_rx(&dev->mt76, q, skb);
1502 return;
1503 }
1504 fallthrough;
1505 default:
1506 dev_kfree_skb(skb);
1507 break;
1508 }
1509 }
1510 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1511
1512 static void
1513 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1514 {
1515 struct mt7615_dev *dev = phy->dev;
1516 bool ext_phy = phy != &dev->phy;
1517
1518 if (is_mt7663(&dev->mt76)) {
1519 if (ofdm)
1520 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1521 MT_WF_PHY_PD_OFDM_MASK(0),
1522 MT_WF_PHY_PD_OFDM(0, val));
1523 else
1524 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1525 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1526 MT_WF_PHY_PD_CCK(ext_phy, val));
1527 return;
1528 }
1529
1530 if (ofdm)
1531 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1532 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1533 MT_WF_PHY_PD_OFDM(ext_phy, val));
1534 else
1535 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1536 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1537 MT_WF_PHY_PD_CCK(ext_phy, val));
1538 }
1539
1540 static void
1541 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1542 {
1543 /* ofdm */
1544 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1545 /* cck */
1546 mt7615_mac_set_sensitivity(phy, 0x92, false);
1547
1548 phy->ofdm_sensitivity = -98;
1549 phy->cck_sensitivity = -110;
1550 phy->last_cca_adj = jiffies;
1551 }
1552
1553 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1554 {
1555 struct mt7615_dev *dev = phy->dev;
1556 bool ext_phy = phy != &dev->phy;
1557 u32 reg, mask;
1558
1559 mt7615_mutex_acquire(dev);
1560
1561 if (phy->scs_en == enable)
1562 goto out;
1563
1564 if (is_mt7663(&dev->mt76)) {
1565 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1566 mask = MT_WF_PHY_PD_BLK(0);
1567 } else {
1568 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1569 mask = MT_WF_PHY_PD_BLK(ext_phy);
1570 }
1571
1572 if (enable) {
1573 mt76_set(dev, reg, mask);
1574 if (is_mt7622(&dev->mt76)) {
1575 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1576 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1577 }
1578 } else {
1579 mt76_clear(dev, reg, mask);
1580 }
1581
1582 mt7615_mac_set_default_sensitivity(phy);
1583 phy->scs_en = enable;
1584
1585 out:
1586 mt7615_mutex_release(dev);
1587 }
1588
1589 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1590 {
1591 u32 rxtd, reg;
1592
1593 if (is_mt7663(&dev->mt76))
1594 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1595 else
1596 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1597
1598 if (ext_phy)
1599 rxtd = MT_WF_PHY_RXTD2(10);
1600 else
1601 rxtd = MT_WF_PHY_RXTD(12);
1602
1603 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1604 mt76_set(dev, reg, 0x5 << 12);
1605 }
1606
1607 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1608 {
1609 struct mt7615_dev *dev = phy->dev;
1610 bool ext_phy = phy != &dev->phy;
1611 u32 reg;
1612
1613 if (is_mt7663(&dev->mt76))
1614 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1615 else
1616 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1617
1618 /* reset PD and MDRDY counters */
1619 mt76_clear(dev, reg, GENMASK(22, 20));
1620 mt76_set(dev, reg, BIT(22) | BIT(20));
1621 }
1622
1623 static void
1624 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1625 u32 rts_err_rate, bool ofdm)
1626 {
1627 struct mt7615_dev *dev = phy->dev;
1628 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1629 bool ext_phy = phy != &dev->phy;
1630 u16 def_th = ofdm ? -98 : -110;
1631 bool update = false;
1632 s8 *sensitivity;
1633 int signal;
1634
1635 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1636 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1637 if (!signal) {
1638 mt7615_mac_set_default_sensitivity(phy);
1639 return;
1640 }
1641
1642 signal = min(signal, -72);
1643 if (false_cca > 500) {
1644 if (rts_err_rate > MT_FRAC(40, 100))
1645 return;
1646
1647 /* decrease coverage */
1648 if (*sensitivity == def_th && signal > -90) {
1649 *sensitivity = -90;
1650 update = true;
1651 } else if (*sensitivity + 2 < signal) {
1652 *sensitivity += 2;
1653 update = true;
1654 }
1655 } else if ((false_cca > 0 && false_cca < 50) ||
1656 rts_err_rate > MT_FRAC(60, 100)) {
1657 /* increase coverage */
1658 if (*sensitivity - 2 >= def_th) {
1659 *sensitivity -= 2;
1660 update = true;
1661 }
1662 }
1663
1664 if (*sensitivity > signal) {
1665 *sensitivity = signal;
1666 update = true;
1667 }
1668
1669 if (update) {
1670 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1671
1672 mt7615_mac_set_sensitivity(phy, val, ofdm);
1673 phy->last_cca_adj = jiffies;
1674 }
1675 }
1676
1677 static void
1678 mt7615_mac_scs_check(struct mt7615_phy *phy)
1679 {
1680 struct mt7615_dev *dev = phy->dev;
1681 struct mib_stats *mib = &phy->mib;
1682 u32 val, rts_err_rate = 0;
1683 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1684 bool ext_phy = phy != &dev->phy;
1685
1686 if (!phy->scs_en)
1687 return;
1688
1689 if (is_mt7663(&dev->mt76))
1690 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1691 else
1692 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1693 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1694 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1695
1696 if (is_mt7663(&dev->mt76))
1697 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1698 else
1699 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1700 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1701 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1702
1703 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1704 phy->false_cca_cck = pd_cck - mdrdy_cck;
1705 mt7615_mac_cca_stats_reset(phy);
1706
1707 if (mib->rts_cnt + mib->rts_retries_cnt)
1708 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1709 mib->rts_cnt + mib->rts_retries_cnt);
1710
1711 /* cck */
1712 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1713 /* ofdm */
1714 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1715
1716 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1717 mt7615_mac_set_default_sensitivity(phy);
1718 }
1719
1720 static u8
1721 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1722 {
1723 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1724 u32 reg, val, sum = 0, n = 0;
1725 int i;
1726
1727 if (is_mt7663(&dev->mt76))
1728 reg = MT7663_WF_PHY_RXTD(20);
1729 else
1730 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1731
1732 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1733 val = mt76_rr(dev, reg);
1734 sum += val * nf_power[i];
1735 n += val;
1736 }
1737
1738 if (!n)
1739 return 0;
1740
1741 return sum / n;
1742 }
1743
1744 static void
1745 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1746 {
1747 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1748 struct mt7615_phy *phy = mphy->priv;
1749 struct mt76_channel_state *state;
1750 u64 busy_time, tx_time, rx_time, obss_time;
1751 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1752 int nf;
1753
1754 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1755 MT_MIB_SDR9_BUSY_MASK);
1756 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1757 MT_MIB_SDR36_TXTIME_MASK);
1758 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1759 MT_MIB_SDR37_RXTIME_MASK);
1760 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1761
1762 nf = mt7615_phy_get_nf(dev, idx);
1763 if (!phy->noise)
1764 phy->noise = nf << 4;
1765 else if (nf)
1766 phy->noise += nf - (phy->noise >> 4);
1767
1768 state = mphy->chan_state;
1769 state->cc_busy += busy_time;
1770 state->cc_tx += tx_time;
1771 state->cc_rx += rx_time + obss_time;
1772 state->cc_bss_rx += rx_time;
1773 state->noise = -(phy->noise >> 4);
1774 }
1775
1776 static void __mt7615_update_channel(struct mt7615_dev *dev)
1777 {
1778 struct mt76_dev *mdev = &dev->mt76;
1779
1780 mt7615_phy_update_channel(&mdev->phy, 0);
1781 if (mdev->phy2)
1782 mt7615_phy_update_channel(mdev->phy2, 1);
1783
1784 /* reset obss airtime */
1785 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1786 }
1787
1788 void mt7615_update_channel(struct mt76_dev *mdev)
1789 {
1790 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1791
1792 if (mt7615_pm_wake(dev))
1793 return;
1794
1795 __mt7615_update_channel(dev);
1796 mt7615_pm_power_save_sched(dev);
1797 }
1798 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1799
1800 static void mt7615_update_survey(struct mt7615_dev *dev)
1801 {
1802 struct mt76_dev *mdev = &dev->mt76;
1803 ktime_t cur_time;
1804
1805 __mt7615_update_channel(dev);
1806 cur_time = ktime_get_boottime();
1807
1808 mt76_update_survey_active_time(&mdev->phy, cur_time);
1809 if (mdev->phy2)
1810 mt76_update_survey_active_time(mdev->phy2, cur_time);
1811 }
1812
1813 static void
1814 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1815 {
1816 struct mt7615_dev *dev = phy->dev;
1817 struct mib_stats *mib = &phy->mib;
1818 bool ext_phy = phy != &dev->phy;
1819 int i, aggr;
1820 u32 val, val2;
1821
1822 memset(mib, 0, sizeof(*mib));
1823
1824 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1825 MT_MIB_SDR3_FCS_ERR_MASK);
1826
1827 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
1828 MT_MIB_AMPDU_MPDU_COUNT);
1829 if (val) {
1830 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
1831 MT_MIB_AMPDU_ACK_COUNT);
1832 mib->aggr_per = 1000 * (val - val2) / val;
1833 }
1834
1835 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1836 for (i = 0; i < 4; i++) {
1837 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1838
1839 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1840 if (val2 > mib->ack_fail_cnt)
1841 mib->ack_fail_cnt = val2;
1842
1843 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1844 if (val2 > mib->ba_miss_cnt)
1845 mib->ba_miss_cnt = val2;
1846
1847 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1848 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1849 if (val2 > mib->rts_retries_cnt) {
1850 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1851 mib->rts_retries_cnt = val2;
1852 }
1853
1854 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1855
1856 dev->mt76.aggr_stats[aggr++] += val & 0xffff;
1857 dev->mt76.aggr_stats[aggr++] += val >> 16;
1858 }
1859 }
1860
1861 void mt7615_pm_wake_work(struct work_struct *work)
1862 {
1863 struct mt7615_dev *dev;
1864 struct mt76_phy *mphy;
1865 int i;
1866
1867 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1868 pm.wake_work);
1869 mphy = dev->phy.mt76;
1870
1871 if (mt7615_mcu_set_drv_ctrl(dev)) {
1872 dev_err(mphy->dev->dev, "failed to wake device\n");
1873 goto out;
1874 }
1875
1876 spin_lock_bh(&dev->pm.txq_lock);
1877 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1878 struct mt7615_sta *msta = dev->pm.tx_q[i].msta;
1879 struct ieee80211_sta *sta = NULL;
1880 struct mt76_wcid *wcid;
1881
1882 if (!dev->pm.tx_q[i].skb)
1883 continue;
1884
1885 wcid = msta ? &msta->wcid : &dev->mt76.global_wcid;
1886 if (msta && wcid->sta)
1887 sta = container_of((void *)msta, struct ieee80211_sta,
1888 drv_priv);
1889
1890 mt76_tx(mphy, sta, wcid, dev->pm.tx_q[i].skb);
1891 dev->pm.tx_q[i].skb = NULL;
1892 }
1893 spin_unlock_bh(&dev->pm.txq_lock);
1894
1895 mt76_worker_schedule(&dev->mt76.tx_worker);
1896
1897 out:
1898 ieee80211_wake_queues(mphy->hw);
1899 complete_all(&dev->pm.wake_cmpl);
1900 }
1901
1902 int mt7615_pm_wake(struct mt7615_dev *dev)
1903 {
1904 struct mt76_phy *mphy = dev->phy.mt76;
1905
1906 if (!mt7615_firmware_offload(dev))
1907 return 0;
1908
1909 if (!mt76_is_mmio(mphy->dev))
1910 return 0;
1911
1912 if (!test_bit(MT76_STATE_PM, &mphy->state))
1913 return 0;
1914
1915 if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
1916 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state))
1917 return 0;
1918
1919 if (queue_work(dev->mt76.wq, &dev->pm.wake_work))
1920 reinit_completion(&dev->pm.wake_cmpl);
1921
1922 if (!wait_for_completion_timeout(&dev->pm.wake_cmpl, 3 * HZ)) {
1923 ieee80211_wake_queues(mphy->hw);
1924 return -ETIMEDOUT;
1925 }
1926
1927 return 0;
1928 }
1929 EXPORT_SYMBOL_GPL(mt7615_pm_wake);
1930
1931 void mt7615_pm_power_save_sched(struct mt7615_dev *dev)
1932 {
1933 struct mt76_phy *mphy = dev->phy.mt76;
1934
1935 if (!mt7615_firmware_offload(dev))
1936 return;
1937
1938 if (!mt76_is_mmio(mphy->dev))
1939 return;
1940
1941 if (!dev->pm.enable || !test_bit(MT76_STATE_RUNNING, &mphy->state))
1942 return;
1943
1944 dev->pm.last_activity = jiffies;
1945
1946 if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
1947 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state))
1948 return;
1949
1950 if (!test_bit(MT76_STATE_PM, &mphy->state))
1951 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work,
1952 dev->pm.idle_timeout);
1953 }
1954 EXPORT_SYMBOL_GPL(mt7615_pm_power_save_sched);
1955
1956 void mt7615_pm_power_save_work(struct work_struct *work)
1957 {
1958 struct mt7615_dev *dev;
1959 unsigned long delta;
1960
1961 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1962 pm.ps_work.work);
1963
1964 delta = dev->pm.idle_timeout;
1965 if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
1966 delta = dev->pm.last_activity + delta - jiffies;
1967 goto out;
1968 }
1969
1970 if (!mt7615_mcu_set_fw_ctrl(dev))
1971 return;
1972 out:
1973 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
1974 }
1975
1976 void mt7615_mac_work(struct work_struct *work)
1977 {
1978 struct mt7615_phy *phy;
1979 struct mt76_dev *mdev;
1980
1981 phy = (struct mt7615_phy *)container_of(work, struct mt7615_phy,
1982 mac_work.work);
1983 mdev = &phy->dev->mt76;
1984
1985 mt7615_mutex_acquire(phy->dev);
1986
1987 mt7615_update_survey(phy->dev);
1988 if (++phy->mac_work_count == 5) {
1989 phy->mac_work_count = 0;
1990
1991 mt7615_mac_update_mib_stats(phy);
1992 mt7615_mac_scs_check(phy);
1993 }
1994
1995 mt7615_mutex_release(phy->dev);
1996
1997 mt76_tx_status_check(mdev, NULL, false);
1998 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
1999 MT7615_WATCHDOG_TIME);
2000 }
2001
2002 static bool
2003 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
2004 {
2005 bool ret;
2006
2007 ret = wait_event_timeout(dev->reset_wait,
2008 (READ_ONCE(dev->reset_state) & state),
2009 MT7615_RESET_TIMEOUT);
2010 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
2011 return ret;
2012 }
2013
2014 static void
2015 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
2016 {
2017 struct ieee80211_hw *hw = priv;
2018 struct mt7615_dev *dev = mt7615_hw_dev(hw);
2019
2020 mt7615_mcu_add_beacon(dev, hw, vif, vif->bss_conf.enable_beacon);
2021 }
2022
2023 static void
2024 mt7615_update_beacons(struct mt7615_dev *dev)
2025 {
2026 ieee80211_iterate_active_interfaces(dev->mt76.hw,
2027 IEEE80211_IFACE_ITER_RESUME_ALL,
2028 mt7615_update_vif_beacon, dev->mt76.hw);
2029
2030 if (!dev->mt76.phy2)
2031 return;
2032
2033 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
2034 IEEE80211_IFACE_ITER_RESUME_ALL,
2035 mt7615_update_vif_beacon, dev->mt76.phy2->hw);
2036 }
2037
2038 void mt7615_dma_reset(struct mt7615_dev *dev)
2039 {
2040 int i;
2041
2042 mt76_clear(dev, MT_WPDMA_GLO_CFG,
2043 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
2044 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
2045 usleep_range(1000, 2000);
2046
2047 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
2048 for (i = 0; i < __MT_TXQ_MAX; i++)
2049 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
2050
2051 mt76_for_each_q_rx(&dev->mt76, i) {
2052 mt76_queue_rx_reset(dev, i);
2053 }
2054
2055 mt76_set(dev, MT_WPDMA_GLO_CFG,
2056 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
2057 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
2058 }
2059 EXPORT_SYMBOL_GPL(mt7615_dma_reset);
2060
2061 void mt7615_mac_reset_work(struct work_struct *work)
2062 {
2063 struct mt7615_phy *phy2;
2064 struct mt76_phy *ext_phy;
2065 struct mt7615_dev *dev;
2066
2067 dev = container_of(work, struct mt7615_dev, reset_work);
2068 ext_phy = dev->mt76.phy2;
2069 phy2 = ext_phy ? ext_phy->priv : NULL;
2070
2071 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
2072 return;
2073
2074 ieee80211_stop_queues(mt76_hw(dev));
2075 if (ext_phy)
2076 ieee80211_stop_queues(ext_phy->hw);
2077
2078 set_bit(MT76_RESET, &dev->mphy.state);
2079 set_bit(MT76_MCU_RESET, &dev->mphy.state);
2080 wake_up(&dev->mt76.mcu.wait);
2081 cancel_delayed_work_sync(&dev->phy.mac_work);
2082 del_timer_sync(&dev->phy.roc_timer);
2083 cancel_work_sync(&dev->phy.roc_work);
2084 if (phy2) {
2085 cancel_delayed_work_sync(&phy2->mac_work);
2086 del_timer_sync(&phy2->roc_timer);
2087 cancel_work_sync(&phy2->roc_work);
2088 }
2089
2090 /* lock/unlock all queues to ensure that no tx is pending */
2091 mt76_txq_schedule_all(&dev->mphy);
2092 if (ext_phy)
2093 mt76_txq_schedule_all(ext_phy);
2094
2095 mt76_worker_disable(&dev->mt76.tx_worker);
2096 napi_disable(&dev->mt76.napi[0]);
2097 napi_disable(&dev->mt76.napi[1]);
2098 napi_disable(&dev->mt76.tx_napi);
2099
2100 mt7615_mutex_acquire(dev);
2101
2102 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_STOPPED);
2103
2104 if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
2105 mt7615_dma_reset(dev);
2106
2107 mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
2108
2109 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_INIT);
2110 mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
2111 }
2112
2113 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
2114 clear_bit(MT76_RESET, &dev->mphy.state);
2115
2116 mt76_worker_enable(&dev->mt76.tx_worker);
2117 napi_enable(&dev->mt76.tx_napi);
2118 napi_schedule(&dev->mt76.tx_napi);
2119
2120 napi_enable(&dev->mt76.napi[0]);
2121 napi_schedule(&dev->mt76.napi[0]);
2122
2123 napi_enable(&dev->mt76.napi[1]);
2124 napi_schedule(&dev->mt76.napi[1]);
2125
2126 ieee80211_wake_queues(mt76_hw(dev));
2127 if (ext_phy)
2128 ieee80211_wake_queues(ext_phy->hw);
2129
2130 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
2131 mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
2132
2133 mt7615_update_beacons(dev);
2134
2135 mt7615_mutex_release(dev);
2136
2137 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
2138 MT7615_WATCHDOG_TIME);
2139 if (phy2)
2140 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
2141 MT7615_WATCHDOG_TIME);
2142
2143 }
2144
2145 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
2146 {
2147 struct mt7615_dev *dev = phy->dev;
2148
2149 if (phy->rdd_state & BIT(0))
2150 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
2151 if (phy->rdd_state & BIT(1))
2152 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
2153 }
2154
2155 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
2156 {
2157 int err;
2158
2159 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
2160 if (err < 0)
2161 return err;
2162
2163 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
2164 MT_RX_SEL0, 1);
2165 }
2166
2167 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
2168 {
2169 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2170 struct mt7615_dev *dev = phy->dev;
2171 bool ext_phy = phy != &dev->phy;
2172 int err;
2173
2174 /* start CAC */
2175 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
2176 if (err < 0)
2177 return err;
2178
2179 err = mt7615_dfs_start_rdd(dev, ext_phy);
2180 if (err < 0)
2181 return err;
2182
2183 phy->rdd_state |= BIT(ext_phy);
2184
2185 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2186 chandef->width == NL80211_CHAN_WIDTH_80P80) {
2187 err = mt7615_dfs_start_rdd(dev, 1);
2188 if (err < 0)
2189 return err;
2190
2191 phy->rdd_state |= BIT(1);
2192 }
2193
2194 return 0;
2195 }
2196
2197 static int
2198 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
2199 {
2200 const struct mt7615_dfs_radar_spec *radar_specs;
2201 struct mt7615_dev *dev = phy->dev;
2202 int err, i;
2203
2204 switch (dev->mt76.region) {
2205 case NL80211_DFS_FCC:
2206 radar_specs = &fcc_radar_specs;
2207 err = mt7615_mcu_set_fcc5_lpn(dev, 8);
2208 if (err < 0)
2209 return err;
2210 break;
2211 case NL80211_DFS_ETSI:
2212 radar_specs = &etsi_radar_specs;
2213 break;
2214 case NL80211_DFS_JP:
2215 radar_specs = &jp_radar_specs;
2216 break;
2217 default:
2218 return -EINVAL;
2219 }
2220
2221 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2222 err = mt7615_mcu_set_radar_th(dev, i,
2223 &radar_specs->radar_pattern[i]);
2224 if (err < 0)
2225 return err;
2226 }
2227
2228 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2229 }
2230
2231 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2232 {
2233 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2234 struct mt7615_dev *dev = phy->dev;
2235 bool ext_phy = phy != &dev->phy;
2236 int err;
2237
2238 if (is_mt7663(&dev->mt76))
2239 return 0;
2240
2241 if (dev->mt76.region == NL80211_DFS_UNSET) {
2242 phy->dfs_state = -1;
2243 if (phy->rdd_state)
2244 goto stop;
2245
2246 return 0;
2247 }
2248
2249 if (test_bit(MT76_SCANNING, &phy->mt76->state))
2250 return 0;
2251
2252 if (phy->dfs_state == chandef->chan->dfs_state)
2253 return 0;
2254
2255 err = mt7615_dfs_init_radar_specs(phy);
2256 if (err < 0) {
2257 phy->dfs_state = -1;
2258 goto stop;
2259 }
2260
2261 phy->dfs_state = chandef->chan->dfs_state;
2262
2263 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
2264 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
2265 return mt7615_dfs_start_radar_detector(phy);
2266
2267 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
2268 MT_RX_SEL0, 0);
2269 }
2270
2271 stop:
2272 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0);
2273 if (err < 0)
2274 return err;
2275
2276 mt7615_dfs_stop_radar_detector(phy);
2277 return 0;
2278 }
2279
2280 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy,
2281 struct ieee80211_vif *vif,
2282 bool enable)
2283 {
2284 struct mt7615_dev *dev = phy->dev;
2285 bool ext_phy = phy != &dev->phy;
2286 int err;
2287
2288 if (!mt7615_firmware_offload(dev))
2289 return -EOPNOTSUPP;
2290
2291 switch (vif->type) {
2292 case NL80211_IFTYPE_MONITOR:
2293 return 0;
2294 case NL80211_IFTYPE_MESH_POINT:
2295 case NL80211_IFTYPE_ADHOC:
2296 case NL80211_IFTYPE_AP:
2297 if (enable)
2298 phy->n_beacon_vif++;
2299 else
2300 phy->n_beacon_vif--;
2301 fallthrough;
2302 default:
2303 break;
2304 }
2305
2306 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif);
2307 if (err)
2308 return err;
2309
2310 if (phy->n_beacon_vif) {
2311 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER;
2312 mt76_clear(dev, MT_WF_RFCR(ext_phy),
2313 MT_WF_RFCR_DROP_OTHER_BEACON);
2314 } else {
2315 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
2316 mt76_set(dev, MT_WF_RFCR(ext_phy),
2317 MT_WF_RFCR_DROP_OTHER_BEACON);
2318 }
2319
2320 return 0;
2321 }
Linux with added FPC-III support