drivers/net/wireless/mediatek/mt76/mt7615/mmio.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/platform_device.h>
   4 #include <linux/pci.h>
   5
   6 #include "mt7615.h"
   7 #include "regs.h"
   8 #include "mac.h"
   9 #include "../trace.h"
  10
  11 const u32 mt7615e_reg_map[] = {
  12         [MT_TOP_CFG_BASE]       = 0x01000,
  13         [MT_HW_BASE]            = 0x01000,
  14         [MT_PCIE_REMAP_2]       = 0x02504,
  15         [MT_ARB_BASE]           = 0x20c00,
  16         [MT_HIF_BASE]           = 0x04000,
  17         [MT_CSR_BASE]           = 0x07000,
  18         [MT_PLE_BASE]           = 0x08000,
  19         [MT_PSE_BASE]           = 0x0c000,
  20         [MT_CFG_BASE]           = 0x20200,
  21         [MT_AGG_BASE]           = 0x20a00,
  22         [MT_TMAC_BASE]          = 0x21000,
  23         [MT_RMAC_BASE]          = 0x21200,
  24         [MT_DMA_BASE]           = 0x21800,
  25         [MT_PF_BASE]            = 0x22000,
  26         [MT_WTBL_BASE_ON]       = 0x23000,
  27         [MT_WTBL_BASE_OFF]      = 0x23400,
  28         [MT_LPON_BASE]          = 0x24200,
  29         [MT_MIB_BASE]           = 0x24800,
  30         [MT_WTBL_BASE_ADDR]     = 0x30000,
  31         [MT_PCIE_REMAP_BASE2]   = 0x80000,
  32         [MT_TOP_MISC_BASE]      = 0xc0000,
  33         [MT_EFUSE_ADDR_BASE]    = 0x81070000,
  34 };
  35
  36 const u32 mt7663e_reg_map[] = {
  37         [MT_TOP_CFG_BASE]       = 0x01000,
  38         [MT_HW_BASE]            = 0x02000,
  39         [MT_DMA_SHDL_BASE]      = 0x06000,
  40         [MT_PCIE_REMAP_2]       = 0x0700c,
  41         [MT_ARB_BASE]           = 0x20c00,
  42         [MT_HIF_BASE]           = 0x04000,
  43         [MT_CSR_BASE]           = 0x07000,
  44         [MT_PLE_BASE]           = 0x08000,
  45         [MT_PSE_BASE]           = 0x0c000,
  46         [MT_PP_BASE]            = 0x0e000,
  47         [MT_CFG_BASE]           = 0x20000,
  48         [MT_AGG_BASE]           = 0x22000,
  49         [MT_TMAC_BASE]          = 0x24000,
  50         [MT_RMAC_BASE]          = 0x25000,
  51         [MT_DMA_BASE]           = 0x27000,
  52         [MT_PF_BASE]            = 0x28000,
  53         [MT_WTBL_BASE_ON]       = 0x29000,
  54         [MT_WTBL_BASE_OFF]      = 0x29800,
  55         [MT_LPON_BASE]          = 0x2b000,
  56         [MT_MIB_BASE]           = 0x2d000,
  57         [MT_WTBL_BASE_ADDR]     = 0x30000,
  58         [MT_PCIE_REMAP_BASE2]   = 0x90000,
  59         [MT_TOP_MISC_BASE]      = 0xc0000,
  60         [MT_EFUSE_ADDR_BASE]    = 0x78011000,
  61 };
  62
  63 u32 mt7615_reg_map(struct mt7615_dev *dev, u32 addr)
  64 {
  65         u32 base, offset;
  66
  67         if (is_mt7663(&dev->mt76)) {
  68                 base = addr & MT7663_MCU_PCIE_REMAP_2_BASE;
  69                 offset = addr & MT7663_MCU_PCIE_REMAP_2_OFFSET;
  70         } else {
  71                 base = addr & MT_MCU_PCIE_REMAP_2_BASE;
  72                 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET;
  73         }
  74         mt76_wr(dev, MT_MCU_PCIE_REMAP_2, base);
  75
  76         return MT_PCIE_REMAP_BASE_2 + offset;
  77 }
  78
  79 static void
  80 mt7615_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
  81 {
  82         struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
  83
  84         mt7615_irq_enable(dev, MT_INT_RX_DONE(q));
  85 }
  86
  87 static irqreturn_t mt7615_irq_handler(int irq, void *dev_instance)
  88 {
  89         struct mt7615_dev *dev = dev_instance;
  90
  91         mt76_wr(dev, MT_INT_MASK_CSR, 0);
  92
  93         if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
  94                 return IRQ_NONE;
  95
  96         tasklet_schedule(&dev->irq_tasklet);
  97
  98         return IRQ_HANDLED;
  99 }
 100
 101 static void mt7615_irq_tasklet(struct tasklet_struct *t)
 102 {
 103         struct mt7615_dev *dev = from_tasklet(dev, t, irq_tasklet);
 104         u32 intr, mask = 0, tx_mcu_mask = mt7615_tx_mcu_int_mask(dev);
 105
 106         mt76_wr(dev, MT_INT_MASK_CSR, 0);
 107
 108         intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
 109         intr &= dev->mt76.mmio.irqmask;
 110         mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
 111
 112         trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
 113
 114         mask |= intr & MT_INT_RX_DONE_ALL;
 115         if (intr & tx_mcu_mask)
 116                 mask |= tx_mcu_mask;
 117         mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
 118
 119         if (intr & tx_mcu_mask)
 120                 napi_schedule(&dev->mt76.tx_napi);
 121
 122         if (intr & MT_INT_RX_DONE(0))
 123                 napi_schedule(&dev->mt76.napi[0]);
 124
 125         if (intr & MT_INT_RX_DONE(1))
 126                 napi_schedule(&dev->mt76.napi[1]);
 127
 128         if (intr & MT_INT_MCU_CMD) {
 129                 u32 val = mt76_rr(dev, MT_MCU_CMD);
 130
 131                 if (val & MT_MCU_CMD_ERROR_MASK) {
 132                         dev->reset_state = val;
 133                         ieee80211_queue_work(mt76_hw(dev), &dev->reset_work);
 134                         wake_up(&dev->reset_wait);
 135                 }
 136         }
 137 }
 138
 139 static u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr)
 140 {
 141         if (addr < 0x100000)
 142                 return addr;
 143
 144         return mt7615_reg_map(dev, addr);
 145 }
 146
 147 static u32 mt7615_rr(struct mt76_dev *mdev, u32 offset)
 148 {
 149         struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
 150         u32 addr = __mt7615_reg_addr(dev, offset);
 151
 152         return dev->bus_ops->rr(mdev, addr);
 153 }
 154
 155 static void mt7615_wr(struct mt76_dev *mdev, u32 offset, u32 val)
 156 {
 157         struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
 158         u32 addr = __mt7615_reg_addr(dev, offset);
 159
 160         dev->bus_ops->wr(mdev, addr, val);
 161 }
 162
 163 static u32 mt7615_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
 164 {
 165         struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
 166         u32 addr = __mt7615_reg_addr(dev, offset);
 167
 168         return dev->bus_ops->rmw(mdev, addr, mask, val);
 169 }
 170
 171 int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
 172                       int irq, const u32 *map)
 173 {
 174         static const struct mt76_driver_ops drv_ops = {
 175                 /* txwi_size = txd size + txp size */
 176                 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7615_txp_common),
 177                 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
 178                 .survey_flags = SURVEY_INFO_TIME_TX |
 179                                 SURVEY_INFO_TIME_RX |
 180                                 SURVEY_INFO_TIME_BSS_RX,
 181                 .tx_prepare_skb = mt7615_tx_prepare_skb,
 182                 .tx_complete_skb = mt7615_tx_complete_skb,
 183                 .rx_skb = mt7615_queue_rx_skb,
 184                 .rx_poll_complete = mt7615_rx_poll_complete,
 185                 .sta_ps = mt7615_sta_ps,
 186                 .sta_add = mt7615_mac_sta_add,
 187                 .sta_remove = mt7615_mac_sta_remove,
 188                 .update_survey = mt7615_update_channel,
 189         };
 190         struct mt76_bus_ops *bus_ops;
 191         struct ieee80211_ops *ops;
 192         struct mt7615_dev *dev;
 193         struct mt76_dev *mdev;
 194         int ret;
 195
 196         ops = devm_kmemdup(pdev, &mt7615_ops, sizeof(mt7615_ops), GFP_KERNEL);
 197         if (!ops)
 198                 return -ENOMEM;
 199
 200         mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops);
 201         if (!mdev)
 202                 return -ENOMEM;
 203
 204         dev = container_of(mdev, struct mt7615_dev, mt76);
 205         mt76_mmio_init(&dev->mt76, mem_base);
 206         tasklet_setup(&dev->irq_tasklet, mt7615_irq_tasklet);
 207
 208         dev->reg_map = map;
 209         dev->ops = ops;
 210         mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
 211                     (mt76_rr(dev, MT_HW_REV) & 0xff);
 212         dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
 213
 214         dev->bus_ops = dev->mt76.bus;
 215         bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
 216                                GFP_KERNEL);
 217         if (!bus_ops) {
 218                 ret = -ENOMEM;
 219                 goto error;
 220         }
 221
 222         bus_ops->rr = mt7615_rr;
 223         bus_ops->wr = mt7615_wr;
 224         bus_ops->rmw = mt7615_rmw;
 225         dev->mt76.bus = bus_ops;
 226
 227         mt76_wr(dev, MT_INT_MASK_CSR, 0);
 228
 229         ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler,
 230                                IRQF_SHARED, KBUILD_MODNAME, dev);
 231         if (ret)
 232                 goto error;
 233
 234         if (is_mt7663(mdev))
 235                 mt76_wr(dev, MT_PCIE_IRQ_ENABLE, 1);
 236
 237         ret = mt7615_register_device(dev);
 238         if (ret)
 239                 goto error;
 240
 241         return 0;
 242 error:
 243         mt76_free_device(&dev->mt76);
 244
 245         return ret;
 246 }
 247
 248 static int __init mt7615_init(void)
 249 {
 250         int ret;
 251
 252         ret = pci_register_driver(&mt7615_pci_driver);
 253         if (ret)
 254                 return ret;
 255
 256         if (IS_ENABLED(CONFIG_MT7622_WMAC)) {
 257                 ret = platform_driver_register(&mt7622_wmac_driver);
 258                 if (ret)
 259                         pci_unregister_driver(&mt7615_pci_driver);
 260         }
 261
 262         return ret;
 263 }
 264
 265 static void __exit mt7615_exit(void)
 266 {
 267         if (IS_ENABLED(CONFIG_MT7622_WMAC))
 268                 platform_driver_unregister(&mt7622_wmac_driver);
 269         pci_unregister_driver(&mt7615_pci_driver);
 270 }
 271
 272 module_init(mt7615_init);
 273 module_exit(mt7615_exit);
 274 MODULE_LICENSE("Dual BSD/GPL");