1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
4 * Author: Felix Fietkau <nbd@nbd.name>
5 * Lorenzo Bianconi <lorenzo@kernel.org>
6 * Sean Wang <sean.wang@mediatek.com>
9 #include <linux/kernel.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/sdio_ids.h>
15 #include <linux/mmc/sdio_func.h>
21 static const struct sdio_device_id mt7663s_table
[] = {
22 { SDIO_DEVICE(SDIO_VENDOR_ID_MEDIATEK
, 0x7603) },
23 { } /* Terminating entry */
26 static u32
mt7663s_read_whisr(struct mt76_dev
*dev
)
28 return sdio_readl(dev
->sdio
.func
, MCR_WHISR
, NULL
);
31 u32
mt7663s_read_pcr(struct mt7615_dev
*dev
)
33 struct mt76_sdio
*sdio
= &dev
->mt76
.sdio
;
35 return sdio_readl(sdio
->func
, MCR_WHLPCR
, NULL
);
38 static u32
mt7663s_read_mailbox(struct mt76_dev
*dev
, u32 offset
)
40 struct sdio_func
*func
= dev
->sdio
.func
;
44 sdio_claim_host(func
);
46 sdio_writel(func
, offset
, MCR_H2DSM0R
, &err
);
48 dev_err(dev
->dev
, "failed setting address [err=%d]\n", err
);
52 sdio_writel(func
, H2D_SW_INT_READ
, MCR_WSICR
, &err
);
54 dev_err(dev
->dev
, "failed setting read mode [err=%d]\n", err
);
58 err
= readx_poll_timeout(mt7663s_read_whisr
, dev
, status
,
59 status
& H2D_SW_INT_READ
, 0, 1000000);
61 dev_err(dev
->dev
, "query whisr timeout\n");
65 sdio_writel(func
, H2D_SW_INT_READ
, MCR_WHISR
, &err
);
67 dev_err(dev
->dev
, "failed setting read mode [err=%d]\n", err
);
71 val
= sdio_readl(func
, MCR_H2DSM0R
, &err
);
73 dev_err(dev
->dev
, "failed reading h2dsm0r [err=%d]\n", err
);
78 dev_err(dev
->dev
, "register mismatch\n");
83 val
= sdio_readl(func
, MCR_D2HRM1R
, &err
);
85 dev_err(dev
->dev
, "failed reading d2hrm1r [err=%d]\n", err
);
88 sdio_release_host(func
);
93 static void mt7663s_write_mailbox(struct mt76_dev
*dev
, u32 offset
, u32 val
)
95 struct sdio_func
*func
= dev
->sdio
.func
;
99 sdio_claim_host(func
);
101 sdio_writel(func
, offset
, MCR_H2DSM0R
, &err
);
103 dev_err(dev
->dev
, "failed setting address [err=%d]\n", err
);
107 sdio_writel(func
, val
, MCR_H2DSM1R
, &err
);
110 "failed setting write value [err=%d]\n", err
);
114 sdio_writel(func
, H2D_SW_INT_WRITE
, MCR_WSICR
, &err
);
116 dev_err(dev
->dev
, "failed setting write mode [err=%d]\n", err
);
120 err
= readx_poll_timeout(mt7663s_read_whisr
, dev
, status
,
121 status
& H2D_SW_INT_WRITE
, 0, 1000000);
123 dev_err(dev
->dev
, "query whisr timeout\n");
127 sdio_writel(func
, H2D_SW_INT_WRITE
, MCR_WHISR
, &err
);
129 dev_err(dev
->dev
, "failed setting write mode [err=%d]\n", err
);
133 val
= sdio_readl(func
, MCR_H2DSM0R
, &err
);
135 dev_err(dev
->dev
, "failed reading h2dsm0r [err=%d]\n", err
);
140 dev_err(dev
->dev
, "register mismatch\n");
143 sdio_release_host(func
);
146 static u32
mt7663s_rr(struct mt76_dev
*dev
, u32 offset
)
148 if (test_bit(MT76_STATE_MCU_RUNNING
, &dev
->phy
.state
))
149 return dev
->mcu_ops
->mcu_rr(dev
, offset
);
151 return mt7663s_read_mailbox(dev
, offset
);
154 static void mt7663s_wr(struct mt76_dev
*dev
, u32 offset
, u32 val
)
156 if (test_bit(MT76_STATE_MCU_RUNNING
, &dev
->phy
.state
))
157 dev
->mcu_ops
->mcu_wr(dev
, offset
, val
);
159 mt7663s_write_mailbox(dev
, offset
, val
);
162 static u32
mt7663s_rmw(struct mt76_dev
*dev
, u32 offset
, u32 mask
, u32 val
)
164 val
|= mt7663s_rr(dev
, offset
) & ~mask
;
165 mt7663s_wr(dev
, offset
, val
);
170 static void mt7663s_write_copy(struct mt76_dev
*dev
, u32 offset
,
171 const void *data
, int len
)
173 const u32
*val
= data
;
176 for (i
= 0; i
< len
/ sizeof(u32
); i
++) {
177 mt7663s_wr(dev
, offset
, val
[i
]);
178 offset
+= sizeof(u32
);
182 static void mt7663s_read_copy(struct mt76_dev
*dev
, u32 offset
,
188 for (i
= 0; i
< len
/ sizeof(u32
); i
++) {
189 val
[i
] = mt7663s_rr(dev
, offset
);
190 offset
+= sizeof(u32
);
194 static int mt7663s_wr_rp(struct mt76_dev
*dev
, u32 base
,
195 const struct mt76_reg_pair
*data
,
200 for (i
= 0; i
< len
; i
++) {
201 mt7663s_wr(dev
, data
->reg
, data
->value
);
208 static int mt7663s_rd_rp(struct mt76_dev
*dev
, u32 base
,
209 struct mt76_reg_pair
*data
,
214 for (i
= 0; i
< len
; i
++) {
215 data
->value
= mt7663s_rr(dev
, data
->reg
);
222 static void mt7663s_init_work(struct work_struct
*work
)
224 struct mt7615_dev
*dev
;
226 dev
= container_of(work
, struct mt7615_dev
, mcu_work
);
227 if (mt7663s_mcu_init(dev
))
230 mt7615_mcu_set_eeprom(dev
);
231 mt7615_mac_init(dev
);
232 mt7615_phy_init(dev
);
233 mt7615_mcu_del_wtbl_all(dev
);
234 mt7615_check_offload_capability(dev
);
237 static int mt7663s_hw_init(struct mt7615_dev
*dev
, struct sdio_func
*func
)
242 sdio_claim_host(func
);
244 ret
= sdio_enable_func(func
);
248 /* Get ownership from the device */
249 sdio_writel(func
, WHLPCR_INT_EN_CLR
| WHLPCR_FW_OWN_REQ_CLR
,
254 ret
= readx_poll_timeout(mt7663s_read_pcr
, dev
, status
,
255 status
& WHLPCR_IS_DRIVER_OWN
, 2000, 1000000);
257 dev_err(dev
->mt76
.dev
, "Cannot get ownership from device");
261 ret
= sdio_set_block_size(func
, 512);
265 /* Enable interrupt */
266 sdio_writel(func
, WHLPCR_INT_EN_SET
, MCR_WHLPCR
, &ret
);
270 ctrl
= WHIER_RX0_DONE_INT_EN
| WHIER_TX_DONE_INT_EN
;
271 sdio_writel(func
, ctrl
, MCR_WHIER
, &ret
);
275 /* set WHISR as read clear and Rx aggregation number as 16 */
276 ctrl
= FIELD_PREP(MAX_HIF_RX_LEN_NUM
, 16);
277 sdio_writel(func
, ctrl
, MCR_WHCR
, &ret
);
281 ret
= sdio_claim_irq(func
, mt7663s_sdio_irq
);
285 sdio_release_host(func
);
290 sdio_disable_func(func
);
292 sdio_release_host(func
);
297 static int mt7663s_probe(struct sdio_func
*func
,
298 const struct sdio_device_id
*id
)
300 static const struct mt76_driver_ops drv_ops
= {
301 .txwi_size
= MT_USB_TXD_SIZE
,
302 .drv_flags
= MT_DRV_RX_DMA_HDR
,
303 .tx_prepare_skb
= mt7663_usb_sdio_tx_prepare_skb
,
304 .tx_complete_skb
= mt7663_usb_sdio_tx_complete_skb
,
305 .tx_status_data
= mt7663_usb_sdio_tx_status_data
,
306 .rx_skb
= mt7615_queue_rx_skb
,
307 .sta_ps
= mt7615_sta_ps
,
308 .sta_add
= mt7615_mac_sta_add
,
309 .sta_remove
= mt7615_mac_sta_remove
,
310 .update_survey
= mt7615_update_channel
,
312 static const struct mt76_bus_ops mt7663s_ops
= {
316 .write_copy
= mt7663s_write_copy
,
317 .read_copy
= mt7663s_read_copy
,
318 .wr_rp
= mt7663s_wr_rp
,
319 .rd_rp
= mt7663s_rd_rp
,
320 .type
= MT76_BUS_SDIO
,
322 struct ieee80211_ops
*ops
;
323 struct mt7615_dev
*dev
;
324 struct mt76_dev
*mdev
;
327 ops
= devm_kmemdup(&func
->dev
, &mt7615_ops
, sizeof(mt7615_ops
),
332 mdev
= mt76_alloc_device(&func
->dev
, sizeof(*dev
), ops
, &drv_ops
);
336 dev
= container_of(mdev
, struct mt7615_dev
, mt76
);
338 INIT_WORK(&dev
->mcu_work
, mt7663s_init_work
);
339 dev
->reg_map
= mt7663_usb_sdio_reg_map
;
341 sdio_set_drvdata(func
, dev
);
343 ret
= mt76s_init(mdev
, func
, &mt7663s_ops
);
347 ret
= mt7663s_hw_init(dev
, func
);
351 mdev
->rev
= (mt76_rr(dev
, MT_HW_CHIPID
) << 16) |
352 (mt76_rr(dev
, MT_HW_REV
) & 0xff);
353 dev_dbg(mdev
->dev
, "ASIC revision: %04x\n", mdev
->rev
);
355 mdev
->sdio
.intr_data
= devm_kmalloc(mdev
->dev
,
356 sizeof(struct mt76s_intr
),
358 if (!mdev
->sdio
.intr_data
) {
363 for (i
= 0; i
< ARRAY_SIZE(mdev
->sdio
.xmit_buf
); i
++) {
364 mdev
->sdio
.xmit_buf
[i
] = devm_kmalloc(mdev
->dev
,
367 if (!mdev
->sdio
.xmit_buf
[i
]) {
373 ret
= mt76s_alloc_queues(&dev
->mt76
);
377 ret
= mt76_worker_setup(mt76_hw(dev
), &mdev
->sdio
.txrx_worker
,
378 mt7663s_txrx_worker
, "sdio-txrx");
382 sched_set_fifo_low(mdev
->sdio
.txrx_worker
.task
);
384 ret
= mt7663_usb_sdio_register_device(dev
);
391 mt76s_deinit(&dev
->mt76
);
392 mt76_free_device(&dev
->mt76
);
397 static void mt7663s_remove(struct sdio_func
*func
)
399 struct mt7615_dev
*dev
= sdio_get_drvdata(func
);
401 if (!test_and_clear_bit(MT76_STATE_INITIALIZED
, &dev
->mphy
.state
))
404 ieee80211_unregister_hw(dev
->mt76
.hw
);
405 mt76s_deinit(&dev
->mt76
);
406 mt76_free_device(&dev
->mt76
);
410 static int mt7663s_suspend(struct device
*dev
)
412 struct sdio_func
*func
= dev_to_sdio_func(dev
);
413 struct mt7615_dev
*mdev
= sdio_get_drvdata(func
);
416 if (!test_bit(MT76_STATE_SUSPEND
, &mdev
->mphy
.state
) &&
417 mt7615_firmware_offload(mdev
)) {
420 err
= mt7615_mcu_set_hif_suspend(mdev
, true);
425 sdio_set_host_pm_flags(func
, MMC_PM_KEEP_POWER
);
427 err
= mt7615_mcu_set_fw_ctrl(mdev
);
431 mt76_worker_disable(&mdev
->mt76
.sdio
.txrx_worker
);
432 mt76_worker_disable(&mdev
->mt76
.sdio
.status_worker
);
433 mt76_worker_disable(&mdev
->mt76
.sdio
.net_worker
);
435 cancel_work_sync(&mdev
->mt76
.sdio
.stat_work
);
436 clear_bit(MT76_READING_STATS
, &mdev
->mphy
.state
);
438 mt76_tx_status_check(&mdev
->mt76
, NULL
, true);
443 static int mt7663s_resume(struct device
*dev
)
445 struct sdio_func
*func
= dev_to_sdio_func(dev
);
446 struct mt7615_dev
*mdev
= sdio_get_drvdata(func
);
449 mt76_worker_enable(&mdev
->mt76
.sdio
.txrx_worker
);
450 mt76_worker_enable(&mdev
->mt76
.sdio
.status_worker
);
451 mt76_worker_enable(&mdev
->mt76
.sdio
.net_worker
);
453 err
= mt7615_mcu_set_drv_ctrl(mdev
);
457 if (!test_bit(MT76_STATE_SUSPEND
, &mdev
->mphy
.state
) &&
458 mt7615_firmware_offload(mdev
))
459 err
= mt7615_mcu_set_hif_suspend(mdev
, false);
464 static const struct dev_pm_ops mt7663s_pm_ops
= {
465 .suspend
= mt7663s_suspend
,
466 .resume
= mt7663s_resume
,
470 MODULE_DEVICE_TABLE(sdio
, mt7663s_table
);
471 MODULE_FIRMWARE(MT7663_OFFLOAD_FIRMWARE_N9
);
472 MODULE_FIRMWARE(MT7663_OFFLOAD_ROM_PATCH
);
473 MODULE_FIRMWARE(MT7663_FIRMWARE_N9
);
474 MODULE_FIRMWARE(MT7663_ROM_PATCH
);
476 static struct sdio_driver mt7663s_driver
= {
477 .name
= KBUILD_MODNAME
,
478 .probe
= mt7663s_probe
,
479 .remove
= mt7663s_remove
,
480 .id_table
= mt7663s_table
,
483 .pm
= &mt7663s_pm_ops
,
487 module_sdio_driver(mt7663s_driver
);
489 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
490 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
491 MODULE_LICENSE("Dual BSD/GPL");