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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / mediatek / mt76 / mt7915 / mac.c
blobf504eeb221f95f38263012898dba10ffd5718556
1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/timekeeping.h>
6 #include "mt7915.h"
7 #include "../dma.h"
8 #include "mac.h"
9
10 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
11
12 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f)
13 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
14 IEEE80211_RADIOTAP_HE_##f)
15
16 static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
18 .radar_pattern = {
19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
27 },
28 };
29
30 static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
32 .radar_pattern = {
33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
38 },
39 };
40
41 static const struct mt7915_dfs_radar_spec jp_radar_specs = {
42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
43 .radar_pattern = {
44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
52 },
53 };
54
55 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
56 u16 idx, bool unicast)
57 {
58 struct mt7915_sta *sta;
59 struct mt76_wcid *wcid;
60
61 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
62 return NULL;
63
64 wcid = rcu_dereference(dev->mt76.wcid[idx]);
65 if (unicast || !wcid)
66 return wcid;
67
68 if (!wcid->sta)
69 return NULL;
70
71 sta = container_of(wcid, struct mt7915_sta, wcid);
72 if (!sta->vif)
73 return NULL;
74
75 return &sta->vif->sta.wcid;
76 }
77
78 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
79 {
80 }
81
82 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
83 {
84 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
85 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
86
87 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
88 0, 5000);
89 }
90
91 static u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid)
92 {
93 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
94 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
95
96 return MT_WTBL_LMAC_OFFS(wcid, 0);
97 }
98
99 /* TODO: use txfree airtime info to avoid runtime accessing in the long run */
100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
101 {
102 static const u8 ac_to_tid[] = {
103 [IEEE80211_AC_BE] = 0,
104 [IEEE80211_AC_BK] = 1,
105 [IEEE80211_AC_VI] = 4,
106 [IEEE80211_AC_VO] = 6
107 };
108 struct ieee80211_sta *sta;
109 struct mt7915_sta *msta;
110 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
111 LIST_HEAD(sta_poll_list);
112 int i;
113
114 spin_lock_bh(&dev->sta_poll_lock);
115 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
116 spin_unlock_bh(&dev->sta_poll_lock);
117
118 rcu_read_lock();
119
120 while (true) {
121 bool clear = false;
122 u32 addr;
123 u16 idx;
124
125 spin_lock_bh(&dev->sta_poll_lock);
126 if (list_empty(&sta_poll_list)) {
127 spin_unlock_bh(&dev->sta_poll_lock);
128 break;
129 }
130 msta = list_first_entry(&sta_poll_list,
131 struct mt7915_sta, poll_list);
132 list_del_init(&msta->poll_list);
133 spin_unlock_bh(&dev->sta_poll_lock);
134
135 idx = msta->wcid.idx;
136 addr = mt7915_mac_wtbl_lmac_addr(dev, idx) + 20 * 4;
137
138 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
139 u32 tx_last = msta->airtime_ac[i];
140 u32 rx_last = msta->airtime_ac[i + 4];
141
142 msta->airtime_ac[i] = mt76_rr(dev, addr);
143 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
144
145 tx_time[i] = msta->airtime_ac[i] - tx_last;
146 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
147
148 if ((tx_last | rx_last) & BIT(30))
149 clear = true;
150
151 addr += 8;
152 }
153
154 if (clear) {
155 mt7915_mac_wtbl_update(dev, idx,
156 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
157 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
158 }
159
160 if (!msta->wcid.sta)
161 continue;
162
163 sta = container_of((void *)msta, struct ieee80211_sta,
164 drv_priv);
165 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
166 u8 q = mt7915_lmac_mapping(dev, i);
167 u32 tx_cur = tx_time[q];
168 u32 rx_cur = rx_time[q];
169 u8 tid = ac_to_tid[i];
170
171 if (!tx_cur && !rx_cur)
172 continue;
173
174 ieee80211_sta_register_airtime(sta, tid, tx_cur,
175 rx_cur);
176 }
177 }
178
179 rcu_read_unlock();
180 }
181
182 static void
183 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status,
184 struct ieee80211_radiotap_he *he,
185 __le32 *rxv)
186 {
187 u32 ru_h, ru_l;
188 u8 ru, offs = 0;
189
190 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0]));
191 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1]));
192 ru = (u8)(ru_l | ru_h << 4);
193
194 status->bw = RATE_INFO_BW_HE_RU;
195
196 switch (ru) {
197 case 0 ... 36:
198 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26;
199 offs = ru;
200 break;
201 case 37 ... 52:
202 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52;
203 offs = ru - 37;
204 break;
205 case 53 ... 60:
206 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106;
207 offs = ru - 53;
208 break;
209 case 61 ... 64:
210 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242;
211 offs = ru - 61;
212 break;
213 case 65 ... 66:
214 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484;
215 offs = ru - 65;
216 break;
217 case 67:
218 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996;
219 break;
220 case 68:
221 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
222 break;
223 }
224
225 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
226 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) |
227 le16_encode_bits(offs,
228 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET);
229 }
230
231 static void
232 mt7915_mac_decode_he_radiotap(struct sk_buff *skb,
233 struct mt76_rx_status *status,
234 __le32 *rxv, u32 phy)
235 {
236 /* TODO: struct ieee80211_radiotap_he_mu */
237 static const struct ieee80211_radiotap_he known = {
238 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) |
239 HE_BITS(DATA1_DATA_DCM_KNOWN) |
240 HE_BITS(DATA1_STBC_KNOWN) |
241 HE_BITS(DATA1_CODING_KNOWN) |
242 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) |
243 HE_BITS(DATA1_DOPPLER_KNOWN) |
244 HE_BITS(DATA1_BSS_COLOR_KNOWN),
245 .data2 = HE_BITS(DATA2_GI_KNOWN) |
246 HE_BITS(DATA2_TXBF_KNOWN) |
247 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) |
248 HE_BITS(DATA2_TXOP_KNOWN),
249 };
250 struct ieee80211_radiotap_he *he = NULL;
251 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1;
252
253 he = skb_push(skb, sizeof(known));
254 memcpy(he, &known, sizeof(known));
255
256 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) |
257 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]);
258 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) |
259 le16_encode_bits(ltf_size,
260 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE);
261 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) |
262 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]);
263
264 switch (phy) {
265 case MT_PHY_TYPE_HE_SU:
266 he->data1 |= HE_BITS(DATA1_FORMAT_SU) |
267 HE_BITS(DATA1_UL_DL_KNOWN) |
268 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) |
269 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
270
271 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) |
272 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
273 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
274 break;
275 case MT_PHY_TYPE_HE_EXT_SU:
276 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) |
277 HE_BITS(DATA1_UL_DL_KNOWN);
278
279 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
280 break;
281 case MT_PHY_TYPE_HE_MU:
282 he->data1 |= HE_BITS(DATA1_FORMAT_MU) |
283 HE_BITS(DATA1_UL_DL_KNOWN) |
284 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
285
286 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
287 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
288
289 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
290 break;
291 case MT_PHY_TYPE_HE_TB:
292 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) |
293 HE_BITS(DATA1_SPTL_REUSE_KNOWN) |
294 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) |
295 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) |
296 HE_BITS(DATA1_SPTL_REUSE4_KNOWN);
297
298 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) |
299 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) |
300 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) |
301 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]);
302
303 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
304 break;
305 default:
306 break;
307 }
308 }
309
310 int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
311 {
312 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
313 struct mt76_phy *mphy = &dev->mt76.phy;
314 struct mt7915_phy *phy = &dev->phy;
315 struct ieee80211_supported_band *sband;
316 struct ieee80211_hdr *hdr;
317 __le32 *rxd = (__le32 *)skb->data;
318 __le32 *rxv = NULL;
319 u32 mode = 0;
320 u32 rxd1 = le32_to_cpu(rxd[1]);
321 u32 rxd2 = le32_to_cpu(rxd[2]);
322 u32 rxd3 = le32_to_cpu(rxd[3]);
323 bool unicast, insert_ccmp_hdr = false;
324 u8 remove_pad;
325 int i, idx;
326
327 memset(status, 0, sizeof(*status));
328
329 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) {
330 mphy = dev->mt76.phy2;
331 if (!mphy)
332 return -EINVAL;
333
334 phy = mphy->priv;
335 status->ext_phy = true;
336 }
337
338 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
339 return -EINVAL;
340
341 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
342 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
343 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
344
345 if (status->wcid) {
346 struct mt7915_sta *msta;
347
348 msta = container_of(status->wcid, struct mt7915_sta, wcid);
349 spin_lock_bh(&dev->sta_poll_lock);
350 if (list_empty(&msta->poll_list))
351 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
352 spin_unlock_bh(&dev->sta_poll_lock);
353 }
354
355 status->freq = mphy->chandef.chan->center_freq;
356 status->band = mphy->chandef.chan->band;
357 if (status->band == NL80211_BAND_5GHZ)
358 sband = &mphy->sband_5g.sband;
359 else
360 sband = &mphy->sband_2g.sband;
361
362 if (!sband->channels)
363 return -EINVAL;
364
365 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
366 status->flag |= RX_FLAG_FAILED_FCS_CRC;
367
368 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
369 status->flag |= RX_FLAG_MMIC_ERROR;
370
371 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
372 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
373 status->flag |= RX_FLAG_DECRYPTED;
374 status->flag |= RX_FLAG_IV_STRIPPED;
375 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
376 }
377
378 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
379 status->flag |= RX_FLAG_AMPDU_DETAILS;
380
381 /* all subframes of an A-MPDU have the same timestamp */
382 if (phy->rx_ampdu_ts != rxd[14]) {
383 if (!++phy->ampdu_ref)
384 phy->ampdu_ref++;
385 }
386 phy->rx_ampdu_ts = rxd[14];
387
388 status->ampdu_ref = phy->ampdu_ref;
389 }
390
391 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
392
393 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
394 return -EINVAL;
395
396 rxd += 6;
397 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
398 rxd += 4;
399 if ((u8 *)rxd - skb->data >= skb->len)
400 return -EINVAL;
401 }
402
403 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
404 u8 *data = (u8 *)rxd;
405
406 if (status->flag & RX_FLAG_DECRYPTED) {
407 status->iv[0] = data[5];
408 status->iv[1] = data[4];
409 status->iv[2] = data[3];
410 status->iv[3] = data[2];
411 status->iv[4] = data[1];
412 status->iv[5] = data[0];
413
414 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
415 }
416 rxd += 4;
417 if ((u8 *)rxd - skb->data >= skb->len)
418 return -EINVAL;
419 }
420
421 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
422 rxd += 2;
423 if ((u8 *)rxd - skb->data >= skb->len)
424 return -EINVAL;
425 }
426
427 /* RXD Group 3 - P-RXV */
428 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
429 u32 v0, v1, v2;
430
431 rxv = rxd;
432 rxd += 2;
433 if ((u8 *)rxd - skb->data >= skb->len)
434 return -EINVAL;
435
436 v0 = le32_to_cpu(rxv[0]);
437 v1 = le32_to_cpu(rxv[1]);
438 v2 = le32_to_cpu(rxv[2]);
439
440 if (v0 & MT_PRXV_HT_AD_CODE)
441 status->enc_flags |= RX_ENC_FLAG_LDPC;
442
443 status->chains = mphy->antenna_mask;
444 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
445 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
446 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
447 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
448 status->signal = status->chain_signal[0];
449
450 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
451 if (!(status->chains & BIT(i)))
452 continue;
453
454 status->signal = max(status->signal,
455 status->chain_signal[i]);
456 }
457
458 /* RXD Group 5 - C-RXV */
459 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
460 u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
461 u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
462 bool cck = false;
463
464 rxd += 18;
465 if ((u8 *)rxd - skb->data >= skb->len)
466 return -EINVAL;
467
468 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
469 mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
470
471 switch (mode) {
472 case MT_PHY_TYPE_CCK:
473 cck = true;
474 fallthrough;
475 case MT_PHY_TYPE_OFDM:
476 i = mt76_get_rate(&dev->mt76, sband, i, cck);
477 break;
478 case MT_PHY_TYPE_HT_GF:
479 case MT_PHY_TYPE_HT:
480 status->encoding = RX_ENC_HT;
481 if (i > 31)
482 return -EINVAL;
483 break;
484 case MT_PHY_TYPE_VHT:
485 status->nss =
486 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
487 status->encoding = RX_ENC_VHT;
488 if (i > 9)
489 return -EINVAL;
490 break;
491 case MT_PHY_TYPE_HE_MU:
492 status->flag |= RX_FLAG_RADIOTAP_HE_MU;
493 fallthrough;
494 case MT_PHY_TYPE_HE_SU:
495 case MT_PHY_TYPE_HE_EXT_SU:
496 case MT_PHY_TYPE_HE_TB:
497 status->nss =
498 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
499 status->encoding = RX_ENC_HE;
500 status->flag |= RX_FLAG_RADIOTAP_HE;
501 i &= GENMASK(3, 0);
502
503 if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
504 status->he_gi = gi;
505
506 status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
507 break;
508 default:
509 return -EINVAL;
510 }
511 status->rate_idx = i;
512
513 switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
514 case IEEE80211_STA_RX_BW_20:
515 break;
516 case IEEE80211_STA_RX_BW_40:
517 if (mode & MT_PHY_TYPE_HE_EXT_SU &&
518 (idx & MT_PRXV_TX_ER_SU_106T)) {
519 status->bw = RATE_INFO_BW_HE_RU;
520 status->he_ru =
521 NL80211_RATE_INFO_HE_RU_ALLOC_106;
522 } else {
523 status->bw = RATE_INFO_BW_40;
524 }
525 break;
526 case IEEE80211_STA_RX_BW_80:
527 status->bw = RATE_INFO_BW_80;
528 break;
529 case IEEE80211_STA_RX_BW_160:
530 status->bw = RATE_INFO_BW_160;
531 break;
532 default:
533 return -EINVAL;
534 }
535
536 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
537 if (mode < MT_PHY_TYPE_HE_SU && gi)
538 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
539 }
540 }
541
542 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
543
544 if (insert_ccmp_hdr) {
545 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
546
547 mt76_insert_ccmp_hdr(skb, key_id);
548 }
549
550 if (rxv && status->flag & RX_FLAG_RADIOTAP_HE)
551 mt7915_mac_decode_he_radiotap(skb, status, rxv, mode);
552
553 hdr = mt76_skb_get_hdr(skb);
554 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
555 return 0;
556
557 status->aggr = unicast &&
558 !ieee80211_is_qos_nullfunc(hdr->frame_control);
559 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
560 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
561
562 return 0;
563 }
564
565 #ifdef CONFIG_NL80211_TESTMODE
566 void mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb)
567 {
568 __le32 *rxd = (__le32 *)skb->data;
569 __le32 *rxv = rxd + 4;
570 u32 rcpi, ib_rssi, wb_rssi, v20, v21;
571 s32 foe;
572 u8 snr;
573 int i;
574
575 rcpi = le32_to_cpu(rxv[6]);
576 ib_rssi = le32_to_cpu(rxv[7]);
577 wb_rssi = le32_to_cpu(rxv[8]) >> 5;
578
579 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) {
580 if (i == 3)
581 wb_rssi = le32_to_cpu(rxv[9]);
582
583 dev->test.last_rcpi[i] = rcpi & 0xff;
584 dev->test.last_ib_rssi[i] = ib_rssi & 0xff;
585 dev->test.last_wb_rssi[i] = wb_rssi & 0xff;
586 }
587
588 v20 = le32_to_cpu(rxv[20]);
589 v21 = le32_to_cpu(rxv[21]);
590
591 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) |
592 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT);
593
594 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16;
595
596 dev->test.last_freq_offset = foe;
597 dev->test.last_snr = snr;
598
599 dev_kfree_skb(skb);
600 }
601 #endif
602
603 static void
604 mt7915_mac_write_txwi_tm(struct mt7915_dev *dev, struct mt76_phy *mphy,
605 __le32 *txwi, struct sk_buff *skb)
606 {
607 #ifdef CONFIG_NL80211_TESTMODE
608 struct mt76_testmode_data *td = &dev->mt76.test;
609 u8 rate_idx = td->tx_rate_idx;
610 u8 nss = td->tx_rate_nss;
611 u8 bw, mode;
612 u16 rateval = 0;
613 u32 val;
614
615 if (skb != dev->mt76.test.tx_skb)
616 return;
617
618 switch (td->tx_rate_mode) {
619 case MT76_TM_TX_MODE_CCK:
620 mode = MT_PHY_TYPE_CCK;
621 break;
622 case MT76_TM_TX_MODE_HT:
623 nss = 1 + (rate_idx >> 3);
624 mode = MT_PHY_TYPE_HT;
625 break;
626 case MT76_TM_TX_MODE_VHT:
627 mode = MT_PHY_TYPE_VHT;
628 break;
629 case MT76_TM_TX_MODE_HE_SU:
630 mode = MT_PHY_TYPE_HE_SU;
631 break;
632 case MT76_TM_TX_MODE_HE_EXT_SU:
633 mode = MT_PHY_TYPE_HE_EXT_SU;
634 break;
635 case MT76_TM_TX_MODE_HE_TB:
636 mode = MT_PHY_TYPE_HE_TB;
637 break;
638 case MT76_TM_TX_MODE_HE_MU:
639 mode = MT_PHY_TYPE_HE_MU;
640 break;
641 case MT76_TM_TX_MODE_OFDM:
642 default:
643 mode = MT_PHY_TYPE_OFDM;
644 break;
645 }
646
647 switch (mphy->chandef.width) {
648 case NL80211_CHAN_WIDTH_40:
649 bw = 1;
650 break;
651 case NL80211_CHAN_WIDTH_80:
652 bw = 2;
653 break;
654 case NL80211_CHAN_WIDTH_80P80:
655 case NL80211_CHAN_WIDTH_160:
656 bw = 3;
657 break;
658 default:
659 bw = 0;
660 break;
661 }
662
663 if (td->tx_rate_stbc && nss == 1) {
664 nss++;
665 rateval |= MT_TX_RATE_STBC;
666 }
667
668 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
669 FIELD_PREP(MT_TX_RATE_MODE, mode) |
670 FIELD_PREP(MT_TX_RATE_NSS, nss - 1);
671
672 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
673
674 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT);
675 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT)
676 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
677
678 val = MT_TXD6_FIXED_BW |
679 FIELD_PREP(MT_TXD6_BW, bw) |
680 FIELD_PREP(MT_TXD6_TX_RATE, rateval) |
681 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi);
682
683 /* for HE_SU/HE_EXT_SU PPDU
684 * - 1x, 2x, 4x LTF + 0.8us GI
685 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
686 * for HE_MU PPDU
687 * - 2x, 4x LTF + 0.8us GI
688 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
689 * for HE_TB PPDU
690 * - 1x, 2x LTF + 1.6us GI
691 * - 4x LTF + 3.2us GI
692 */
693 if (mode >= MT_PHY_TYPE_HE_SU)
694 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
695
696 if (td->tx_rate_ldpc)
697 val |= MT_TXD6_LDPC;
698
699 txwi[6] |= cpu_to_le32(val);
700 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
701 dev->test.spe_idx));
702 #endif
703 }
704
705 static void
706 mt7915_mac_write_txwi_8023(struct mt7915_dev *dev, __le32 *txwi,
707 struct sk_buff *skb, struct mt76_wcid *wcid)
708 {
709
710 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
711 u8 fc_type, fc_stype;
712 bool wmm = false;
713 u32 val;
714
715 if (wcid->sta) {
716 struct ieee80211_sta *sta;
717
718 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv);
719 wmm = sta->wme;
720 }
721
722 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) |
723 FIELD_PREP(MT_TXD1_TID, tid);
724
725 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN)
726 val |= MT_TXD1_ETH_802_3;
727
728 txwi[1] |= cpu_to_le32(val);
729
730 fc_type = IEEE80211_FTYPE_DATA >> 2;
731 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0;
732
733 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
734 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype);
735
736 txwi[2] |= cpu_to_le32(val);
737
738 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
739 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
740 txwi[7] |= cpu_to_le32(val);
741 }
742
743 static void
744 mt7915_mac_write_txwi_80211(struct mt7915_dev *dev, __le32 *txwi,
745 struct sk_buff *skb, struct ieee80211_key_conf *key)
746 {
747 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
748 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
749 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
750 bool multicast = is_multicast_ether_addr(hdr->addr1);
751 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
752 __le16 fc = hdr->frame_control;
753 u8 fc_type, fc_stype;
754 u32 val;
755
756 if (ieee80211_is_action(fc) &&
757 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
758 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) {
759 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
760
761 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA);
762 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK;
763 } else if (ieee80211_is_back_req(hdr->frame_control)) {
764 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr;
765 u16 control = le16_to_cpu(bar->control);
766
767 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control);
768 }
769
770 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
771 FIELD_PREP(MT_TXD1_HDR_INFO,
772 ieee80211_get_hdrlen_from_skb(skb) / 2) |
773 FIELD_PREP(MT_TXD1_TID, tid);
774 txwi[1] |= cpu_to_le32(val);
775
776 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
777 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
778
779 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
780 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
781 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
782
783 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) &&
784 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
785 val |= MT_TXD2_BIP;
786 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME);
787 }
788
789 if (!ieee80211_is_data(fc) || multicast)
790 val |= MT_TXD2_FIX_RATE;
791
792 txwi[2] |= cpu_to_le32(val);
793
794 if (ieee80211_is_beacon(fc)) {
795 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT);
796 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT);
797 }
798
799 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
800 u16 seqno = le16_to_cpu(hdr->seq_ctrl);
801
802 if (ieee80211_is_back_req(hdr->frame_control)) {
803 struct ieee80211_bar *bar;
804
805 bar = (struct ieee80211_bar *)skb->data;
806 seqno = le16_to_cpu(bar->start_seq_num);
807 }
808
809 val = MT_TXD3_SN_VALID |
810 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
811 txwi[3] |= cpu_to_le32(val);
812 }
813
814 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
815 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
816 txwi[7] |= cpu_to_le32(val);
817 }
818
819 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
820 struct sk_buff *skb, struct mt76_wcid *wcid,
821 struct ieee80211_key_conf *key, bool beacon)
822 {
823 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
824 struct ieee80211_vif *vif = info->control.vif;
825 struct mt76_phy *mphy = &dev->mphy;
826 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
827 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
828 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
829 u16 tx_count = 15;
830 u32 val;
831
832 if (vif) {
833 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
834
835 omac_idx = mvif->omac_idx;
836 wmm_idx = mvif->wmm_idx;
837 }
838
839 if (ext_phy && dev->mt76.phy2)
840 mphy = dev->mt76.phy2;
841
842 if (beacon) {
843 p_fmt = MT_TX_TYPE_FW;
844 q_idx = MT_LMAC_BCN0;
845 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
846 p_fmt = MT_TX_TYPE_CT;
847 q_idx = MT_LMAC_ALTX0;
848 } else {
849 p_fmt = MT_TX_TYPE_CT;
850 q_idx = wmm_idx * MT7915_MAX_WMM_SETS +
851 mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb));
852 }
853
854 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
855 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) |
856 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
857 txwi[0] = cpu_to_le32(val);
858
859 val = MT_TXD1_LONG_FORMAT |
860 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
861 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
862
863 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0)
864 val |= MT_TXD1_TGID;
865
866 txwi[1] = cpu_to_le32(val);
867
868 txwi[2] = 0;
869
870 val = MT_TXD3_SW_POWER_MGMT |
871 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
872 if (key)
873 val |= MT_TXD3_PROTECT_FRAME;
874 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
875 val |= MT_TXD3_NO_ACK;
876
877 txwi[3] = cpu_to_le32(val);
878 txwi[4] = 0;
879 txwi[5] = 0;
880 txwi[6] = 0;
881 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0;
882
883 if (is_8023)
884 mt7915_mac_write_txwi_8023(dev, txwi, skb, wcid);
885 else
886 mt7915_mac_write_txwi_80211(dev, txwi, skb, key);
887
888 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) {
889 u16 rate;
890
891 /* hardware won't add HTC for mgmt/ctrl frame */
892 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD);
893
894 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
895 rate = MT7915_5G_RATE_DEFAULT;
896 else
897 rate = MT7915_2G_RATE_DEFAULT;
898
899 val = MT_TXD6_FIXED_BW |
900 FIELD_PREP(MT_TXD6_TX_RATE, rate);
901 txwi[6] |= cpu_to_le32(val);
902 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
903 }
904
905 if (mt76_testmode_enabled(&dev->mt76))
906 mt7915_mac_write_txwi_tm(dev, mphy, txwi, skb);
907 }
908
909 static void
910 mt7915_set_tx_blocked(struct mt7915_dev *dev, bool blocked)
911 {
912 struct mt76_phy *mphy = &dev->mphy, *mphy2 = dev->mt76.phy2;
913 struct mt76_queue *q, *q2 = NULL;
914
915 q = mphy->q_tx[0];
916 if (blocked == q->blocked)
917 return;
918
919 q->blocked = blocked;
920 if (mphy2) {
921 q2 = mphy2->q_tx[0];
922 q2->blocked = blocked;
923 }
924
925 if (!blocked)
926 mt76_worker_schedule(&dev->mt76.tx_worker);
927 }
928
929 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
930 enum mt76_txq_id qid, struct mt76_wcid *wcid,
931 struct ieee80211_sta *sta,
932 struct mt76_tx_info *tx_info)
933 {
934 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
935 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
936 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
937 struct ieee80211_key_conf *key = info->control.hw_key;
938 struct ieee80211_vif *vif = info->control.vif;
939 struct mt76_tx_cb *cb = mt76_tx_skb_cb(tx_info->skb);
940 struct mt76_txwi_cache *t;
941 struct mt7915_txp *txp;
942 int id, i, nbuf = tx_info->nbuf - 1;
943 u8 *txwi = (u8 *)txwi_ptr;
944
945 if (!wcid)
946 wcid = &dev->mt76.global_wcid;
947
948 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key,
949 false);
950
951 cb->wcid = wcid->idx;
952
953 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
954 for (i = 0; i < nbuf; i++) {
955 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
956 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
957 }
958 txp->nbuf = nbuf;
959
960 /* pass partial skb header to fw */
961 tx_info->buf[1].len = MT_CT_PARSE_LEN;
962 tx_info->buf[1].skip_unmap = true;
963 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
964
965 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST);
966
967 if (!key)
968 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
969
970 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
971 ieee80211_is_mgmt(hdr->frame_control))
972 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
973
974 if (vif) {
975 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
976
977 txp->bss_idx = mvif->idx;
978 }
979
980 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
981 t->skb = tx_info->skb;
982
983 spin_lock_bh(&dev->token_lock);
984 id = idr_alloc(&dev->token, t, 0, MT7915_TOKEN_SIZE, GFP_ATOMIC);
985 if (id >= 0)
986 dev->token_count++;
987
988 if (dev->token_count >= MT7915_TOKEN_SIZE - MT7915_TOKEN_FREE_THR)
989 mt7915_set_tx_blocked(dev, true);
990 spin_unlock_bh(&dev->token_lock);
991
992 if (id < 0)
993 return id;
994
995 txp->token = cpu_to_le16(id);
996 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags))
997 txp->rept_wds_wcid = cpu_to_le16(wcid->idx);
998 else
999 txp->rept_wds_wcid = cpu_to_le16(0x3ff);
1000 tx_info->skb = DMA_DUMMY_DATA;
1001
1002 return 0;
1003 }
1004
1005 static void
1006 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
1007 {
1008 struct mt7915_sta *msta;
1009 u16 fc, tid;
1010 u32 val;
1011
1012 if (!sta || !sta->ht_cap.ht_supported)
1013 return;
1014
1015 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1]));
1016 if (tid >= 6) /* skip VO queue */
1017 return;
1018
1019 val = le32_to_cpu(txwi[2]);
1020 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 |
1021 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4;
1022 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)))
1023 return;
1024
1025 msta = (struct mt7915_sta *)sta->drv_priv;
1026 if (!test_and_set_bit(tid, &msta->ampdu_state))
1027 ieee80211_start_tx_ba_session(sta, tid, 0);
1028 }
1029
1030 static void
1031 mt7915_tx_complete_status(struct mt76_dev *mdev, struct sk_buff *skb,
1032 struct ieee80211_sta *sta, u8 stat,
1033 struct list_head *free_list)
1034 {
1035 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1036 struct ieee80211_tx_status status = {
1037 .sta = sta,
1038 .info = info,
1039 .skb = skb,
1040 .free_list = free_list,
1041 };
1042 struct ieee80211_hw *hw;
1043
1044 if (sta) {
1045 struct mt7915_sta *msta;
1046
1047 msta = (struct mt7915_sta *)sta->drv_priv;
1048 status.rate = &msta->stats.tx_rate;
1049 }
1050
1051 hw = mt76_tx_status_get_hw(mdev, skb);
1052
1053 #ifdef CONFIG_NL80211_TESTMODE
1054 if (skb == mdev->test.tx_skb) {
1055 struct mt7915_phy *phy = mt7915_hw_phy(hw);
1056 struct ieee80211_vif *vif = phy->monitor_vif;
1057 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1058
1059 mt76_tx_complete_skb(mdev, mvif->sta.wcid.idx, skb);
1060
1061 return;
1062 }
1063 #endif
1064
1065 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1066 info->flags |= IEEE80211_TX_STAT_AMPDU;
1067
1068 if (stat)
1069 ieee80211_tx_info_clear_status(info);
1070
1071 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
1072 info->flags |= IEEE80211_TX_STAT_ACK;
1073
1074 info->status.tx_time = 0;
1075 ieee80211_tx_status_ext(hw, &status);
1076 }
1077
1078 void mt7915_txp_skb_unmap(struct mt76_dev *dev,
1079 struct mt76_txwi_cache *t)
1080 {
1081 struct mt7915_txp *txp;
1082 int i;
1083
1084 txp = mt7915_txwi_to_txp(dev, t);
1085 for (i = 1; i < txp->nbuf; i++)
1086 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
1087 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
1088 }
1089
1090 void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
1091 {
1092 struct mt7915_tx_free *free = (struct mt7915_tx_free *)skb->data;
1093 struct mt76_dev *mdev = &dev->mt76;
1094 struct mt76_phy *mphy_ext = mdev->phy2;
1095 struct mt76_txwi_cache *txwi;
1096 struct ieee80211_sta *sta = NULL;
1097 LIST_HEAD(free_list);
1098 struct sk_buff *tmp;
1099 u8 i, count;
1100 bool wake = false;
1101
1102 /* clean DMA queues and unmap buffers first */
1103 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1104 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1105 if (mphy_ext) {
1106 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
1107 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
1108 }
1109
1110 /*
1111 * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE,
1112 * to the time ack is received or dropped by hw (air + hw queue time).
1113 * Should avoid accessing WTBL to get Tx airtime, and use it instead.
1114 */
1115 count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl));
1116 for (i = 0; i < count; i++) {
1117 u32 msdu, info = le32_to_cpu(free->info[i]);
1118 u8 stat;
1119
1120 /*
1121 * 1'b1: new wcid pair.
1122 * 1'b0: msdu_id with the same 'wcid pair' as above.
1123 */
1124 if (info & MT_TX_FREE_PAIR) {
1125 struct mt7915_sta *msta;
1126 struct mt7915_phy *phy;
1127 struct mt76_wcid *wcid;
1128 u16 idx;
1129
1130 count++;
1131 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
1132 wcid = rcu_dereference(dev->mt76.wcid[idx]);
1133 sta = wcid_to_sta(wcid);
1134 if (!sta)
1135 continue;
1136
1137 msta = container_of(wcid, struct mt7915_sta, wcid);
1138 phy = msta->vif->phy;
1139 spin_lock_bh(&dev->sta_poll_lock);
1140 if (list_empty(&msta->stats_list))
1141 list_add_tail(&msta->stats_list, &phy->stats_list);
1142 if (list_empty(&msta->poll_list))
1143 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1144 spin_unlock_bh(&dev->sta_poll_lock);
1145 continue;
1146 }
1147
1148 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
1149 stat = FIELD_GET(MT_TX_FREE_STATUS, info);
1150
1151 spin_lock_bh(&dev->token_lock);
1152 txwi = idr_remove(&dev->token, msdu);
1153 if (txwi)
1154 dev->token_count--;
1155 if (dev->token_count < MT7915_TOKEN_SIZE - MT7915_TOKEN_FREE_THR &&
1156 dev->mphy.q_tx[0]->blocked)
1157 wake = true;
1158 spin_unlock_bh(&dev->token_lock);
1159
1160 if (!txwi)
1161 continue;
1162
1163 mt7915_txp_skb_unmap(mdev, txwi);
1164 if (txwi->skb) {
1165 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(txwi->skb);
1166 void *txwi_ptr = mt76_get_txwi_ptr(mdev, txwi);
1167
1168 if (likely(txwi->skb->protocol != cpu_to_be16(ETH_P_PAE)))
1169 mt7915_tx_check_aggr(sta, txwi_ptr);
1170
1171 if (sta && !info->tx_time_est) {
1172 struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv;
1173 int pending;
1174
1175 pending = atomic_dec_return(&wcid->non_aql_packets);
1176 if (pending < 0)
1177 atomic_cmpxchg(&wcid->non_aql_packets, pending, 0);
1178 }
1179
1180 mt7915_tx_complete_status(mdev, txwi->skb, sta, stat, &free_list);
1181 txwi->skb = NULL;
1182 }
1183
1184 mt76_put_txwi(mdev, txwi);
1185 }
1186
1187 mt7915_mac_sta_poll(dev);
1188
1189 if (wake) {
1190 spin_lock_bh(&dev->token_lock);
1191 mt7915_set_tx_blocked(dev, false);
1192 spin_unlock_bh(&dev->token_lock);
1193 }
1194
1195 mt76_worker_schedule(&dev->mt76.tx_worker);
1196
1197 napi_consume_skb(skb, 1);
1198
1199 list_for_each_entry_safe(skb, tmp, &free_list, list) {
1200 skb_list_del_init(skb);
1201 napi_consume_skb(skb, 1);
1202 }
1203 }
1204
1205 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1206 {
1207 struct mt7915_dev *dev;
1208
1209 if (!e->txwi) {
1210 dev_kfree_skb_any(e->skb);
1211 return;
1212 }
1213
1214 dev = container_of(mdev, struct mt7915_dev, mt76);
1215
1216 /* error path */
1217 if (e->skb == DMA_DUMMY_DATA) {
1218 struct mt76_txwi_cache *t;
1219 struct mt7915_txp *txp;
1220
1221 txp = mt7915_txwi_to_txp(mdev, e->txwi);
1222
1223 spin_lock_bh(&dev->token_lock);
1224 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
1225 spin_unlock_bh(&dev->token_lock);
1226 e->skb = t ? t->skb : NULL;
1227 }
1228
1229 if (e->skb) {
1230 struct mt76_tx_cb *cb = mt76_tx_skb_cb(e->skb);
1231 struct mt76_wcid *wcid;
1232
1233 wcid = rcu_dereference(dev->mt76.wcid[cb->wcid]);
1234
1235 mt7915_tx_complete_status(mdev, e->skb, wcid_to_sta(wcid), 0,
1236 NULL);
1237 }
1238 }
1239
1240 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
1241 {
1242 struct mt7915_dev *dev = phy->dev;
1243 bool ext_phy = phy != &dev->phy;
1244 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy);
1245
1246 mt7915_l2_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
1247 mt7915_l2_set(dev, reg, BIT(11) | BIT(9));
1248 }
1249
1250 void mt7915_mac_reset_counters(struct mt7915_phy *phy)
1251 {
1252 struct mt7915_dev *dev = phy->dev;
1253 bool ext_phy = phy != &dev->phy;
1254 int i;
1255
1256 for (i = 0; i < 4; i++) {
1257 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1258 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
1259 }
1260
1261 if (ext_phy) {
1262 dev->mt76.phy2->survey_time = ktime_get_boottime();
1263 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2;
1264 } else {
1265 dev->mt76.phy.survey_time = ktime_get_boottime();
1266 i = 0;
1267 }
1268 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2);
1269
1270 /* reset airtime counters */
1271 mt76_rr(dev, MT_MIB_SDR9(ext_phy));
1272 mt76_rr(dev, MT_MIB_SDR36(ext_phy));
1273 mt76_rr(dev, MT_MIB_SDR37(ext_phy));
1274
1275 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(ext_phy),
1276 MT_WF_RMAC_MIB_RXTIME_CLR);
1277 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy),
1278 MT_WF_RMAC_MIB_RXTIME_CLR);
1279 }
1280
1281 void mt7915_mac_set_timing(struct mt7915_phy *phy)
1282 {
1283 s16 coverage_class = phy->coverage_class;
1284 struct mt7915_dev *dev = phy->dev;
1285 bool ext_phy = phy != &dev->phy;
1286 u32 val, reg_offset;
1287 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1288 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1289 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1290 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1291 int sifs, offset;
1292 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
1293
1294 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1295 return;
1296
1297 if (is_5ghz)
1298 sifs = 16;
1299 else
1300 sifs = 10;
1301
1302 if (ext_phy) {
1303 coverage_class = max_t(s16, dev->phy.coverage_class,
1304 coverage_class);
1305 } else {
1306 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev);
1307
1308 if (phy_ext)
1309 coverage_class = max_t(s16, phy_ext->coverage_class,
1310 coverage_class);
1311 }
1312 mt76_set(dev, MT_ARB_SCR(ext_phy),
1313 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1314 udelay(1);
1315
1316 offset = 3 * coverage_class;
1317 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1318 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1319
1320 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset);
1321 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset);
1322 mt76_wr(dev, MT_TMAC_ICR0(ext_phy),
1323 FIELD_PREP(MT_IFS_EIFS, 360) |
1324 FIELD_PREP(MT_IFS_RIFS, 2) |
1325 FIELD_PREP(MT_IFS_SIFS, sifs) |
1326 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1327
1328 if (phy->slottime < 20 || is_5ghz)
1329 val = MT7915_CFEND_RATE_DEFAULT;
1330 else
1331 val = MT7915_CFEND_RATE_11B;
1332
1333 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
1334 mt76_clear(dev, MT_ARB_SCR(ext_phy),
1335 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1336 }
1337
1338 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy)
1339 {
1340 mt7915_l2_set(dev, MT_WF_PHY_RXTD12(ext_phy),
1341 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY |
1342 MT_WF_PHY_RXTD12_IRPI_SW_CLR);
1343
1344 mt7915_l2_set(dev, MT_WF_PHY_RX_CTRL1(ext_phy),
1345 FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));
1346 }
1347
1348 static u8
1349 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx)
1350 {
1351 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1352 struct mt7915_dev *dev = phy->dev;
1353 u32 val, sum = 0, n = 0;
1354 int nss, i;
1355
1356 for (nss = 0; nss < hweight8(phy->chainmask); nss++) {
1357 u32 reg = MT_WF_IRPI(nss + (idx << dev->dbdc_support));
1358
1359 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1360 val = mt7915_l2_rr(dev, reg);
1361 sum += val * nf_power[i];
1362 n += val;
1363 }
1364 }
1365
1366 if (!n)
1367 return 0;
1368
1369 return sum / n;
1370 }
1371
1372 static void
1373 mt7915_phy_update_channel(struct mt76_phy *mphy, int idx)
1374 {
1375 struct mt7915_dev *dev = container_of(mphy->dev, struct mt7915_dev, mt76);
1376 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv;
1377 struct mt76_channel_state *state;
1378 u64 busy_time, tx_time, rx_time, obss_time;
1379 int nf;
1380
1381 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1382 MT_MIB_SDR9_BUSY_MASK);
1383 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1384 MT_MIB_SDR36_TXTIME_MASK);
1385 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1386 MT_MIB_SDR37_RXTIME_MASK);
1387 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx),
1388 MT_MIB_OBSSTIME_MASK);
1389
1390 nf = mt7915_phy_get_nf(phy, idx);
1391 if (!phy->noise)
1392 phy->noise = nf << 4;
1393 else if (nf)
1394 phy->noise += nf - (phy->noise >> 4);
1395
1396 state = mphy->chan_state;
1397 state->cc_busy += busy_time;
1398 state->cc_tx += tx_time;
1399 state->cc_rx += rx_time + obss_time;
1400 state->cc_bss_rx += rx_time;
1401 state->noise = -(phy->noise >> 4);
1402 }
1403
1404 void mt7915_update_channel(struct mt76_dev *mdev)
1405 {
1406 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1407
1408 mt7915_phy_update_channel(&mdev->phy, 0);
1409 if (mdev->phy2)
1410 mt7915_phy_update_channel(mdev->phy2, 1);
1411
1412 /* reset obss airtime */
1413 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
1414 if (mdev->phy2)
1415 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(1),
1416 MT_WF_RMAC_MIB_RXTIME_CLR);
1417 }
1418
1419 static bool
1420 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1421 {
1422 bool ret;
1423
1424 ret = wait_event_timeout(dev->reset_wait,
1425 (READ_ONCE(dev->reset_state) & state),
1426 MT7915_RESET_TIMEOUT);
1427
1428 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1429 return ret;
1430 }
1431
1432 static void
1433 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1434 {
1435 struct ieee80211_hw *hw = priv;
1436
1437 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon);
1438 }
1439
1440 static void
1441 mt7915_update_beacons(struct mt7915_dev *dev)
1442 {
1443 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1444 IEEE80211_IFACE_ITER_RESUME_ALL,
1445 mt7915_update_vif_beacon, dev->mt76.hw);
1446
1447 if (!dev->mt76.phy2)
1448 return;
1449
1450 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1451 IEEE80211_IFACE_ITER_RESUME_ALL,
1452 mt7915_update_vif_beacon, dev->mt76.phy2->hw);
1453 }
1454
1455 static void
1456 mt7915_dma_reset(struct mt7915_phy *phy)
1457 {
1458 struct mt7915_dev *dev = phy->dev;
1459 struct mt76_phy *mphy_ext = dev->mt76.phy2;
1460 int i;
1461
1462 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
1463 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1464 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
1465 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1466 usleep_range(1000, 2000);
1467
1468 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], true);
1469 for (i = 0; i < __MT_TXQ_MAX; i++) {
1470 mt76_queue_tx_cleanup(dev, phy->mt76->q_tx[i], true);
1471 if (mphy_ext)
1472 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true);
1473 }
1474
1475 mt76_for_each_q_rx(&dev->mt76, i) {
1476 mt76_queue_rx_reset(dev, i);
1477 }
1478
1479 /* re-init prefetch settings after reset */
1480 mt7915_dma_prefetch(dev);
1481
1482 mt76_set(dev, MT_WFDMA0_GLO_CFG,
1483 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1484 mt76_set(dev, MT_WFDMA1_GLO_CFG,
1485 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1486 }
1487
1488 /* system error recovery */
1489 void mt7915_mac_reset_work(struct work_struct *work)
1490 {
1491 struct mt7915_phy *phy2;
1492 struct mt76_phy *ext_phy;
1493 struct mt7915_dev *dev;
1494
1495 dev = container_of(work, struct mt7915_dev, reset_work);
1496 ext_phy = dev->mt76.phy2;
1497 phy2 = ext_phy ? ext_phy->priv : NULL;
1498
1499 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
1500 return;
1501
1502 ieee80211_stop_queues(mt76_hw(dev));
1503 if (ext_phy)
1504 ieee80211_stop_queues(ext_phy->hw);
1505
1506 set_bit(MT76_RESET, &dev->mphy.state);
1507 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1508 wake_up(&dev->mt76.mcu.wait);
1509 cancel_delayed_work_sync(&dev->phy.mac_work);
1510 if (phy2)
1511 cancel_delayed_work_sync(&phy2->mac_work);
1512
1513 /* lock/unlock all queues to ensure that no tx is pending */
1514 mt76_txq_schedule_all(&dev->mphy);
1515 if (ext_phy)
1516 mt76_txq_schedule_all(ext_phy);
1517
1518 mt76_worker_disable(&dev->mt76.tx_worker);
1519 napi_disable(&dev->mt76.napi[0]);
1520 napi_disable(&dev->mt76.napi[1]);
1521 napi_disable(&dev->mt76.napi[2]);
1522 napi_disable(&dev->mt76.tx_napi);
1523
1524 mutex_lock(&dev->mt76.mutex);
1525
1526 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1527
1528 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1529 mt7915_dma_reset(&dev->phy);
1530
1531 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1532 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1533 }
1534
1535 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1536 clear_bit(MT76_RESET, &dev->mphy.state);
1537
1538 mt76_worker_enable(&dev->mt76.tx_worker);
1539 napi_enable(&dev->mt76.tx_napi);
1540 napi_schedule(&dev->mt76.tx_napi);
1541
1542 napi_enable(&dev->mt76.napi[0]);
1543 napi_schedule(&dev->mt76.napi[0]);
1544
1545 napi_enable(&dev->mt76.napi[1]);
1546 napi_schedule(&dev->mt76.napi[1]);
1547
1548 napi_enable(&dev->mt76.napi[2]);
1549 napi_schedule(&dev->mt76.napi[2]);
1550
1551 ieee80211_wake_queues(mt76_hw(dev));
1552 if (ext_phy)
1553 ieee80211_wake_queues(ext_phy->hw);
1554
1555 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1556 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1557
1558 mutex_unlock(&dev->mt76.mutex);
1559
1560 mt7915_update_beacons(dev);
1561
1562 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
1563 MT7915_WATCHDOG_TIME);
1564 if (phy2)
1565 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
1566 MT7915_WATCHDOG_TIME);
1567 }
1568
1569 static void
1570 mt7915_mac_update_mib_stats(struct mt7915_phy *phy)
1571 {
1572 struct mt7915_dev *dev = phy->dev;
1573 struct mib_stats *mib = &phy->mib;
1574 bool ext_phy = phy != &dev->phy;
1575 int i, aggr0, aggr1;
1576
1577 memset(mib, 0, sizeof(*mib));
1578
1579 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1580 MT_MIB_SDR3_FCS_ERR_MASK);
1581
1582 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1583 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
1584 u32 val, val2;
1585
1586 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1587
1588 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1589 if (val2 > mib->ack_fail_cnt)
1590 mib->ack_fail_cnt = val2;
1591
1592 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1593 if (val2 > mib->ba_miss_cnt)
1594 mib->ba_miss_cnt = val2;
1595
1596 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1597 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1598 if (val2 > mib->rts_retries_cnt) {
1599 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1600 mib->rts_retries_cnt = val2;
1601 }
1602
1603 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1604 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
1605
1606 dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
1607 dev->mt76.aggr_stats[aggr0++] += val >> 16;
1608 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff;
1609 dev->mt76.aggr_stats[aggr1++] += val2 >> 16;
1610 }
1611 }
1612
1613 static void
1614 mt7915_mac_sta_stats_work(struct mt7915_phy *phy)
1615 {
1616 struct mt7915_dev *dev = phy->dev;
1617 struct mt7915_sta *msta;
1618 LIST_HEAD(list);
1619
1620 spin_lock_bh(&dev->sta_poll_lock);
1621 list_splice_init(&phy->stats_list, &list);
1622
1623 while (!list_empty(&list)) {
1624 msta = list_first_entry(&list, struct mt7915_sta, stats_list);
1625 list_del_init(&msta->stats_list);
1626 spin_unlock_bh(&dev->sta_poll_lock);
1627
1628 /* use MT_TX_FREE_RATE to report Tx rate for further devices */
1629 mt7915_mcu_get_tx_rate(dev, RATE_CTRL_RU_INFO, msta->wcid.idx);
1630
1631 spin_lock_bh(&dev->sta_poll_lock);
1632 }
1633
1634 spin_unlock_bh(&dev->sta_poll_lock);
1635 }
1636
1637 void mt7915_mac_sta_rc_work(struct work_struct *work)
1638 {
1639 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work);
1640 struct ieee80211_sta *sta;
1641 struct ieee80211_vif *vif;
1642 struct mt7915_sta *msta;
1643 u32 changed;
1644 LIST_HEAD(list);
1645
1646 spin_lock_bh(&dev->sta_poll_lock);
1647 list_splice_init(&dev->sta_rc_list, &list);
1648
1649 while (!list_empty(&list)) {
1650 msta = list_first_entry(&list, struct mt7915_sta, rc_list);
1651 list_del_init(&msta->rc_list);
1652 changed = msta->stats.changed;
1653 msta->stats.changed = 0;
1654 spin_unlock_bh(&dev->sta_poll_lock);
1655
1656 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
1657 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
1658
1659 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED |
1660 IEEE80211_RC_NSS_CHANGED |
1661 IEEE80211_RC_BW_CHANGED))
1662 mt7915_mcu_add_rate_ctrl(dev, vif, sta);
1663
1664 if (changed & IEEE80211_RC_SMPS_CHANGED)
1665 mt7915_mcu_add_smps(dev, vif, sta);
1666
1667 spin_lock_bh(&dev->sta_poll_lock);
1668 }
1669
1670 spin_unlock_bh(&dev->sta_poll_lock);
1671 }
1672
1673 void mt7915_mac_work(struct work_struct *work)
1674 {
1675 struct mt7915_phy *phy;
1676 struct mt76_dev *mdev;
1677
1678 phy = (struct mt7915_phy *)container_of(work, struct mt7915_phy,
1679 mac_work.work);
1680 mdev = &phy->dev->mt76;
1681
1682 mutex_lock(&mdev->mutex);
1683
1684 mt76_update_survey(mdev);
1685 if (++phy->mac_work_count == 5) {
1686 phy->mac_work_count = 0;
1687
1688 mt7915_mac_update_mib_stats(phy);
1689 }
1690
1691 if (++phy->sta_work_count == 10) {
1692 phy->sta_work_count = 0;
1693 mt7915_mac_sta_stats_work(phy);
1694 };
1695
1696 mutex_unlock(&mdev->mutex);
1697
1698 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
1699 MT7915_WATCHDOG_TIME);
1700 }
1701
1702 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
1703 {
1704 struct mt7915_dev *dev = phy->dev;
1705
1706 if (phy->rdd_state & BIT(0))
1707 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
1708 if (phy->rdd_state & BIT(1))
1709 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
1710 }
1711
1712 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain)
1713 {
1714 int err;
1715
1716 err = mt7915_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1717 if (err < 0)
1718 return err;
1719
1720 return mt7915_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, MT_RX_SEL0, 1);
1721 }
1722
1723 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
1724 {
1725 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1726 struct mt7915_dev *dev = phy->dev;
1727 bool ext_phy = phy != &dev->phy;
1728 int err;
1729
1730 /* start CAC */
1731 err = mt7915_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
1732 if (err < 0)
1733 return err;
1734
1735 err = mt7915_dfs_start_rdd(dev, ext_phy);
1736 if (err < 0)
1737 return err;
1738
1739 phy->rdd_state |= BIT(ext_phy);
1740
1741 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1742 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1743 err = mt7915_dfs_start_rdd(dev, 1);
1744 if (err < 0)
1745 return err;
1746
1747 phy->rdd_state |= BIT(1);
1748 }
1749
1750 return 0;
1751 }
1752
1753 static int
1754 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
1755 {
1756 const struct mt7915_dfs_radar_spec *radar_specs;
1757 struct mt7915_dev *dev = phy->dev;
1758 int err, i;
1759
1760 switch (dev->mt76.region) {
1761 case NL80211_DFS_FCC:
1762 radar_specs = &fcc_radar_specs;
1763 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
1764 if (err < 0)
1765 return err;
1766 break;
1767 case NL80211_DFS_ETSI:
1768 radar_specs = &etsi_radar_specs;
1769 break;
1770 case NL80211_DFS_JP:
1771 radar_specs = &jp_radar_specs;
1772 break;
1773 default:
1774 return -EINVAL;
1775 }
1776
1777 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1778 err = mt7915_mcu_set_radar_th(dev, i,
1779 &radar_specs->radar_pattern[i]);
1780 if (err < 0)
1781 return err;
1782 }
1783
1784 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
1785 }
1786
1787 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
1788 {
1789 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1790 struct mt7915_dev *dev = phy->dev;
1791 bool ext_phy = phy != &dev->phy;
1792 int err;
1793
1794 if (dev->mt76.region == NL80211_DFS_UNSET) {
1795 phy->dfs_state = -1;
1796 if (phy->rdd_state)
1797 goto stop;
1798
1799 return 0;
1800 }
1801
1802 if (test_bit(MT76_SCANNING, &phy->mt76->state))
1803 return 0;
1804
1805 if (phy->dfs_state == chandef->chan->dfs_state)
1806 return 0;
1807
1808 err = mt7915_dfs_init_radar_specs(phy);
1809 if (err < 0) {
1810 phy->dfs_state = -1;
1811 goto stop;
1812 }
1813
1814 phy->dfs_state = chandef->chan->dfs_state;
1815
1816 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
1817 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
1818 return mt7915_dfs_start_radar_detector(phy);
1819
1820 return mt7915_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
1821 MT_RX_SEL0, 0);
1822 }
1823
1824 stop:
1825 err = mt7915_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy,
1826 MT_RX_SEL0, 0);
1827 if (err < 0)
1828 return err;
1829
1830 mt7915_dfs_stop_radar_detector(phy);
1831 return 0;
1832 }
Linux with added FPC-III support