?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / mediatek / mt76 / mt7915 / mcu.h
blobcd1a4256c8437b6bdcd17a21267acdc8931daa46
1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT7915_MCU_H
5 #define __MT7915_MCU_H
6
7 struct mt7915_mcu_txd {
8 __le32 txd[8];
9
10 __le16 len;
11 __le16 pq_id;
12
13 u8 cid;
14 u8 pkt_type;
15 u8 set_query; /* FW don't care */
16 u8 seq;
17
18 u8 uc_d2b0_rev;
19 u8 ext_cid;
20 u8 s2d_index;
21 u8 ext_cid_ack;
22
23 u32 reserved[5];
24 } __packed __aligned(4);
25
26 /* event table */
27 enum {
28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29 MCU_EVENT_FW_START = 0x01,
30 MCU_EVENT_GENERIC = 0x01,
31 MCU_EVENT_ACCESS_REG = 0x02,
32 MCU_EVENT_MT_PATCH_SEM = 0x04,
33 MCU_EVENT_CH_PRIVILEGE = 0x18,
34 MCU_EVENT_EXT = 0xed,
35 MCU_EVENT_RESTART_DL = 0xef,
36 };
37
38 /* ext event table */
39 enum {
40 MCU_EXT_EVENT_PS_SYNC = 0x5,
41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46 MCU_EXT_EVENT_RATE_REPORT = 0x87,
47 };
48
49 enum {
50 MCU_ATE_SET_TRX = 0x1,
51 MCU_ATE_SET_FREQ_OFFSET = 0xa,
52 };
53
54 struct mt7915_mcu_rxd {
55 __le32 rxd[6];
56
57 __le16 len;
58 __le16 pkt_type_id;
59
60 u8 eid;
61 u8 seq;
62 __le16 __rsv;
63
64 u8 ext_eid;
65 u8 __rsv1[2];
66 u8 s2d_index;
67 };
68
69 struct mt7915_mcu_rdd_report {
70 struct mt7915_mcu_rxd rxd;
71
72 u8 idx;
73 u8 long_detected;
74 u8 constant_prf_detected;
75 u8 staggered_prf_detected;
76 u8 radar_type_idx;
77 u8 periodic_pulse_num;
78 u8 long_pulse_num;
79 u8 hw_pulse_num;
80
81 u8 out_lpn;
82 u8 out_spn;
83 u8 out_crpn;
84 u8 out_crpw;
85 u8 out_crbn;
86 u8 out_stgpn;
87 u8 out_stgpw;
88
89 u8 rsv;
90
91 __le32 out_pri_const;
92 __le32 out_pri_stg[3];
93
94 struct {
95 __le32 start;
96 __le16 pulse_width;
97 __le16 pulse_power;
98 u8 mdrdy_flag;
99 u8 rsv[3];
100 } long_pulse[32];
101
102 struct {
103 __le32 start;
104 __le16 pulse_width;
105 __le16 pulse_power;
106 u8 mdrdy_flag;
107 u8 rsv[3];
108 } periodic_pulse[32];
109
110 struct {
111 __le32 start;
112 __le16 pulse_width;
113 __le16 pulse_power;
114 u8 sc_pass;
115 u8 sw_reset;
116 u8 mdrdy_flag;
117 u8 tx_active;
118 } hw_pulse[32];
119 } __packed;
120
121 struct mt7915_mcu_eeprom_info {
122 __le32 addr;
123 __le32 valid;
124 u8 data[16];
125 } __packed;
126
127 struct mt7915_mcu_ra_info {
128 struct mt7915_mcu_rxd rxd;
129
130 __le32 event_id;
131 __le16 wlan_idx;
132 __le16 ru_idx;
133 __le16 direction;
134 __le16 dump_group;
135
136 __le32 suggest_rate;
137 __le32 min_rate; /* for dynamic sounding */
138 __le32 max_rate; /* for dynamic sounding */
139 __le32 init_rate_down_rate;
140
141 __le16 curr_rate;
142 __le16 init_rate_down_total;
143 __le16 init_rate_down_succ;
144 __le16 success;
145 __le16 attempts;
146
147 __le16 prev_rate;
148 __le16 prob_up_rate;
149 u8 no_rate_up_cnt;
150 u8 ppdu_cnt;
151 u8 gi;
152
153 u8 try_up_fail;
154 u8 try_up_total;
155 u8 suggest_wf;
156 u8 try_up_check;
157 u8 prob_up_period;
158 u8 prob_down_pending;
159 } __packed;
160
161
162 struct mt7915_mcu_phy_rx_info {
163 u8 category;
164 u8 rate;
165 u8 mode;
166 u8 nsts;
167 u8 gi;
168 u8 coding;
169 u8 stbc;
170 u8 bw;
171 };
172
173 #define MT_RA_RATE_NSS GENMASK(8, 6)
174 #define MT_RA_RATE_MCS GENMASK(3, 0)
175 #define MT_RA_RATE_TX_MODE GENMASK(12, 9)
176 #define MT_RA_RATE_DCM_EN BIT(4)
177 #define MT_RA_RATE_BW GENMASK(14, 13)
178
179 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
180 #define MCU_PKT_ID 0xa0
181
182 enum {
183 MCU_Q_QUERY,
184 MCU_Q_SET,
185 MCU_Q_RESERVED,
186 MCU_Q_NA
187 };
188
189 enum {
190 MCU_S2D_H2N,
191 MCU_S2D_C2N,
192 MCU_S2D_H2C,
193 MCU_S2D_H2CN
194 };
195
196 enum {
197 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
198 MCU_CMD_FW_START_REQ = 0x02,
199 MCU_CMD_INIT_ACCESS_REG = 0x3,
200 MCU_CMD_NIC_POWER_CTRL = 0x4,
201 MCU_CMD_PATCH_START_REQ = 0x05,
202 MCU_CMD_PATCH_FINISH_REQ = 0x07,
203 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
204 MCU_CMD_EXT_CID = 0xED,
205 MCU_CMD_FW_SCATTER = 0xEE,
206 MCU_CMD_RESTART_DL_REQ = 0xEF,
207 };
208
209 enum {
210 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
211 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
212 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
213 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
214 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
215 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
216 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
217 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
218 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
219 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
220 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
221 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
222 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
223 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
224 MCU_EXT_CMD_ATE_CTRL = 0x3d,
225 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
226 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
227 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
228 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
229 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
230 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
231 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
232 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
233 MCU_EXT_CMD_SCS_CTRL = 0x82,
234 MCU_EXT_CMD_RATE_CTRL = 0x87,
235 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
236 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
237 MCU_EXT_CMD_SET_SPR = 0xa8,
238 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
239 };
240
241 enum {
242 PATCH_SEM_RELEASE,
243 PATCH_SEM_GET
244 };
245
246 enum {
247 PATCH_NOT_DL_SEM_FAIL,
248 PATCH_IS_DL,
249 PATCH_NOT_DL_SEM_SUCCESS,
250 PATCH_REL_SEM_SUCCESS
251 };
252
253 enum {
254 FW_STATE_INITIAL,
255 FW_STATE_FW_DOWNLOAD,
256 FW_STATE_NORMAL_OPERATION,
257 FW_STATE_NORMAL_TRX,
258 FW_STATE_WACPU_RDY = 7
259 };
260
261 enum {
262 EE_MODE_EFUSE,
263 EE_MODE_BUFFER,
264 };
265
266 enum {
267 EE_FORMAT_BIN,
268 EE_FORMAT_WHOLE,
269 EE_FORMAT_MULTIPLE,
270 };
271
272 enum {
273 MCU_PHY_STATE_TX_RATE,
274 MCU_PHY_STATE_RX_RATE,
275 MCU_PHY_STATE_RSSI,
276 MCU_PHY_STATE_CONTENTION_RX_RATE,
277 MCU_PHY_STATE_OFDMLQ_CNINFO,
278 };
279
280 #define STA_TYPE_STA BIT(0)
281 #define STA_TYPE_AP BIT(1)
282 #define STA_TYPE_ADHOC BIT(2)
283 #define STA_TYPE_WDS BIT(4)
284 #define STA_TYPE_BC BIT(5)
285
286 #define NETWORK_INFRA BIT(16)
287 #define NETWORK_P2P BIT(17)
288 #define NETWORK_IBSS BIT(18)
289 #define NETWORK_WDS BIT(21)
290
291 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
292 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
293 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
294 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
295 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
296 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
297 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
298
299 #define CONN_STATE_DISCONNECT 0
300 #define CONN_STATE_CONNECT 1
301 #define CONN_STATE_PORT_SECURE 2
302
303 enum {
304 DEV_INFO_ACTIVE,
305 DEV_INFO_MAX_NUM
306 };
307
308 enum {
309 SCS_SEND_DATA,
310 SCS_SET_MANUAL_PD_TH,
311 SCS_CONFIG,
312 SCS_ENABLE,
313 SCS_SHOW_INFO,
314 SCS_GET_GLO_ADDR,
315 SCS_GET_GLO_ADDR_EVENT,
316 };
317
318 enum {
319 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
320 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
321 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
322 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
323 CMD_CBW_10MHZ,
324 CMD_CBW_5MHZ,
325 CMD_CBW_8080MHZ,
326
327 CMD_HE_MCS_BW80 = 0,
328 CMD_HE_MCS_BW160,
329 CMD_HE_MCS_BW8080,
330 CMD_HE_MCS_BW_NUM
331 };
332
333 struct tlv {
334 __le16 tag;
335 __le16 len;
336 } __packed;
337
338 struct bss_info_omac {
339 __le16 tag;
340 __le16 len;
341 u8 hw_bss_idx;
342 u8 omac_idx;
343 u8 band_idx;
344 u8 rsv0;
345 __le32 conn_type;
346 u32 rsv1;
347 } __packed;
348
349 struct bss_info_basic {
350 __le16 tag;
351 __le16 len;
352 __le32 network_type;
353 u8 active;
354 u8 rsv0;
355 __le16 bcn_interval;
356 u8 bssid[ETH_ALEN];
357 u8 wmm_idx;
358 u8 dtim_period;
359 u8 bmc_wcid_lo;
360 u8 cipher;
361 u8 phy_mode;
362 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
363 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
364 u8 bmc_wcid_hi; /* high Byte and version */
365 u8 rsv[2];
366 } __packed;
367
368 struct bss_info_rf_ch {
369 __le16 tag;
370 __le16 len;
371 u8 pri_ch;
372 u8 center_ch0;
373 u8 center_ch1;
374 u8 bw;
375 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
376 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
377 u8 rsv[2];
378 } __packed;
379
380 struct bss_info_ext_bss {
381 __le16 tag;
382 __le16 len;
383 __le32 mbss_tsf_offset; /* in unit of us */
384 u8 rsv[8];
385 } __packed;
386
387 struct bss_info_bmc_rate {
388 __le16 tag;
389 __le16 len;
390 __le16 bc_trans;
391 __le16 mc_trans;
392 u8 short_preamble;
393 u8 rsv[7];
394 } __packed;
395
396 struct bss_info_ra {
397 __le16 tag;
398 __le16 len;
399 u8 op_mode;
400 u8 adhoc_en;
401 u8 short_preamble;
402 u8 tx_streams;
403 u8 rx_streams;
404 u8 algo;
405 u8 force_sgi;
406 u8 force_gf;
407 u8 ht_mode;
408 u8 has_20_sta; /* Check if any sta support GF. */
409 u8 bss_width_trigger_events;
410 u8 vht_nss_cap;
411 u8 vht_bw_signal; /* not use */
412 u8 vht_force_sgi; /* not use */
413 u8 se_off;
414 u8 antenna_idx;
415 u8 train_up_rule;
416 u8 rsv[3];
417 unsigned short train_up_high_thres;
418 short train_up_rule_rssi;
419 unsigned short low_traffic_thres;
420 __le16 max_phyrate;
421 __le32 phy_cap;
422 __le32 interval;
423 __le32 fast_interval;
424 } __packed;
425
426 struct bss_info_hw_amsdu {
427 __le16 tag;
428 __le16 len;
429 __le32 cmp_bitmap_0;
430 __le32 cmp_bitmap_1;
431 __le16 trig_thres;
432 u8 enable;
433 u8 rsv;
434 } __packed;
435
436 struct bss_info_he {
437 __le16 tag;
438 __le16 len;
439 u8 he_pe_duration;
440 u8 vht_op_info_present;
441 __le16 he_rts_thres;
442 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
443 u8 rsv[6];
444 } __packed;
445
446 struct bss_info_bcn {
447 __le16 tag;
448 __le16 len;
449 u8 ver;
450 u8 enable;
451 __le16 sub_ntlv;
452 } __packed __aligned(4);
453
454 struct bss_info_bcn_csa {
455 __le16 tag;
456 __le16 len;
457 u8 cnt;
458 u8 rsv[3];
459 } __packed __aligned(4);
460
461 struct bss_info_bcn_bcc {
462 __le16 tag;
463 __le16 len;
464 u8 cnt;
465 u8 rsv[3];
466 } __packed __aligned(4);
467
468 struct bss_info_bcn_mbss {
469 #define MAX_BEACON_NUM 32
470 __le16 tag;
471 __le16 len;
472 __le32 bitmap;
473 __le16 offset[MAX_BEACON_NUM];
474 u8 rsv[8];
475 } __packed __aligned(4);
476
477 struct bss_info_bcn_cont {
478 __le16 tag;
479 __le16 len;
480 __le16 tim_ofs;
481 __le16 csa_ofs;
482 __le16 bcc_ofs;
483 __le16 pkt_len;
484 } __packed __aligned(4);
485
486 enum {
487 BSS_INFO_BCN_CSA,
488 BSS_INFO_BCN_BCC,
489 BSS_INFO_BCN_MBSSID,
490 BSS_INFO_BCN_CONTENT,
491 BSS_INFO_BCN_MAX
492 };
493
494 enum {
495 BSS_INFO_OMAC,
496 BSS_INFO_BASIC,
497 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
498 BSS_INFO_PM, /* sta only */
499 BSS_INFO_UAPSD, /* sta only */
500 BSS_INFO_ROAM_DETECT, /* obsoleted */
501 BSS_INFO_LQ_RM, /* obsoleted */
502 BSS_INFO_EXT_BSS,
503 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
504 BSS_INFO_SYNC_MODE, /* obsoleted */
505 BSS_INFO_RA,
506 BSS_INFO_HW_AMSDU,
507 BSS_INFO_BSS_COLOR,
508 BSS_INFO_HE_BASIC,
509 BSS_INFO_PROTECT_INFO,
510 BSS_INFO_OFFLOAD,
511 BSS_INFO_11V_MBSSID,
512 BSS_INFO_MAX_NUM
513 };
514
515 enum {
516 WTBL_RESET_AND_SET = 1,
517 WTBL_SET,
518 WTBL_QUERY,
519 WTBL_RESET_ALL
520 };
521
522 struct wtbl_req_hdr {
523 u8 wlan_idx_lo;
524 u8 operation;
525 __le16 tlv_num;
526 u8 wlan_idx_hi;
527 u8 rsv[3];
528 } __packed;
529
530 struct wtbl_generic {
531 __le16 tag;
532 __le16 len;
533 u8 peer_addr[ETH_ALEN];
534 u8 muar_idx;
535 u8 skip_tx;
536 u8 cf_ack;
537 u8 qos;
538 u8 mesh;
539 u8 adm;
540 __le16 partial_aid;
541 u8 baf_en;
542 u8 aad_om;
543 } __packed;
544
545 struct wtbl_rx {
546 __le16 tag;
547 __le16 len;
548 u8 rcid;
549 u8 rca1;
550 u8 rca2;
551 u8 rv;
552 u8 rsv[4];
553 } __packed;
554
555 struct wtbl_ht {
556 __le16 tag;
557 __le16 len;
558 u8 ht;
559 u8 ldpc;
560 u8 af;
561 u8 mm;
562 u8 rsv[4];
563 } __packed;
564
565 struct wtbl_vht {
566 __le16 tag;
567 __le16 len;
568 u8 ldpc;
569 u8 dyn_bw;
570 u8 vht;
571 u8 txop_ps;
572 u8 rsv[4];
573 } __packed;
574
575 struct wtbl_hdr_trans {
576 __le16 tag;
577 __le16 len;
578 u8 to_ds;
579 u8 from_ds;
580 u8 no_rx_trans;
581 u8 _rsv;
582 };
583
584 enum {
585 MT_BA_TYPE_INVALID,
586 MT_BA_TYPE_ORIGINATOR,
587 MT_BA_TYPE_RECIPIENT
588 };
589
590 enum {
591 RST_BA_MAC_TID_MATCH,
592 RST_BA_MAC_MATCH,
593 RST_BA_NO_MATCH
594 };
595
596 struct wtbl_ba {
597 __le16 tag;
598 __le16 len;
599 /* common */
600 u8 tid;
601 u8 ba_type;
602 u8 rsv0[2];
603 /* originator only */
604 __le16 sn;
605 u8 ba_en;
606 u8 ba_winsize_idx;
607 __le16 ba_winsize;
608 /* recipient only */
609 u8 peer_addr[ETH_ALEN];
610 u8 rst_ba_tid;
611 u8 rst_ba_sel;
612 u8 rst_ba_sb;
613 u8 band_idx;
614 u8 rsv1[4];
615 } __packed;
616
617 struct wtbl_smps {
618 __le16 tag;
619 __le16 len;
620 u8 smps;
621 u8 rsv[3];
622 } __packed;
623
624 enum {
625 WTBL_GENERIC,
626 WTBL_RX,
627 WTBL_HT,
628 WTBL_VHT,
629 WTBL_PEER_PS, /* not used */
630 WTBL_TX_PS,
631 WTBL_HDR_TRANS,
632 WTBL_SEC_KEY,
633 WTBL_BA,
634 WTBL_RDG, /* obsoleted */
635 WTBL_PROTECT, /* not used */
636 WTBL_CLEAR, /* not used */
637 WTBL_BF,
638 WTBL_SMPS,
639 WTBL_RAW_DATA, /* debug only */
640 WTBL_PN,
641 WTBL_SPE,
642 WTBL_MAX_NUM
643 };
644
645 struct sta_ntlv_hdr {
646 u8 rsv[2];
647 __le16 tlv_num;
648 } __packed;
649
650 struct sta_req_hdr {
651 u8 bss_idx;
652 u8 wlan_idx_lo;
653 __le16 tlv_num;
654 u8 is_tlv_append;
655 u8 muar_idx;
656 u8 wlan_idx_hi;
657 u8 rsv;
658 } __packed;
659
660 struct sta_rec_basic {
661 __le16 tag;
662 __le16 len;
663 __le32 conn_type;
664 u8 conn_state;
665 u8 qos;
666 __le16 aid;
667 u8 peer_addr[ETH_ALEN];
668 __le16 extra_info;
669 } __packed;
670
671 struct sta_rec_ht {
672 __le16 tag;
673 __le16 len;
674 __le16 ht_cap;
675 u16 rsv;
676 } __packed;
677
678 struct sta_rec_vht {
679 __le16 tag;
680 __le16 len;
681 __le32 vht_cap;
682 __le16 vht_rx_mcs_map;
683 __le16 vht_tx_mcs_map;
684 u8 rts_bw_sig;
685 u8 rsv[3];
686 } __packed;
687
688 struct sta_rec_uapsd {
689 __le16 tag;
690 __le16 len;
691 u8 dac_map;
692 u8 tac_map;
693 u8 max_sp;
694 u8 rsv0;
695 __le16 listen_interval;
696 u8 rsv1[2];
697 } __packed;
698
699 struct sta_rec_muru {
700 __le16 tag;
701 __le16 len;
702
703 struct {
704 bool ofdma_dl_en;
705 bool ofdma_ul_en;
706 bool mimo_dl_en;
707 bool mimo_ul_en;
708 u8 rsv[4];
709 } cfg;
710
711 struct {
712 u8 punc_pream_rx;
713 bool he_20m_in_40m_2g;
714 bool he_20m_in_160m;
715 bool he_80m_in_160m;
716 bool lt16_sigb;
717 bool rx_su_comp_sigb;
718 bool rx_su_non_comp_sigb;
719 u8 rsv;
720 } ofdma_dl;
721
722 struct {
723 u8 t_frame_dur;
724 u8 mu_cascading;
725 u8 uo_ra;
726 u8 he_2x996_tone;
727 u8 rx_t_frame_11ac;
728 u8 rsv[3];
729 } ofdma_ul;
730
731 struct {
732 bool vht_mu_bfee;
733 bool partial_bw_dl_mimo;
734 u8 rsv[2];
735 } mimo_dl;
736
737 struct {
738 bool full_ul_mimo;
739 bool partial_ul_mimo;
740 u8 rsv[2];
741 } mimo_ul;
742 } __packed;
743
744 struct sta_rec_he {
745 __le16 tag;
746 __le16 len;
747
748 __le32 he_cap;
749
750 u8 t_frame_dur;
751 u8 max_ampdu_exp;
752 u8 bw_set;
753 u8 device_class;
754 u8 dcm_tx_mode;
755 u8 dcm_tx_max_nss;
756 u8 dcm_rx_mode;
757 u8 dcm_rx_max_nss;
758 u8 dcm_max_ru;
759 u8 punc_pream_rx;
760 u8 pkt_ext;
761 u8 rsv1;
762
763 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
764
765 u8 rsv2[2];
766 } __packed;
767
768 struct sta_rec_ba {
769 __le16 tag;
770 __le16 len;
771 u8 tid;
772 u8 ba_type;
773 u8 amsdu;
774 u8 ba_en;
775 __le16 ssn;
776 __le16 winsize;
777 } __packed;
778
779 struct sta_rec_amsdu {
780 __le16 tag;
781 __le16 len;
782 u8 max_amsdu_num;
783 u8 max_mpdu_size;
784 u8 amsdu_en;
785 u8 rsv;
786 } __packed;
787
788 struct sec_key {
789 u8 cipher_id;
790 u8 cipher_len;
791 u8 key_id;
792 u8 key_len;
793 u8 key[32];
794 } __packed;
795
796 struct sta_rec_sec {
797 __le16 tag;
798 __le16 len;
799 u8 add;
800 u8 n_cipher;
801 u8 rsv[2];
802
803 struct sec_key key[2];
804 } __packed;
805
806 struct ra_phy {
807 u8 type;
808 u8 flag;
809 u8 stbc;
810 u8 sgi;
811 u8 bw;
812 u8 ldpc;
813 u8 mcs;
814 u8 nss;
815 u8 he_ltf;
816 };
817
818 struct sta_rec_ra {
819 __le16 tag;
820 __le16 len;
821
822 u8 valid;
823 u8 auto_rate;
824 u8 phy_mode;
825 u8 channel;
826 u8 bw;
827 u8 disable_cck;
828 u8 ht_mcs32;
829 u8 ht_gf;
830 u8 ht_mcs[4];
831 u8 mmps_mode;
832 u8 gband_256;
833 u8 af;
834 u8 auth_wapi_mode;
835 u8 rate_len;
836
837 u8 supp_mode;
838 u8 supp_cck_rate;
839 u8 supp_ofdm_rate;
840 __le32 supp_ht_mcs;
841 __le16 supp_vht_mcs[4];
842
843 u8 op_mode;
844 u8 op_vht_chan_width;
845 u8 op_vht_rx_nss;
846 u8 op_vht_rx_nss_type;
847
848 __le32 sta_status;
849
850 struct ra_phy phy;
851 } __packed;
852
853 struct sta_rec_ra_fixed {
854 __le16 tag;
855 __le16 len;
856
857 __le32 field;
858 u8 op_mode;
859 u8 op_vht_chan_width;
860 u8 op_vht_rx_nss;
861 u8 op_vht_rx_nss_type;
862
863 struct ra_phy phy;
864
865 u8 spe_en;
866 u8 short_preamble;
867 u8 is_5g;
868 u8 mmps_mode;
869 } __packed;
870
871 #define RATE_PARAM_FIXED 3
872 #define RATE_PARAM_AUTO 20
873 #define RATE_CFG_MCS GENMASK(3, 0)
874 #define RATE_CFG_NSS GENMASK(7, 4)
875 #define RATE_CFG_GI GENMASK(11, 8)
876 #define RATE_CFG_BW GENMASK(15, 12)
877 #define RATE_CFG_STBC GENMASK(19, 16)
878 #define RATE_CFG_LDPC GENMASK(23, 20)
879 #define RATE_CFG_PHY_TYPE GENMASK(27, 24)
880
881 struct sta_rec_bf {
882 __le16 tag;
883 __le16 len;
884
885 __le16 pfmu; /* 0xffff: no access right for PFMU */
886 bool su_mu; /* 0: SU, 1: MU */
887 u8 bf_cap; /* 0: iBF, 1: eBF */
888 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
889 u8 ndpa_rate;
890 u8 ndp_rate;
891 u8 rept_poll_rate;
892 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
893 u8 nc;
894 u8 nr;
895 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
896
897 u8 mem_total;
898 u8 mem_20m;
899 struct {
900 u8 row;
901 u8 col: 6, row_msb: 2;
902 } mem[4];
903
904 __le16 smart_ant;
905 u8 se_idx;
906 u8 auto_sounding; /* b7: low traffic indicator
907 * b6: Stop sounding for this entry
908 * b5 ~ b0: postpone sounding
909 */
910 u8 ibf_timeout;
911 u8 ibf_dbw;
912 u8 ibf_ncol;
913 u8 ibf_nrow;
914 u8 nr_bw160;
915 u8 nc_bw160;
916 u8 ru_start_idx;
917 u8 ru_end_idx;
918
919 bool trigger_su;
920 bool trigger_mu;
921 bool ng16_su;
922 bool ng16_mu;
923 bool codebook42_su;
924 bool codebook75_mu;
925
926 u8 he_ltf;
927 u8 rsv[2];
928 } __packed;
929
930 struct sta_rec_bfee {
931 __le16 tag;
932 __le16 len;
933 bool fb_identity_matrix; /* 1: feedback identity matrix */
934 bool ignore_feedback; /* 1: ignore */
935 u8 rsv[2];
936 } __packed;
937
938 enum {
939 STA_REC_BASIC,
940 STA_REC_RA,
941 STA_REC_RA_CMM_INFO,
942 STA_REC_RA_UPDATE,
943 STA_REC_BF,
944 STA_REC_AMSDU,
945 STA_REC_BA,
946 STA_REC_RED, /* not used */
947 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
948 STA_REC_HT,
949 STA_REC_VHT,
950 STA_REC_APPS,
951 STA_REC_KEY,
952 STA_REC_WTBL,
953 STA_REC_HE,
954 STA_REC_HW_AMSDU,
955 STA_REC_WTBL_AADOM,
956 STA_REC_KEY_V2,
957 STA_REC_MURU,
958 STA_REC_MUEDCA,
959 STA_REC_BFEE,
960 STA_REC_MAX_NUM
961 };
962
963 enum mt7915_cipher_type {
964 MT_CIPHER_NONE,
965 MT_CIPHER_WEP40,
966 MT_CIPHER_WEP104,
967 MT_CIPHER_WEP128,
968 MT_CIPHER_TKIP,
969 MT_CIPHER_AES_CCMP,
970 MT_CIPHER_CCMP_256,
971 MT_CIPHER_GCMP,
972 MT_CIPHER_GCMP_256,
973 MT_CIPHER_WAPI,
974 MT_CIPHER_BIP_CMAC_128,
975 };
976
977 enum {
978 CH_SWITCH_NORMAL = 0,
979 CH_SWITCH_SCAN = 3,
980 CH_SWITCH_MCC = 4,
981 CH_SWITCH_DFS = 5,
982 CH_SWITCH_BACKGROUND_SCAN_START = 6,
983 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
984 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
985 CH_SWITCH_SCAN_BYPASS_DPD = 9
986 };
987
988 enum {
989 THERMAL_SENSOR_TEMP_QUERY,
990 THERMAL_SENSOR_MANUAL_CTRL,
991 THERMAL_SENSOR_INFO_QUERY,
992 THERMAL_SENSOR_TASK_CTRL,
993 };
994
995 enum {
996 MT_EBF = BIT(0), /* explicit beamforming */
997 MT_IBF = BIT(1) /* implicit beamforming */
998 };
999
1000 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
1001 sizeof(struct wtbl_generic) + \
1002 sizeof(struct wtbl_rx) + \
1003 sizeof(struct wtbl_ht) + \
1004 sizeof(struct wtbl_vht) + \
1005 sizeof(struct wtbl_hdr_trans) +\
1006 sizeof(struct wtbl_ba) + \
1007 sizeof(struct wtbl_smps))
1008
1009 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1010 sizeof(struct sta_rec_basic) + \
1011 sizeof(struct sta_rec_ht) + \
1012 sizeof(struct sta_rec_he) + \
1013 sizeof(struct sta_rec_ba) + \
1014 sizeof(struct sta_rec_vht) + \
1015 sizeof(struct sta_rec_uapsd) + \
1016 sizeof(struct sta_rec_amsdu) + \
1017 sizeof(struct tlv) + \
1018 MT7915_WTBL_UPDATE_MAX_SIZE)
1019
1020 #define MT7915_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \
1021 sizeof(struct wtbl_ba))
1022
1023 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1024 sizeof(struct bss_info_omac) + \
1025 sizeof(struct bss_info_basic) +\
1026 sizeof(struct bss_info_rf_ch) +\
1027 sizeof(struct bss_info_ra) + \
1028 sizeof(struct bss_info_hw_amsdu) +\
1029 sizeof(struct bss_info_he) + \
1030 sizeof(struct bss_info_bmc_rate) +\
1031 sizeof(struct bss_info_ext_bss))
1032
1033 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \
1034 sizeof(struct bss_info_bcn_csa) + \
1035 sizeof(struct bss_info_bcn_bcc) + \
1036 sizeof(struct bss_info_bcn_mbss) + \
1037 sizeof(struct bss_info_bcn_cont))
1038
1039 #define PHY_MODE_A BIT(0)
1040 #define PHY_MODE_B BIT(1)
1041 #define PHY_MODE_G BIT(2)
1042 #define PHY_MODE_GN BIT(3)
1043 #define PHY_MODE_AN BIT(4)
1044 #define PHY_MODE_AC BIT(5)
1045 #define PHY_MODE_AX_24G BIT(6)
1046 #define PHY_MODE_AX_5G BIT(7)
1047 #define PHY_MODE_AX_6G BIT(8)
1048
1049 #define MODE_CCK BIT(0)
1050 #define MODE_OFDM BIT(1)
1051 #define MODE_HT BIT(2)
1052 #define MODE_VHT BIT(3)
1053 #define MODE_HE BIT(4)
1054
1055 #define STA_CAP_WMM BIT(0)
1056 #define STA_CAP_SGI_20 BIT(4)
1057 #define STA_CAP_SGI_40 BIT(5)
1058 #define STA_CAP_TX_STBC BIT(6)
1059 #define STA_CAP_RX_STBC BIT(7)
1060 #define STA_CAP_VHT_SGI_80 BIT(16)
1061 #define STA_CAP_VHT_SGI_160 BIT(17)
1062 #define STA_CAP_VHT_TX_STBC BIT(18)
1063 #define STA_CAP_VHT_RX_STBC BIT(19)
1064 #define STA_CAP_VHT_LDPC BIT(23)
1065 #define STA_CAP_LDPC BIT(24)
1066 #define STA_CAP_HT BIT(26)
1067 #define STA_CAP_VHT BIT(27)
1068 #define STA_CAP_HE BIT(28)
1069
1070 /* HE MAC */
1071 #define STA_REC_HE_CAP_HTC BIT(0)
1072 #define STA_REC_HE_CAP_BQR BIT(1)
1073 #define STA_REC_HE_CAP_BSR BIT(2)
1074 #define STA_REC_HE_CAP_OM BIT(3)
1075 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
1076 /* HE PHY */
1077 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
1078 #define STA_REC_HE_CAP_LDPC BIT(6)
1079 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
1080 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
1081 /* STBC */
1082 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
1083 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
1084 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
1085 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
1086 /* GI */
1087 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
1088 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
1089 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
1090 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
1091 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
1092 /* 242 TONE */
1093 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
1094 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
1095 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
1096
1097 #endif
Linux with added FPC-III support