| blob | 0c070288a140f41ea8513362520e8dfcea1598f1 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 <http://rt2x00.serialmonkey.com>
6 */
8 /*
9 Module: rt2500usb
10 Abstract: Data structures and registers for the rt2500usb module.
11 Supported chipsets: RT2570.
12 */
14 #ifndef RT2500USB_H
15 #define RT2500USB_H
17 /*
18 * RF chip defines.
19 */
20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0005
25 #define RF5222 0x0010
27 /*
28 * RT2570 version
29 */
30 #define RT2570_VERSION_B 2
31 #define RT2570_VERSION_C 3
32 #define RT2570_VERSION_D 4
34 /*
35 * Signal information.
36 * Default offset is required for RSSI <-> dBm conversion.
37 */
38 #define DEFAULT_RSSI_OFFSET 120
40 /*
41 * Register layout information.
42 */
43 #define CSR_REG_BASE 0x0400
44 #define CSR_REG_SIZE 0x0100
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x006e
47 #define BBP_BASE 0x0000
48 #define BBP_SIZE 0x0060
49 #define RF_BASE 0x0004
50 #define RF_SIZE 0x0010
52 /*
53 * Number of TX queues.
54 */
55 #define NUM_TX_QUEUES 2
57 /*
58 * Control/Status Registers(CSR).
59 * Some values are set in TU, whereas 1 TU == 1024 us.
60 */
62 /*
63 * MAC_CSR0: ASIC revision number.
64 */
65 #define MAC_CSR0 0x0400
67 /*
68 * MAC_CSR1: System control.
69 * SOFT_RESET: Software reset, 1: reset, 0: normal.
70 * BBP_RESET: Hardware reset, 1: reset, 0, release.
71 * HOST_READY: Host ready after initialization.
72 */
73 #define MAC_CSR1 0x0402
74 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
75 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
76 #define MAC_CSR1_HOST_READY FIELD16(0x00000004)
78 /*
79 * MAC_CSR2: STA MAC register 0.
80 */
81 #define MAC_CSR2 0x0404
82 #define MAC_CSR2_BYTE0 FIELD16(0x00ff)
83 #define MAC_CSR2_BYTE1 FIELD16(0xff00)
85 /*
86 * MAC_CSR3: STA MAC register 1.
87 */
88 #define MAC_CSR3 0x0406
89 #define MAC_CSR3_BYTE2 FIELD16(0x00ff)
90 #define MAC_CSR3_BYTE3 FIELD16(0xff00)
92 /*
93 * MAC_CSR4: STA MAC register 2.
94 */
95 #define MAC_CSR4 0X0408
96 #define MAC_CSR4_BYTE4 FIELD16(0x00ff)
97 #define MAC_CSR4_BYTE5 FIELD16(0xff00)
99 /*
100 * MAC_CSR5: BSSID register 0.
101 */
102 #define MAC_CSR5 0x040a
103 #define MAC_CSR5_BYTE0 FIELD16(0x00ff)
104 #define MAC_CSR5_BYTE1 FIELD16(0xff00)
106 /*
107 * MAC_CSR6: BSSID register 1.
108 */
109 #define MAC_CSR6 0x040c
110 #define MAC_CSR6_BYTE2 FIELD16(0x00ff)
111 #define MAC_CSR6_BYTE3 FIELD16(0xff00)
113 /*
114 * MAC_CSR7: BSSID register 2.
115 */
116 #define MAC_CSR7 0x040e
117 #define MAC_CSR7_BYTE4 FIELD16(0x00ff)
118 #define MAC_CSR7_BYTE5 FIELD16(0xff00)
120 /*
121 * MAC_CSR8: Max frame length.
122 */
123 #define MAC_CSR8 0x0410
124 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
126 /*
127 * Misc MAC_CSR registers.
128 * MAC_CSR9: Timer control.
129 * MAC_CSR10: Slot time.
130 * MAC_CSR11: SIFS.
131 * MAC_CSR12: EIFS.
132 * MAC_CSR13: Power mode0.
133 * MAC_CSR14: Power mode1.
134 * MAC_CSR15: Power saving transition0
135 * MAC_CSR16: Power saving transition1
136 */
137 #define MAC_CSR9 0x0412
138 #define MAC_CSR10 0x0414
139 #define MAC_CSR11 0x0416
140 #define MAC_CSR12 0x0418
141 #define MAC_CSR13 0x041a
142 #define MAC_CSR14 0x041c
143 #define MAC_CSR15 0x041e
144 #define MAC_CSR16 0x0420
146 /*
147 * MAC_CSR17: Manual power control / status register.
148 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
149 * SET_STATE: Set state. Write 1 to trigger, self cleared.
150 * BBP_DESIRE_STATE: BBP desired state.
151 * RF_DESIRE_STATE: RF desired state.
152 * BBP_CURRENT_STATE: BBP current state.
153 * RF_CURRENT_STATE: RF current state.
154 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
155 */
156 #define MAC_CSR17 0x0422
157 #define MAC_CSR17_SET_STATE FIELD16(0x0001)
158 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
159 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
160 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
161 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
162 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
164 /*
165 * MAC_CSR18: Wakeup timer register.
166 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
167 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
168 * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
169 */
170 #define MAC_CSR18 0x0424
171 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
172 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
173 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
175 /*
176 * MAC_CSR19: GPIO control register.
177 * MAC_CSR19_VALx: GPIO value
178 * MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output
179 */
180 #define MAC_CSR19 0x0426
181 #define MAC_CSR19_VAL0 FIELD16(0x0001)
182 #define MAC_CSR19_VAL1 FIELD16(0x0002)
183 #define MAC_CSR19_VAL2 FIELD16(0x0004)
184 #define MAC_CSR19_VAL3 FIELD16(0x0008)
185 #define MAC_CSR19_VAL4 FIELD16(0x0010)
186 #define MAC_CSR19_VAL5 FIELD16(0x0020)
187 #define MAC_CSR19_VAL6 FIELD16(0x0040)
188 #define MAC_CSR19_VAL7 FIELD16(0x0080)
189 #define MAC_CSR19_DIR0 FIELD16(0x0100)
190 #define MAC_CSR19_DIR1 FIELD16(0x0200)
191 #define MAC_CSR19_DIR2 FIELD16(0x0400)
192 #define MAC_CSR19_DIR3 FIELD16(0x0800)
193 #define MAC_CSR19_DIR4 FIELD16(0x1000)
194 #define MAC_CSR19_DIR5 FIELD16(0x2000)
195 #define MAC_CSR19_DIR6 FIELD16(0x4000)
196 #define MAC_CSR19_DIR7 FIELD16(0x8000)
198 /*
199 * MAC_CSR20: LED control register.
200 * ACTIVITY: 0: idle, 1: active.
201 * LINK: 0: linkoff, 1: linkup.
202 * ACTIVITY_POLARITY: 0: active low, 1: active high.
203 */
204 #define MAC_CSR20 0x0428
205 #define MAC_CSR20_ACTIVITY FIELD16(0x0001)
206 #define MAC_CSR20_LINK FIELD16(0x0002)
207 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
209 /*
210 * MAC_CSR21: LED control register.
211 * ON_PERIOD: On period, default 70ms.
212 * OFF_PERIOD: Off period, default 30ms.
213 */
214 #define MAC_CSR21 0x042a
215 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
216 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
218 /*
219 * MAC_CSR22: Collision window control register.
220 */
221 #define MAC_CSR22 0x042c
223 /*
224 * Transmit related CSRs.
225 * Some values are set in TU, whereas 1 TU == 1024 us.
226 */
228 /*
229 * TXRX_CSR0: Security control register.
230 */
231 #define TXRX_CSR0 0x0440
232 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
233 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
234 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
236 /*
237 * TXRX_CSR1: TX configuration.
238 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
239 * TSF_OFFSET: TSF offset in MAC header.
240 * AUTO_SEQUENCE: Let ASIC control frame sequence number.
241 */
242 #define TXRX_CSR1 0x0442
243 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
244 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
245 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
247 /*
248 * TXRX_CSR2: RX control.
249 * DISABLE_RX: Disable rx engine.
250 * DROP_CRC: Drop crc error.
251 * DROP_PHYSICAL: Drop physical error.
252 * DROP_CONTROL: Drop control frame.
253 * DROP_NOT_TO_ME: Drop not to me unicast frame.
254 * DROP_TODS: Drop frame tods bit is true.
255 * DROP_VERSION_ERROR: Drop version error frame.
256 * DROP_MCAST: Drop multicast frames.
257 * DROP_BCAST: Drop broadcast frames.
258 */
259 #define TXRX_CSR2 0x0444
260 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
261 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
262 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
263 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
264 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
265 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
266 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
267 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
268 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
270 /*
271 * RX BBP ID registers
272 * TXRX_CSR3: CCK RX BBP ID.
273 * TXRX_CSR4: OFDM RX BBP ID.
274 */
275 #define TXRX_CSR3 0x0446
276 #define TXRX_CSR4 0x0448
278 /*
279 * TXRX_CSR5: CCK TX BBP ID0.
280 */
281 #define TXRX_CSR5 0x044a
282 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
283 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
284 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
285 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
287 /*
288 * TXRX_CSR6: CCK TX BBP ID1.
289 */
290 #define TXRX_CSR6 0x044c
291 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
292 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
293 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
294 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
296 /*
297 * TXRX_CSR7: OFDM TX BBP ID0.
298 */
299 #define TXRX_CSR7 0x044e
300 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
301 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
302 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
303 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
305 /*
306 * TXRX_CSR8: OFDM TX BBP ID1.
307 */
308 #define TXRX_CSR8 0x0450
309 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
310 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
311 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
312 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
314 /*
315 * TXRX_CSR9: TX ACK time-out.
316 */
317 #define TXRX_CSR9 0x0452
319 /*
320 * TXRX_CSR10: Auto responder control.
321 */
322 #define TXRX_CSR10 0x0454
323 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
325 /*
326 * TXRX_CSR11: Auto responder basic rate.
327 */
328 #define TXRX_CSR11 0x0456
330 /*
331 * ACK/CTS time registers.
332 */
333 #define TXRX_CSR12 0x0458
334 #define TXRX_CSR13 0x045a
335 #define TXRX_CSR14 0x045c
336 #define TXRX_CSR15 0x045e
337 #define TXRX_CSR16 0x0460
338 #define TXRX_CSR17 0x0462
340 /*
341 * TXRX_CSR18: Synchronization control register.
342 */
343 #define TXRX_CSR18 0x0464
344 #define TXRX_CSR18_OFFSET FIELD16(0x000f)
345 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
347 /*
348 * TXRX_CSR19: Synchronization control register.
349 * TSF_COUNT: Enable TSF auto counting.
350 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
351 * TBCN: Enable Tbcn with reload value.
352 * BEACON_GEN: Enable beacon generator.
353 */
354 #define TXRX_CSR19 0x0466
355 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
356 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
357 #define TXRX_CSR19_TBCN FIELD16(0x0008)
358 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
360 /*
361 * TXRX_CSR20: Tx BEACON offset time control register.
362 * OFFSET: In units of usec.
363 * BCN_EXPECT_WINDOW: Default: 2^CWmin
364 */
365 #define TXRX_CSR20 0x0468
366 #define TXRX_CSR20_OFFSET FIELD16(0x1fff)
367 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
369 /*
370 * TXRX_CSR21
371 */
372 #define TXRX_CSR21 0x046a
374 /*
375 * Encryption related CSRs.
376 *
377 */
379 /*
380 * SEC_CSR0: Shared key 0, word 0
381 * SEC_CSR1: Shared key 0, word 1
382 * SEC_CSR2: Shared key 0, word 2
383 * SEC_CSR3: Shared key 0, word 3
384 * SEC_CSR4: Shared key 0, word 4
385 * SEC_CSR5: Shared key 0, word 5
386 * SEC_CSR6: Shared key 0, word 6
387 * SEC_CSR7: Shared key 0, word 7
388 */
389 #define SEC_CSR0 0x0480
390 #define SEC_CSR1 0x0482
391 #define SEC_CSR2 0x0484
392 #define SEC_CSR3 0x0486
393 #define SEC_CSR4 0x0488
394 #define SEC_CSR5 0x048a
395 #define SEC_CSR6 0x048c
396 #define SEC_CSR7 0x048e
398 /*
399 * SEC_CSR8: Shared key 1, word 0
400 * SEC_CSR9: Shared key 1, word 1
401 * SEC_CSR10: Shared key 1, word 2
402 * SEC_CSR11: Shared key 1, word 3
403 * SEC_CSR12: Shared key 1, word 4
404 * SEC_CSR13: Shared key 1, word 5
405 * SEC_CSR14: Shared key 1, word 6
406 * SEC_CSR15: Shared key 1, word 7
407 */
408 #define SEC_CSR8 0x0490
409 #define SEC_CSR9 0x0492
410 #define SEC_CSR10 0x0494
411 #define SEC_CSR11 0x0496
412 #define SEC_CSR12 0x0498
413 #define SEC_CSR13 0x049a
414 #define SEC_CSR14 0x049c
415 #define SEC_CSR15 0x049e
417 /*
418 * SEC_CSR16: Shared key 2, word 0
419 * SEC_CSR17: Shared key 2, word 1
420 * SEC_CSR18: Shared key 2, word 2
421 * SEC_CSR19: Shared key 2, word 3
422 * SEC_CSR20: Shared key 2, word 4
423 * SEC_CSR21: Shared key 2, word 5
424 * SEC_CSR22: Shared key 2, word 6
425 * SEC_CSR23: Shared key 2, word 7
426 */
427 #define SEC_CSR16 0x04a0
428 #define SEC_CSR17 0x04a2
429 #define SEC_CSR18 0X04A4
430 #define SEC_CSR19 0x04a6
431 #define SEC_CSR20 0x04a8
432 #define SEC_CSR21 0x04aa
433 #define SEC_CSR22 0x04ac
434 #define SEC_CSR23 0x04ae
436 /*
437 * SEC_CSR24: Shared key 3, word 0
438 * SEC_CSR25: Shared key 3, word 1
439 * SEC_CSR26: Shared key 3, word 2
440 * SEC_CSR27: Shared key 3, word 3
441 * SEC_CSR28: Shared key 3, word 4
442 * SEC_CSR29: Shared key 3, word 5
443 * SEC_CSR30: Shared key 3, word 6
444 * SEC_CSR31: Shared key 3, word 7
445 */
446 #define SEC_CSR24 0x04b0
447 #define SEC_CSR25 0x04b2
448 #define SEC_CSR26 0x04b4
449 #define SEC_CSR27 0x04b6
450 #define SEC_CSR28 0x04b8
451 #define SEC_CSR29 0x04ba
452 #define SEC_CSR30 0x04bc
453 #define SEC_CSR31 0x04be
455 #define KEY_ENTRY(__idx) \
456 ( SEC_CSR0 + ((__idx) * 16) )
458 /*
459 * PHY control registers.
460 */
462 /*
463 * PHY_CSR0: RF switching timing control.
464 */
465 #define PHY_CSR0 0x04c0
467 /*
468 * PHY_CSR1: TX PA configuration.
469 */
470 #define PHY_CSR1 0x04c2
472 /*
473 * MAC configuration registers.
474 */
476 /*
477 * PHY_CSR2: TX MAC configuration.
478 * NOTE: Both register fields are complete dummy,
479 * documentation and legacy drivers are unclear un
480 * what this register means or what fields exists.
481 */
482 #define PHY_CSR2 0x04c4
483 #define PHY_CSR2_LNA FIELD16(0x0002)
484 #define PHY_CSR2_LNA_MODE FIELD16(0x3000)
486 /*
487 * PHY_CSR3: RX MAC configuration.
488 */
489 #define PHY_CSR3 0x04c6
491 /*
492 * PHY_CSR4: Interface configuration.
493 */
494 #define PHY_CSR4 0x04c8
495 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
497 /*
498 * BBP pre-TX registers.
499 * PHY_CSR5: BBP pre-TX CCK.
500 */
501 #define PHY_CSR5 0x04ca
502 #define PHY_CSR5_CCK FIELD16(0x0003)
503 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
505 /*
506 * BBP pre-TX registers.
507 * PHY_CSR6: BBP pre-TX OFDM.
508 */
509 #define PHY_CSR6 0x04cc
510 #define PHY_CSR6_OFDM FIELD16(0x0003)
511 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
513 /*
514 * PHY_CSR7: BBP access register 0.
515 * BBP_DATA: BBP data.
516 * BBP_REG_ID: BBP register ID.
517 * BBP_READ_CONTROL: 0: write, 1: read.
518 */
519 #define PHY_CSR7 0x04ce
520 #define PHY_CSR7_DATA FIELD16(0x00ff)
521 #define PHY_CSR7_REG_ID FIELD16(0x7f00)
522 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
524 /*
525 * PHY_CSR8: BBP access register 1.
526 * BBP_BUSY: ASIC is busy execute BBP programming.
527 */
528 #define PHY_CSR8 0x04d0
529 #define PHY_CSR8_BUSY FIELD16(0x0001)
531 /*
532 * PHY_CSR9: RF access register.
533 * RF_VALUE: Register value + id to program into rf/if.
534 */
535 #define PHY_CSR9 0x04d2
536 #define PHY_CSR9_RF_VALUE FIELD16(0xffff)
538 /*
539 * PHY_CSR10: RF access register.
540 * RF_VALUE: Register value + id to program into rf/if.
541 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
542 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
543 * RF_PLL_LD: Rf pll_ld status.
544 * RF_BUSY: 1: asic is busy execute rf programming.
545 */
546 #define PHY_CSR10 0x04d4
547 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
548 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
549 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
550 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
551 #define PHY_CSR10_RF_BUSY FIELD16(0x8000)
553 /*
554 * STA_CSR0: FCS error count.
555 * FCS_ERROR: FCS error count, cleared when read.
556 */
557 #define STA_CSR0 0x04e0
558 #define STA_CSR0_FCS_ERROR FIELD16(0xffff)
560 /*
561 * STA_CSR1: PLCP error count.
562 */
563 #define STA_CSR1 0x04e2
565 /*
566 * STA_CSR2: LONG error count.
567 */
568 #define STA_CSR2 0x04e4
570 /*
571 * STA_CSR3: CCA false alarm.
572 * FALSE_CCA_ERROR: False CCA error count, cleared when read.
573 */
574 #define STA_CSR3 0x04e6
575 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
577 /*
578 * STA_CSR4: RX FIFO overflow.
579 */
580 #define STA_CSR4 0x04e8
582 /*
583 * STA_CSR5: Beacon sent counter.
584 */
585 #define STA_CSR5 0x04ea
587 /*
588 * Statistics registers
589 */
590 #define STA_CSR6 0x04ec
591 #define STA_CSR7 0x04ee
592 #define STA_CSR8 0x04f0
593 #define STA_CSR9 0x04f2
594 #define STA_CSR10 0x04f4
596 /*
597 * BBP registers.
598 * The wordsize of the BBP is 8 bits.
599 */
601 /*
602 * R2: TX antenna control
603 */
604 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
605 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
607 /*
608 * R14: RX antenna control
609 */
610 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
611 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
613 /*
614 * RF registers.
615 */
617 /*
618 * RF 1
619 */
620 #define RF1_TUNER FIELD32(0x00020000)
622 /*
623 * RF 3
624 */
625 #define RF3_TUNER FIELD32(0x00000100)
626 #define RF3_TXPOWER FIELD32(0x00003e00)
628 /*
629 * EEPROM contents.
630 */
632 /*
633 * HW MAC address.
634 */
635 #define EEPROM_MAC_ADDR_0 0x0002
636 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
637 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
638 #define EEPROM_MAC_ADDR1 0x0003
639 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
640 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
641 #define EEPROM_MAC_ADDR_2 0x0004
642 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
643 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
645 /*
646 * EEPROM antenna.
647 * ANTENNA_NUM: Number of antenna's.
648 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
649 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
650 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
651 * DYN_TXAGC: Dynamic TX AGC control.
652 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
653 * RF_TYPE: Rf_type of this adapter.
654 */
655 #define EEPROM_ANTENNA 0x000b
656 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
657 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
658 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
659 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
660 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
661 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
662 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
664 /*
665 * EEPROM NIC config.
666 * CARDBUS_ACCEL: 0: enable, 1: disable.
667 * DYN_BBP_TUNE: 0: enable, 1: disable.
668 * CCK_TX_POWER: CCK TX power compensation.
669 */
670 #define EEPROM_NIC 0x000c
671 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
672 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
673 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
675 /*
676 * EEPROM geography.
677 * GEO: Default geography setting for device.
678 */
679 #define EEPROM_GEOGRAPHY 0x000d
680 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
682 /*
683 * EEPROM BBP.
684 */
685 #define EEPROM_BBP_START 0x000e
686 #define EEPROM_BBP_SIZE 16
687 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
688 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
690 /*
691 * EEPROM TXPOWER
692 */
693 #define EEPROM_TXPOWER_START 0x001e
694 #define EEPROM_TXPOWER_SIZE 7
695 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
696 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
698 /*
699 * EEPROM Tuning threshold
700 */
701 #define EEPROM_BBPTUNE 0x0030
702 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
704 /*
705 * EEPROM BBP R24 Tuning.
706 */
707 #define EEPROM_BBPTUNE_R24 0x0031
708 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
709 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
711 /*
712 * EEPROM BBP R25 Tuning.
713 */
714 #define EEPROM_BBPTUNE_R25 0x0032
715 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
716 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
718 /*
719 * EEPROM BBP R24 Tuning.
720 */
721 #define EEPROM_BBPTUNE_R61 0x0033
722 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
723 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
725 /*
726 * EEPROM BBP VGC Tuning.
727 */
728 #define EEPROM_BBPTUNE_VGC 0x0034
729 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
730 #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00)
732 /*
733 * EEPROM BBP R17 Tuning.
734 */
735 #define EEPROM_BBPTUNE_R17 0x0035
736 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
737 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
739 /*
740 * RSSI <-> dBm offset calibration
741 */
742 #define EEPROM_CALIBRATE_OFFSET 0x0036
743 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
745 /*
746 * DMA descriptor defines.
747 */
748 #define TXD_DESC_SIZE ( 5 * sizeof(__le32) )
749 #define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
751 /*
752 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
753 */
755 /*
756 * Word0
757 */
758 #define TXD_W0_PACKET_ID FIELD32(0x0000000f)
759 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
760 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
761 #define TXD_W0_ACK FIELD32(0x00000200)
762 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
763 #define TXD_W0_OFDM FIELD32(0x00000800)
764 #define TXD_W0_NEW_SEQ FIELD32(0x00001000)
765 #define TXD_W0_IFS FIELD32(0x00006000)
766 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
767 #define TXD_W0_CIPHER FIELD32(0x20000000)
768 #define TXD_W0_KEY_ID FIELD32(0xc0000000)
770 /*
771 * Word1
772 */
773 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
774 #define TXD_W1_AIFS FIELD32(0x000000c0)
775 #define TXD_W1_CWMIN FIELD32(0x00000f00)
776 #define TXD_W1_CWMAX FIELD32(0x0000f000)
778 /*
779 * Word2: PLCP information
780 */
781 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
782 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
783 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
784 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
786 /*
787 * Word3
788 */
789 #define TXD_W3_IV FIELD32(0xffffffff)
791 /*
792 * Word4
793 */
794 #define TXD_W4_EIV FIELD32(0xffffffff)
796 /*
797 * RX descriptor format for RX Ring.
798 */
800 /*
801 * Word0
802 */
803 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
804 #define RXD_W0_MULTICAST FIELD32(0x00000004)
805 #define RXD_W0_BROADCAST FIELD32(0x00000008)
806 #define RXD_W0_MY_BSS FIELD32(0x00000010)
807 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
808 #define RXD_W0_OFDM FIELD32(0x00000040)
809 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
810 #define RXD_W0_CIPHER FIELD32(0x00000100)
811 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
812 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
814 /*
815 * Word1
816 */
817 #define RXD_W1_RSSI FIELD32(0x000000ff)
818 #define RXD_W1_SIGNAL FIELD32(0x0000ff00)
820 /*
821 * Word2
822 */
823 #define RXD_W2_IV FIELD32(0xffffffff)
825 /*
826 * Word3
827 */
828 #define RXD_W3_EIV FIELD32(0xffffffff)
830 /*
831 * Macros for converting txpower from EEPROM to mac80211 value
832 * and from mac80211 value to register value.
833 */
834 #define MIN_TXPOWER 0
835 #define MAX_TXPOWER 31
836 #define DEFAULT_TXPOWER 24
838 #define TXPOWER_FROM_DEV(__txpower) \
839 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
841 #define TXPOWER_TO_DEV(__txpower) \
842 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)