WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / ralink / rt2x00 / rt2x00reg.h
blobffe802b42ba45d2223e65204cba31213c5b15e63
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 <http://rt2x00.serialmonkey.com>
6 */
8 /*
9 Module: rt2x00
10 Abstract: rt2x00 generic register information.
13 #ifndef RT2X00REG_H
14 #define RT2X00REG_H
17 * RX crypto status
19 enum rx_crypto {
20 RX_CRYPTO_SUCCESS = 0,
21 RX_CRYPTO_FAIL_ICV = 1,
22 RX_CRYPTO_FAIL_MIC = 2,
23 RX_CRYPTO_FAIL_KEY = 3,
27 * Antenna values
29 enum antenna {
30 ANTENNA_SW_DIVERSITY = 0,
31 ANTENNA_A = 1,
32 ANTENNA_B = 2,
33 ANTENNA_HW_DIVERSITY = 3,
37 * Led mode values.
39 enum led_mode {
40 LED_MODE_DEFAULT = 0,
41 LED_MODE_TXRX_ACTIVITY = 1,
42 LED_MODE_SIGNAL_STRENGTH = 2,
43 LED_MODE_ASUS = 3,
44 LED_MODE_ALPHA = 4,
48 * TSF sync values
50 enum tsf_sync {
51 TSF_SYNC_NONE = 0,
52 TSF_SYNC_INFRA = 1,
53 TSF_SYNC_ADHOC = 2,
54 TSF_SYNC_AP_NONE = 3,
58 * Device states
60 enum dev_state {
61 STATE_DEEP_SLEEP = 0,
62 STATE_SLEEP = 1,
63 STATE_STANDBY = 2,
64 STATE_AWAKE = 3,
67 * Additional device states, these values are
68 * not strict since they are not directly passed
69 * into the device.
71 STATE_RADIO_ON,
72 STATE_RADIO_OFF,
73 STATE_RADIO_IRQ_ON,
74 STATE_RADIO_IRQ_OFF,
78 * IFS backoff values
80 enum ifs {
81 IFS_BACKOFF = 0,
82 IFS_SIFS = 1,
83 IFS_NEW_BACKOFF = 2,
84 IFS_NONE = 3,
88 * IFS backoff values for HT devices
90 enum txop {
91 TXOP_HTTXOP = 0,
92 TXOP_PIFS = 1,
93 TXOP_SIFS = 2,
94 TXOP_BACKOFF = 3,
98 * Cipher types for hardware encryption
100 enum cipher {
101 CIPHER_NONE = 0,
102 CIPHER_WEP64 = 1,
103 CIPHER_WEP128 = 2,
104 CIPHER_TKIP = 3,
105 CIPHER_AES = 4,
107 * The following fields were added by rt61pci and rt73usb.
109 CIPHER_CKIP64 = 5,
110 CIPHER_CKIP128 = 6,
111 CIPHER_TKIP_NO_MIC = 7, /* Don't send to device */
114 * Max cipher type.
115 * Note that CIPHER_NONE isn't counted, and CKIP64 and CKIP128
116 * are excluded due to limitations in mac80211.
118 CIPHER_MAX = 4,
122 * Rate modulations
124 enum rate_modulation {
125 RATE_MODE_CCK = 0,
126 RATE_MODE_OFDM = 1,
127 RATE_MODE_HT_MIX = 2,
128 RATE_MODE_HT_GREENFIELD = 3,
132 * Firmware validation error codes
134 enum firmware_errors {
135 FW_OK,
136 FW_BAD_CRC,
137 FW_BAD_LENGTH,
138 FW_BAD_VERSION,
142 * Register handlers.
143 * We store the position of a register field inside a field structure,
144 * This will simplify the process of setting and reading a certain field
145 * inside the register while making sure the process remains byte order safe.
147 struct rt2x00_field8 {
148 u8 bit_offset;
149 u8 bit_mask;
152 struct rt2x00_field16 {
153 u16 bit_offset;
154 u16 bit_mask;
157 struct rt2x00_field32 {
158 u32 bit_offset;
159 u32 bit_mask;
163 * Power of two check, this will check
164 * if the mask that has been given contains and contiguous set of bits.
165 * Note that we cannot use the is_power_of_2() function since this
166 * check must be done at compile-time.
168 #define is_power_of_two(x) ( !((x) & ((x)-1)) )
169 #define low_bit_mask(x) ( ((x)-1) & ~(x) )
170 #define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x))
173 * Macros to find first set bit in a variable.
174 * These macros behave the same as the __ffs() functions but
175 * the most important difference that this is done during
176 * compile-time rather then run-time.
178 #define compile_ffs2(__x) \
179 __builtin_choose_expr(((__x) & 0x1), 0, 1)
181 #define compile_ffs4(__x) \
182 __builtin_choose_expr(((__x) & 0x3), \
183 (compile_ffs2((__x))), \
184 (compile_ffs2((__x) >> 2) + 2))
186 #define compile_ffs8(__x) \
187 __builtin_choose_expr(((__x) & 0xf), \
188 (compile_ffs4((__x))), \
189 (compile_ffs4((__x) >> 4) + 4))
191 #define compile_ffs16(__x) \
192 __builtin_choose_expr(((__x) & 0xff), \
193 (compile_ffs8((__x))), \
194 (compile_ffs8((__x) >> 8) + 8))
196 #define compile_ffs32(__x) \
197 __builtin_choose_expr(((__x) & 0xffff), \
198 (compile_ffs16((__x))), \
199 (compile_ffs16((__x) >> 16) + 16))
202 * This macro will check the requirements for the FIELD{8,16,32} macros
203 * The mask should be a constant non-zero contiguous set of bits which
204 * does not exceed the given typelimit.
206 #define FIELD_CHECK(__mask, __type) \
207 BUILD_BUG_ON(!(__mask) || \
208 !is_valid_mask(__mask) || \
209 (__mask) != (__type)(__mask)) \
211 #define FIELD8(__mask) \
212 ({ \
213 FIELD_CHECK(__mask, u8); \
214 (struct rt2x00_field8) { \
215 compile_ffs8(__mask), (__mask) \
216 }; \
219 #define FIELD16(__mask) \
220 ({ \
221 FIELD_CHECK(__mask, u16); \
222 (struct rt2x00_field16) { \
223 compile_ffs16(__mask), (__mask) \
224 }; \
227 #define FIELD32(__mask) \
228 ({ \
229 FIELD_CHECK(__mask, u32); \
230 (struct rt2x00_field32) { \
231 compile_ffs32(__mask), (__mask) \
232 }; \
235 #define SET_FIELD(__reg, __type, __field, __value)\
236 ({ \
237 typecheck(__type, __field); \
238 *(__reg) &= ~((__field).bit_mask); \
239 *(__reg) |= ((__value) << \
240 ((__field).bit_offset)) & \
241 ((__field).bit_mask); \
244 #define GET_FIELD(__reg, __type, __field) \
245 ({ \
246 typecheck(__type, __field); \
247 ((__reg) & ((__field).bit_mask)) >> \
248 ((__field).bit_offset); \
251 #define rt2x00_set_field32(__reg, __field, __value) \
252 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
253 #define rt2x00_get_field32(__reg, __field) \
254 GET_FIELD(__reg, struct rt2x00_field32, __field)
256 #define rt2x00_set_field16(__reg, __field, __value) \
257 SET_FIELD(__reg, struct rt2x00_field16, __field, __value)
258 #define rt2x00_get_field16(__reg, __field) \
259 GET_FIELD(__reg, struct rt2x00_field16, __field)
261 #define rt2x00_set_field8(__reg, __field, __value) \
262 SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
263 #define rt2x00_get_field8(__reg, __field) \
264 GET_FIELD(__reg, struct rt2x00_field8, __field)
266 #endif /* RT2X00REG_H */