| blob | 5f208ad509bd43a61019baee275bd091554b4bc8 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 <http://rt2x00.serialmonkey.com>
6 */
8 /*
9 Module: rt61pci
10 Abstract: Data structures and registers for the rt61pci module.
11 Supported chipsets: RT2561, RT2561s, RT2661.
12 */
14 #ifndef RT61PCI_H
15 #define RT61PCI_H
17 /*
18 * RT chip PCI IDs.
19 */
20 #define RT2561s_PCI_ID 0x0301
21 #define RT2561_PCI_ID 0x0302
22 #define RT2661_PCI_ID 0x0401
24 /*
25 * RF chip defines.
26 */
27 #define RF5225 0x0001
28 #define RF5325 0x0002
29 #define RF2527 0x0003
30 #define RF2529 0x0004
32 /*
33 * Signal information.
34 * Default offset is required for RSSI <-> dBm conversion.
35 */
36 #define DEFAULT_RSSI_OFFSET 120
38 /*
39 * Register layout information.
40 */
41 #define CSR_REG_BASE 0x3000
42 #define CSR_REG_SIZE 0x04b0
43 #define EEPROM_BASE 0x0000
44 #define EEPROM_SIZE 0x0100
45 #define BBP_BASE 0x0000
46 #define BBP_SIZE 0x0080
47 #define RF_BASE 0x0004
48 #define RF_SIZE 0x0010
50 /*
51 * Number of TX queues.
52 */
53 #define NUM_TX_QUEUES 4
55 /*
56 * PCI registers.
57 */
59 /*
60 * HOST_CMD_CSR: For HOST to interrupt embedded processor
61 */
62 #define HOST_CMD_CSR 0x0008
63 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
64 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
66 /*
67 * MCU_CNTL_CSR
68 * SELECT_BANK: Select 8051 program bank.
69 * RESET: Enable 8051 reset state.
70 * READY: Ready state for 8051.
71 */
72 #define MCU_CNTL_CSR 0x000c
73 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
74 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
75 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
77 /*
78 * SOFT_RESET_CSR
79 * FORCE_CLOCK_ON: Host force MAC clock ON
80 */
81 #define SOFT_RESET_CSR 0x0010
82 #define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002)
84 /*
85 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
86 */
87 #define MCU_INT_SOURCE_CSR 0x0014
88 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
89 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
90 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
91 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
92 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
93 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
94 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
95 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
96 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
97 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
99 /*
100 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
101 */
102 #define MCU_INT_MASK_CSR 0x0018
103 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
104 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
105 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
106 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
107 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
108 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
109 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
110 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
111 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
112 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
114 /*
115 * PCI_USEC_CSR
116 */
117 #define PCI_USEC_CSR 0x001c
119 /*
120 * Security key table memory.
121 * 16 entries 32-byte for shared key table
122 * 64 entries 32-byte for pairwise key table
123 * 64 entries 8-byte for pairwise ta key table
124 */
125 #define SHARED_KEY_TABLE_BASE 0x1000
126 #define PAIRWISE_KEY_TABLE_BASE 0x1200
127 #define PAIRWISE_TA_TABLE_BASE 0x1a00
129 #define SHARED_KEY_ENTRY(__idx) \
130 (SHARED_KEY_TABLE_BASE + \
131 ((__idx) * sizeof(struct hw_key_entry)))
132 #define PAIRWISE_KEY_ENTRY(__idx) \
133 (PAIRWISE_KEY_TABLE_BASE + \
134 ((__idx) * sizeof(struct hw_key_entry)))
135 #define PAIRWISE_TA_ENTRY(__idx) \
136 (PAIRWISE_TA_TABLE_BASE + \
137 ((__idx) * sizeof(struct hw_pairwise_ta_entry)))
147 u8 cipher;
148 u8 reserved;
151 /*
152 * Other on-chip shared memory space.
153 */
154 #define HW_CIS_BASE 0x2000
155 #define HW_NULL_BASE 0x2b00
157 /*
158 * Since NULL frame won't be that long (256 byte),
159 * We steal 16 tail bytes to save debugging settings.
160 */
161 #define HW_DEBUG_SETTING_BASE 0x2bf0
163 /*
164 * On-chip BEACON frame space.
165 */
166 #define HW_BEACON_BASE0 0x2c00
167 #define HW_BEACON_BASE1 0x2d00
168 #define HW_BEACON_BASE2 0x2e00
169 #define HW_BEACON_BASE3 0x2f00
171 #define HW_BEACON_OFFSET(__index) \
172 (HW_BEACON_BASE0 + (__index * 0x0100))
174 /*
175 * HOST-MCU shared memory.
176 */
178 /*
179 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
180 */
181 #define H2M_MAILBOX_CSR 0x2100
182 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
183 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
184 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
185 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
187 /*
188 * MCU_LEDCS: LED control for MCU Mailbox.
189 */
190 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
191 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
192 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
193 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
194 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
195 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
196 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
197 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
198 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
199 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
200 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
201 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
203 /*
204 * M2H_CMD_DONE_CSR.
205 */
206 #define M2H_CMD_DONE_CSR 0x2104
208 /*
209 * MCU_TXOP_ARRAY_BASE.
210 */
211 #define MCU_TXOP_ARRAY_BASE 0x2110
213 /*
214 * MAC Control/Status Registers(CSR).
215 * Some values are set in TU, whereas 1 TU == 1024 us.
216 */
218 /*
219 * MAC_CSR0: ASIC revision number.
220 */
221 #define MAC_CSR0 0x3000
222 #define MAC_CSR0_REVISION FIELD32(0x0000000f)
223 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
225 /*
226 * MAC_CSR1: System control register.
227 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
228 * BBP_RESET: Hardware reset BBP.
229 * HOST_READY: Host is ready after initialization, 1: ready.
230 */
231 #define MAC_CSR1 0x3004
232 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
233 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
234 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
236 /*
237 * MAC_CSR2: STA MAC register 0.
238 */
239 #define MAC_CSR2 0x3008
240 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
241 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
242 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
243 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
245 /*
246 * MAC_CSR3: STA MAC register 1.
247 * UNICAST_TO_ME_MASK:
248 * Used to mask off bits from byte 5 of the MAC address
249 * to determine the UNICAST_TO_ME bit for RX frames.
250 * The full mask is complemented by BSS_ID_MASK:
251 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
252 */
253 #define MAC_CSR3 0x300c
254 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
255 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
256 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
258 /*
259 * MAC_CSR4: BSSID register 0.
260 */
261 #define MAC_CSR4 0x3010
262 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
263 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
264 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
265 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
267 /*
268 * MAC_CSR5: BSSID register 1.
269 * BSS_ID_MASK:
270 * This mask is used to mask off bits 0 and 1 of byte 5 of the
271 * BSSID. This will make sure that those bits will be ignored
272 * when determining the MY_BSS of RX frames.
273 * 0: 1-BSSID mode (BSS index = 0)
274 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
275 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
276 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
277 */
278 #define MAC_CSR5 0x3014
279 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
280 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
281 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
283 /*
284 * MAC_CSR6: Maximum frame length register.
285 */
286 #define MAC_CSR6 0x3018
287 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
289 /*
290 * MAC_CSR7: Reserved
291 */
292 #define MAC_CSR7 0x301c
294 /*
295 * MAC_CSR8: SIFS/EIFS register.
296 * All units are in US.
297 */
298 #define MAC_CSR8 0x3020
299 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
300 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
301 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
303 /*
304 * MAC_CSR9: Back-Off control register.
305 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
306 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
307 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
308 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
309 */
310 #define MAC_CSR9 0x3024
311 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
312 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
313 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
314 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
316 /*
317 * MAC_CSR10: Power state configuration.
318 */
319 #define MAC_CSR10 0x3028
321 /*
322 * MAC_CSR11: Power saving transition time register.
323 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
324 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
325 * WAKEUP_LATENCY: In unit of TU.
326 */
327 #define MAC_CSR11 0x302c
328 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
329 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
330 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
331 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
333 /*
334 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
335 * CURRENT_STATE: 0:sleep, 1:awake.
336 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
337 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
338 */
339 #define MAC_CSR12 0x3030
340 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
341 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
342 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
343 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
345 /*
346 * MAC_CSR13: GPIO.
347 * MAC_CSR13_VALx: GPIO value
348 * MAC_CSR13_DIRx: GPIO direction: 0 = output; 1 = input
349 */
350 #define MAC_CSR13 0x3034
351 #define MAC_CSR13_VAL0 FIELD32(0x00000001)
352 #define MAC_CSR13_VAL1 FIELD32(0x00000002)
353 #define MAC_CSR13_VAL2 FIELD32(0x00000004)
354 #define MAC_CSR13_VAL3 FIELD32(0x00000008)
355 #define MAC_CSR13_VAL4 FIELD32(0x00000010)
356 #define MAC_CSR13_VAL5 FIELD32(0x00000020)
357 #define MAC_CSR13_DIR0 FIELD32(0x00000100)
358 #define MAC_CSR13_DIR1 FIELD32(0x00000200)
359 #define MAC_CSR13_DIR2 FIELD32(0x00000400)
360 #define MAC_CSR13_DIR3 FIELD32(0x00000800)
361 #define MAC_CSR13_DIR4 FIELD32(0x00001000)
362 #define MAC_CSR13_DIR5 FIELD32(0x00002000)
364 /*
365 * MAC_CSR14: LED control register.
366 * ON_PERIOD: On period, default 70ms.
367 * OFF_PERIOD: Off period, default 30ms.
368 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
369 * SW_LED: s/w LED, 1: ON, 0: OFF.
370 * HW_LED_POLARITY: 0: active low, 1: active high.
371 */
372 #define MAC_CSR14 0x3038
373 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
374 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
375 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
376 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
377 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
378 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
380 /*
381 * MAC_CSR15: NAV control.
382 */
383 #define MAC_CSR15 0x303c
385 /*
386 * TXRX control registers.
387 * Some values are set in TU, whereas 1 TU == 1024 us.
388 */
390 /*
391 * TXRX_CSR0: TX/RX configuration register.
392 * TSF_OFFSET: Default is 24.
393 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
394 * DISABLE_RX: Disable Rx engine.
395 * DROP_CRC: Drop CRC error.
396 * DROP_PHYSICAL: Drop physical error.
397 * DROP_CONTROL: Drop control frame.
398 * DROP_NOT_TO_ME: Drop not to me unicast frame.
399 * DROP_TO_DS: Drop fram ToDs bit is true.
400 * DROP_VERSION_ERROR: Drop version error frame.
401 * DROP_MULTICAST: Drop multicast frames.
402 * DROP_BORADCAST: Drop broadcast frames.
403 * DROP_ACK_CTS: Drop received ACK and CTS.
404 */
405 #define TXRX_CSR0 0x3040
406 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
407 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
408 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
409 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
410 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
411 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
412 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
413 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
414 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
415 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
416 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
417 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
418 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
419 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
421 /*
422 * TXRX_CSR1
423 */
424 #define TXRX_CSR1 0x3044
425 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
426 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
427 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
428 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
429 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
430 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
431 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
432 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
434 /*
435 * TXRX_CSR2
436 */
437 #define TXRX_CSR2 0x3048
438 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
439 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
440 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
441 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
442 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
443 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
444 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
445 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
447 /*
448 * TXRX_CSR3
449 */
450 #define TXRX_CSR3 0x304c
451 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
452 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
453 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
454 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
455 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
456 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
457 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
458 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
460 /*
461 * TXRX_CSR4: Auto-Responder/Tx-retry register.
462 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
463 * OFDM_TX_RATE_DOWN: 1:enable.
464 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
465 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
466 */
467 #define TXRX_CSR4 0x3050
468 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
469 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
470 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
471 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
472 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
473 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
474 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
475 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
476 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
477 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
479 /*
480 * TXRX_CSR5
481 */
482 #define TXRX_CSR5 0x3054
484 /*
485 * TXRX_CSR6: ACK/CTS payload consumed time
486 */
487 #define TXRX_CSR6 0x3058
489 /*
490 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
491 */
492 #define TXRX_CSR7 0x305c
493 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
494 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
495 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
496 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
498 /*
499 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
500 */
501 #define TXRX_CSR8 0x3060
502 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
503 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
504 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
505 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
507 /*
508 * TXRX_CSR9: Synchronization control register.
509 * BEACON_INTERVAL: In unit of 1/16 TU.
510 * TSF_TICKING: Enable TSF auto counting.
511 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
512 * BEACON_GEN: Enable beacon generator.
513 */
514 #define TXRX_CSR9 0x3064
515 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
516 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
517 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
518 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
519 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
520 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
522 /*
523 * TXRX_CSR10: BEACON alignment.
524 */
525 #define TXRX_CSR10 0x3068
527 /*
528 * TXRX_CSR11: AES mask.
529 */
530 #define TXRX_CSR11 0x306c
532 /*
533 * TXRX_CSR12: TSF low 32.
534 */
535 #define TXRX_CSR12 0x3070
536 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
538 /*
539 * TXRX_CSR13: TSF high 32.
540 */
541 #define TXRX_CSR13 0x3074
542 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
544 /*
545 * TXRX_CSR14: TBTT timer.
546 */
547 #define TXRX_CSR14 0x3078
549 /*
550 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
551 */
552 #define TXRX_CSR15 0x307c
554 /*
555 * PHY control registers.
556 * Some values are set in TU, whereas 1 TU == 1024 us.
557 */
559 /*
560 * PHY_CSR0: RF/PS control.
561 */
562 #define PHY_CSR0 0x3080
563 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
564 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
566 /*
567 * PHY_CSR1
568 */
569 #define PHY_CSR1 0x3084
571 /*
572 * PHY_CSR2: Pre-TX BBP control.
573 */
574 #define PHY_CSR2 0x3088
576 /*
577 * PHY_CSR3: BBP serial control register.
578 * VALUE: Register value to program into BBP.
579 * REG_NUM: Selected BBP register.
580 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
581 * BUSY: 1: ASIC is busy execute BBP programming.
582 */
583 #define PHY_CSR3 0x308c
584 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
585 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
586 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
587 #define PHY_CSR3_BUSY FIELD32(0x00010000)
589 /*
590 * PHY_CSR4: RF serial control register
591 * VALUE: Register value (include register id) serial out to RF/IF chip.
592 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
593 * IF_SELECT: 1: select IF to program, 0: select RF to program.
594 * PLL_LD: RF PLL_LD status.
595 * BUSY: 1: ASIC is busy execute RF programming.
596 */
597 #define PHY_CSR4 0x3090
598 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
599 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
600 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
601 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
602 #define PHY_CSR4_BUSY FIELD32(0x80000000)
604 /*
605 * PHY_CSR5: RX to TX signal switch timing control.
606 */
607 #define PHY_CSR5 0x3094
608 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
610 /*
611 * PHY_CSR6: TX to RX signal timing control.
612 */
613 #define PHY_CSR6 0x3098
614 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
616 /*
617 * PHY_CSR7: TX DAC switching timing control.
618 */
619 #define PHY_CSR7 0x309c
621 /*
622 * Security control register.
623 */
625 /*
626 * SEC_CSR0: Shared key table control.
627 */
628 #define SEC_CSR0 0x30a0
629 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
630 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
631 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
632 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
633 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
634 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
635 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
636 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
637 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
638 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
639 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
640 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
641 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
642 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
643 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
644 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
646 /*
647 * SEC_CSR1: Shared key table security mode register.
648 */
649 #define SEC_CSR1 0x30a4
650 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
651 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
652 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
653 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
654 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
655 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
656 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
657 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
659 /*
660 * Pairwise key table valid bitmap registers.
661 * SEC_CSR2: pairwise key table valid bitmap 0.
662 * SEC_CSR3: pairwise key table valid bitmap 1.
663 */
664 #define SEC_CSR2 0x30a8
665 #define SEC_CSR3 0x30ac
667 /*
668 * SEC_CSR4: Pairwise key table lookup control.
669 */
670 #define SEC_CSR4 0x30b0
671 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
672 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
673 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
674 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
676 /*
677 * SEC_CSR5: shared key table security mode register.
678 */
679 #define SEC_CSR5 0x30b4
680 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
681 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
682 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
683 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
684 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
685 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
686 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
687 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
689 /*
690 * STA control registers.
691 */
693 /*
694 * STA_CSR0: RX PLCP error count & RX FCS error count.
695 */
696 #define STA_CSR0 0x30c0
697 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
698 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
700 /*
701 * STA_CSR1: RX False CCA count & RX LONG frame count.
702 */
703 #define STA_CSR1 0x30c4
704 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
705 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
707 /*
708 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
709 */
710 #define STA_CSR2 0x30c8
711 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
712 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
714 /*
715 * STA_CSR3: TX Beacon count.
716 */
717 #define STA_CSR3 0x30cc
718 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
720 /*
721 * STA_CSR4: TX Result status register.
722 * VALID: 1:This register contains a valid TX result.
723 */
724 #define STA_CSR4 0x30d0
725 #define STA_CSR4_VALID FIELD32(0x00000001)
726 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
727 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
728 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
729 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
730 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
732 /*
733 * QOS control registers.
734 */
736 /*
737 * QOS_CSR0: TXOP holder MAC address register.
738 */
739 #define QOS_CSR0 0x30e0
740 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
741 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
742 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
743 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
745 /*
746 * QOS_CSR1: TXOP holder MAC address register.
747 */
748 #define QOS_CSR1 0x30e4
749 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
750 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
752 /*
753 * QOS_CSR2: TXOP holder timeout register.
754 */
755 #define QOS_CSR2 0x30e8
757 /*
758 * RX QOS-CFPOLL MAC address register.
759 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
760 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
761 */
762 #define QOS_CSR3 0x30ec
763 #define QOS_CSR4 0x30f0
765 /*
766 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
767 */
768 #define QOS_CSR5 0x30f4
770 /*
771 * Host DMA registers.
772 */
774 /*
775 * AC0_BASE_CSR: AC_VO base address.
776 */
777 #define AC0_BASE_CSR 0x3400
778 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
780 /*
781 * AC1_BASE_CSR: AC_VI base address.
782 */
783 #define AC1_BASE_CSR 0x3404
784 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
786 /*
787 * AC2_BASE_CSR: AC_BE base address.
788 */
789 #define AC2_BASE_CSR 0x3408
790 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
792 /*
793 * AC3_BASE_CSR: AC_BK base address.
794 */
795 #define AC3_BASE_CSR 0x340c
796 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
798 /*
799 * MGMT_BASE_CSR: MGMT ring base address.
800 */
801 #define MGMT_BASE_CSR 0x3410
802 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
804 /*
805 * TX_RING_CSR0: TX Ring size for AC_VO, AC_VI, AC_BE, AC_BK.
806 */
807 #define TX_RING_CSR0 0x3418
808 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
809 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
810 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
811 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
813 /*
814 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
815 * TXD_SIZE: In unit of 32-bit.
816 */
817 #define TX_RING_CSR1 0x341c
818 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
819 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
820 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
822 /*
823 * AIFSN_CSR: AIFSN for each EDCA AC.
824 * AIFSN0: For AC_VO.
825 * AIFSN1: For AC_VI.
826 * AIFSN2: For AC_BE.
827 * AIFSN3: For AC_BK.
828 */
829 #define AIFSN_CSR 0x3420
830 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
831 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
832 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
833 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
835 /*
836 * CWMIN_CSR: CWmin for each EDCA AC.
837 * CWMIN0: For AC_VO.
838 * CWMIN1: For AC_VI.
839 * CWMIN2: For AC_BE.
840 * CWMIN3: For AC_BK.
841 */
842 #define CWMIN_CSR 0x3424
843 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
844 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
845 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
846 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
848 /*
849 * CWMAX_CSR: CWmax for each EDCA AC.
850 * CWMAX0: For AC_VO.
851 * CWMAX1: For AC_VI.
852 * CWMAX2: For AC_BE.
853 * CWMAX3: For AC_BK.
854 */
855 #define CWMAX_CSR 0x3428
856 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
857 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
858 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
859 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
861 /*
862 * TX_DMA_DST_CSR: TX DMA destination
863 * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
864 */
865 #define TX_DMA_DST_CSR 0x342c
866 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
867 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
868 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
869 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
870 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
872 /*
873 * TX_CNTL_CSR: KICK/Abort TX.
874 * KICK_TX_AC0: For AC_VO.
875 * KICK_TX_AC1: For AC_VI.
876 * KICK_TX_AC2: For AC_BE.
877 * KICK_TX_AC3: For AC_BK.
878 * ABORT_TX_AC0: For AC_VO.
879 * ABORT_TX_AC1: For AC_VI.
880 * ABORT_TX_AC2: For AC_BE.
881 * ABORT_TX_AC3: For AC_BK.
882 */
883 #define TX_CNTL_CSR 0x3430
884 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
885 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
886 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
887 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
888 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
889 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
890 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
891 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
892 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
893 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
895 /*
896 * LOAD_TX_RING_CSR: Load RX desriptor
897 */
898 #define LOAD_TX_RING_CSR 0x3434
899 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
900 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
901 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
902 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
903 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
905 /*
906 * Several read-only registers, for debugging.
907 */
908 #define AC0_TXPTR_CSR 0x3438
909 #define AC1_TXPTR_CSR 0x343c
910 #define AC2_TXPTR_CSR 0x3440
911 #define AC3_TXPTR_CSR 0x3444
912 #define MGMT_TXPTR_CSR 0x3448
914 /*
915 * RX_BASE_CSR
916 */
917 #define RX_BASE_CSR 0x3450
918 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
920 /*
921 * RX_RING_CSR.
922 * RXD_SIZE: In unit of 32-bit.
923 */
924 #define RX_RING_CSR 0x3454
925 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
926 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
927 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
929 /*
930 * RX_CNTL_CSR
931 */
932 #define RX_CNTL_CSR 0x3458
933 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
934 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
936 /*
937 * RXPTR_CSR: Read-only, for debugging.
938 */
939 #define RXPTR_CSR 0x345c
941 /*
942 * PCI_CFG_CSR
943 */
944 #define PCI_CFG_CSR 0x3460
946 /*
947 * BUF_FORMAT_CSR
948 */
949 #define BUF_FORMAT_CSR 0x3464
951 /*
952 * INT_SOURCE_CSR: Interrupt source register.
953 * Write one to clear corresponding bit.
954 */
955 #define INT_SOURCE_CSR 0x3468
956 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
957 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
958 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
959 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
960 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
961 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
962 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
963 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
964 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
965 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
967 /*
968 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
969 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
970 */
971 #define INT_MASK_CSR 0x346c
972 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
973 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
974 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
975 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
976 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
977 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
978 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
979 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
980 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
981 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
982 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
983 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
985 /*
986 * E2PROM_CSR: EEPROM control register.
987 * RELOAD: Write 1 to reload eeprom content.
988 * TYPE_93C46: 1: 93c46, 0:93c66.
989 * LOAD_STATUS: 1:loading, 0:done.
990 */
991 #define E2PROM_CSR 0x3470
992 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
993 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
994 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
995 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
996 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
997 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
998 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
1000 /*
1001 * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
1002 * AC0_TX_OP: For AC_VO, in unit of 32us.
1003 * AC1_TX_OP: For AC_VI, in unit of 32us.
1004 */
1005 #define AC_TXOP_CSR0 0x3474
1006 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
1007 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1009 /*
1010 * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
1011 * AC2_TX_OP: For AC_BE, in unit of 32us.
1012 * AC3_TX_OP: For AC_BK, in unit of 32us.
1013 */
1014 #define AC_TXOP_CSR1 0x3478
1015 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1016 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1018 /*
1019 * DMA_STATUS_CSR
1020 */
1021 #define DMA_STATUS_CSR 0x3480
1023 /*
1024 * TEST_MODE_CSR
1025 */
1026 #define TEST_MODE_CSR 0x3484
1028 /*
1029 * UART0_TX_CSR
1030 */
1031 #define UART0_TX_CSR 0x3488
1033 /*
1034 * UART0_RX_CSR
1035 */
1036 #define UART0_RX_CSR 0x348c
1038 /*
1039 * UART0_FRAME_CSR
1040 */
1041 #define UART0_FRAME_CSR 0x3490
1043 /*
1044 * UART0_BUFFER_CSR
1045 */
1046 #define UART0_BUFFER_CSR 0x3494
1048 /*
1049 * IO_CNTL_CSR
1050 * RF_PS: Set RF interface value to power save
1051 */
1052 #define IO_CNTL_CSR 0x3498
1053 #define IO_CNTL_CSR_RF_PS FIELD32(0x00000004)
1055 /*
1056 * UART_INT_SOURCE_CSR
1057 */
1058 #define UART_INT_SOURCE_CSR 0x34a8
1060 /*
1061 * UART_INT_MASK_CSR
1062 */
1063 #define UART_INT_MASK_CSR 0x34ac
1065 /*
1066 * PBF_QUEUE_CSR
1067 */
1068 #define PBF_QUEUE_CSR 0x34b0
1070 /*
1071 * Firmware DMA registers.
1072 * Firmware DMA registers are dedicated for MCU usage
1073 * and should not be touched by host driver.
1074 * Therefore we skip the definition of these registers.
1075 */
1076 #define FW_TX_BASE_CSR 0x34c0
1077 #define FW_TX_START_CSR 0x34c4
1078 #define FW_TX_LAST_CSR 0x34c8
1079 #define FW_MODE_CNTL_CSR 0x34cc
1080 #define FW_TXPTR_CSR 0x34d0
1082 /*
1083 * 8051 firmware image.
1084 */
1088 #define FIRMWARE_IMAGE_BASE 0x4000
1090 /*
1091 * BBP registers.
1092 * The wordsize of the BBP is 8 bits.
1093 */
1095 /*
1096 * R2
1097 */
1098 #define BBP_R2_BG_MODE FIELD8(0x20)
1100 /*
1101 * R3
1102 */
1103 #define BBP_R3_SMART_MODE FIELD8(0x01)
1105 /*
1106 * R4: RX antenna control
1107 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1108 */
1110 /*
1111 * ANTENNA_CONTROL semantics (guessed):
1112 * 0x1: Software controlled antenna switching (fixed or SW diversity)
1113 * 0x2: Hardware diversity.
1114 */
1115 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
1116 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
1118 /*
1119 * R77
1120 */
1121 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
1123 /*
1124 * RF registers
1125 */
1127 /*
1128 * RF 3
1129 */
1130 #define RF3_TXPOWER FIELD32(0x00003e00)
1132 /*
1133 * RF 4
1134 */
1135 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1137 /*
1138 * EEPROM content.
1139 * The wordsize of the EEPROM is 16 bits.
1140 */
1142 /*
1143 * HW MAC address.
1144 */
1145 #define EEPROM_MAC_ADDR_0 0x0002
1146 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1147 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1148 #define EEPROM_MAC_ADDR1 0x0003
1149 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1150 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1151 #define EEPROM_MAC_ADDR_2 0x0004
1152 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1153 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1155 /*
1156 * EEPROM antenna.
1157 * ANTENNA_NUM: Number of antenna's.
1158 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1159 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1160 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1161 * DYN_TXAGC: Dynamic TX AGC control.
1162 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1163 * RF_TYPE: Rf_type of this adapter.
1164 */
1165 #define EEPROM_ANTENNA 0x0010
1166 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1167 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1168 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1169 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1170 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1171 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1172 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1174 /*
1175 * EEPROM NIC config.
1176 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1177 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1178 * CARDBUS_ACCEL: 0:enable, 1:disable.
1179 * EXTERNAL_LNA_A: External LNA enable for 5G.
1180 */
1181 #define EEPROM_NIC 0x0011
1182 #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1183 #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1184 #define EEPROM_NIC_RX_FIXED FIELD16(0x0004)
1185 #define EEPROM_NIC_TX_FIXED FIELD16(0x0008)
1186 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1187 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1188 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1190 /*
1191 * EEPROM geography.
1192 * GEO_A: Default geographical setting for 5GHz band
1193 * GEO: Default geographical setting.
1194 */
1195 #define EEPROM_GEOGRAPHY 0x0012
1196 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1197 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1199 /*
1200 * EEPROM BBP.
1201 */
1202 #define EEPROM_BBP_START 0x0013
1203 #define EEPROM_BBP_SIZE 16
1204 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1205 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1207 /*
1208 * EEPROM TXPOWER 802.11G
1209 */
1210 #define EEPROM_TXPOWER_G_START 0x0023
1211 #define EEPROM_TXPOWER_G_SIZE 7
1212 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1213 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1215 /*
1216 * EEPROM Frequency
1217 */
1218 #define EEPROM_FREQ 0x002f
1219 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1220 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1221 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
1223 /*
1224 * EEPROM LED.
1225 * POLARITY_RDY_G: Polarity RDY_G setting.
1226 * POLARITY_RDY_A: Polarity RDY_A setting.
1227 * POLARITY_ACT: Polarity ACT setting.
1228 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1229 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1230 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1231 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1232 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1233 * LED_MODE: Led mode.
1234 */
1235 #define EEPROM_LED 0x0030
1236 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1237 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1238 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1239 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1240 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1241 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1242 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1243 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1244 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1246 /*
1247 * EEPROM TXPOWER 802.11A
1248 */
1249 #define EEPROM_TXPOWER_A_START 0x0031
1250 #define EEPROM_TXPOWER_A_SIZE 12
1251 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1252 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1254 /*
1255 * EEPROM RSSI offset 802.11BG
1256 */
1257 #define EEPROM_RSSI_OFFSET_BG 0x004d
1258 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1259 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1261 /*
1262 * EEPROM RSSI offset 802.11A
1263 */
1264 #define EEPROM_RSSI_OFFSET_A 0x004e
1265 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1266 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1268 /*
1269 * MCU mailbox commands.
1270 */
1271 #define MCU_SLEEP 0x30
1272 #define MCU_WAKEUP 0x31
1273 #define MCU_LED 0x50
1274 #define MCU_LED_STRENGTH 0x52
1276 /*
1277 * DMA descriptor defines.
1278 */
1279 #define TXD_DESC_SIZE (16 * sizeof(__le32))
1280 #define TXINFO_SIZE (6 * sizeof(__le32))
1281 #define RXD_DESC_SIZE (16 * sizeof(__le32))
1283 /*
1284 * TX descriptor format for TX, PRIO and Beacon Ring.
1285 */
1287 /*
1288 * Word0
1289 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1290 * KEY_TABLE: Use per-client pairwise KEY table.
1291 * KEY_INDEX:
1292 * Key index (0~31) to the pairwise KEY table.
1293 * 0~3 to shared KEY table 0 (BSS0).
1294 * 4~7 to shared KEY table 1 (BSS1).
1295 * 8~11 to shared KEY table 2 (BSS2).
1296 * 12~15 to shared KEY table 3 (BSS3).
1297 * BURST: Next frame belongs to same "burst" event.
1298 */
1299 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1300 #define TXD_W0_VALID FIELD32(0x00000002)
1301 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1302 #define TXD_W0_ACK FIELD32(0x00000008)
1303 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1304 #define TXD_W0_OFDM FIELD32(0x00000020)
1305 #define TXD_W0_IFS FIELD32(0x00000040)
1306 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1307 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1308 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1309 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1310 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1311 #define TXD_W0_BURST FIELD32(0x10000000)
1312 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1314 /*
1315 * Word1
1316 * HOST_Q_ID: EDCA/HCCA queue ID.
1317 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1318 * BUFFER_COUNT: Number of buffers in this TXD.
1319 */
1320 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1321 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1322 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1323 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1324 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1325 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1326 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1327 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1329 /*
1330 * Word2: PLCP information
1331 */
1332 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1333 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1334 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1335 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1337 /*
1338 * Word3
1339 */
1340 #define TXD_W3_IV FIELD32(0xffffffff)
1342 /*
1343 * Word4
1344 */
1345 #define TXD_W4_EIV FIELD32(0xffffffff)
1347 /*
1348 * Word5
1349 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1350 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1351 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1352 * WAITING_DMA_DONE_INT: TXD been filled with data
1353 * and waiting for TxDoneISR housekeeping.
1354 */
1355 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1356 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1357 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1358 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1359 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1361 /*
1362 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1363 * through TXFIFO. MAC block use this TXINFO to control the transmission
1364 * behavior of this frame.
1365 * The following fields are not used by MAC block.
1366 * They are used by DMA block and HOST driver only.
1367 * Once a frame has been DMA to ASIC, all the following fields are useless
1368 * to ASIC.
1369 */
1371 /*
1372 * Word6-10: Buffer physical address
1373 */
1374 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1375 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1376 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1377 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1378 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1380 /*
1381 * Word11-13: Buffer length
1382 */
1383 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1384 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1385 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1386 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1387 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1389 /*
1390 * Word14
1391 */
1392 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1394 /*
1395 * Word15
1396 */
1397 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1399 /*
1400 * RX descriptor format for RX Ring.
1401 */
1403 /*
1404 * Word0
1405 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1406 * KEY_INDEX: Decryption key actually used.
1407 */
1408 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1409 #define RXD_W0_DROP FIELD32(0x00000002)
1410 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1411 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1412 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1413 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1414 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1415 #define RXD_W0_OFDM FIELD32(0x00000080)
1416 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1417 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1418 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1419 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1421 /*
1422 * Word1
1423 * SIGNAL: RX raw data rate reported by BBP.
1424 */
1425 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1426 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1427 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1428 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1430 /*
1431 * Word2
1432 * IV: Received IV of originally encrypted.
1433 */
1434 #define RXD_W2_IV FIELD32(0xffffffff)
1436 /*
1437 * Word3
1438 * EIV: Received EIV of originally encrypted.
1439 */
1440 #define RXD_W3_EIV FIELD32(0xffffffff)
1442 /*
1443 * Word4
1444 * ICV: Received ICV of originally encrypted.
1445 * NOTE: This is a guess, the official definition is "reserved"
1446 */
1447 #define RXD_W4_ICV FIELD32(0xffffffff)
1449 /*
1450 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1451 * and passed to the HOST driver.
1452 * The following fields are for DMA block and HOST usage only.
1453 * Can't be touched by ASIC MAC block.
1454 */
1456 /*
1457 * Word5
1458 */
1459 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1461 /*
1462 * Word6-15: Reserved
1463 */
1464 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1465 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1466 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1467 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1468 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1469 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1470 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1471 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1472 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1473 #define RXD_W15_RESERVED FIELD32(0xffffffff)
1475 /*
1476 * Macros for converting txpower from EEPROM to mac80211 value
1477 * and from mac80211 value to register value.
1478 */
1479 #define MIN_TXPOWER 0
1480 #define MAX_TXPOWER 31
1481 #define DEFAULT_TXPOWER 24
1483 #define TXPOWER_FROM_DEV(__txpower) \
1484 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1486 #define TXPOWER_TO_DEV(__txpower) \
1487 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)