1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
8 /* 1: MSDU packet queue,
11 #define RTL_PCI_RX_MPDU_QUEUE 0
12 #define RTL_PCI_RX_CMD_QUEUE 1
13 #define RTL_PCI_MAX_RX_QUEUE 2
15 #define RTL_PCI_MAX_RX_COUNT 512/*64*/
16 #define RTL_PCI_MAX_TX_QUEUE_COUNT 9
18 #define RT_TXDESC_NUM 128
19 #define TX_DESC_NUM_92E 512
20 #define TX_DESC_NUM_8822B 512
21 #define RT_TXDESC_NUM_BE_QUEUE 256
27 #define BEACON_QUEUE 4
32 #define H2C_QUEUE TXCMD_QUEUE /* In 8822B */
34 #define RTL_PCI_DEVICE(vend, dev, cfg) \
37 .subvendor = PCI_ANY_ID, \
38 .subdevice = PCI_ANY_ID,\
39 .driver_data = (kernel_ulong_t)&(cfg)
41 #define INTEL_VENDOR_ID 0x8086
42 #define SIS_VENDOR_ID 0x1039
43 #define ATI_VENDOR_ID 0x1002
44 #define ATI_DEVICE_ID 0x7914
45 #define AMD_VENDOR_ID 0x1022
47 #define PCI_MAX_BRIDGE_NUMBER 255
48 #define PCI_MAX_DEVICES 32
49 #define PCI_MAX_FUNCTION 8
51 #define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
52 #define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
54 #define PCI_CLASS_BRIDGE_DEV 0x06
55 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
56 #define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
57 #define PCI_CAP_ID_EXP 0x10
59 #define U1DONTCARE 0xFF
60 #define U2DONTCARE 0xFFFF
61 #define U4DONTCARE 0xFFFFFFFF
63 #define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
64 #define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
65 #define RTL_PCI_8174_DID 0x8174 /*8192 SE */
66 #define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
67 #define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
68 #define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
69 #define RTL_PCI_8723AE_DID 0x8723 /*8723AE */
70 #define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
71 #define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
72 #define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
73 #define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
74 #define RTL_PCI_700F_DID 0x700F
75 #define RTL_PCI_701F_DID 0x701F
76 #define RTL_PCI_DLINK_DID 0x3304
77 #define RTL_PCI_8723AE_DID 0x8723 /*8723e */
78 #define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
79 #define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
80 #define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
81 #define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
82 #define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
83 #define RTL_PCI_8192DE_DID 0x8193 /*8192de */
84 #define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
85 #define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
86 #define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
87 #define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
88 #define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
89 #define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
90 #define RTL_PCI_8822BE_DID 0xB822 /*8822be*/
92 /*8192 support 16 pages of IO registers*/
93 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
94 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
95 #define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
96 #define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
97 #define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
99 #define RTL_PCI_REVISION_ID_8190PCI 0x00
100 #define RTL_PCI_REVISION_ID_8192PCIE 0x01
101 #define RTL_PCI_REVISION_ID_8192SE 0x10
102 #define RTL_PCI_REVISION_ID_8192CE 0x1
103 #define RTL_PCI_REVISION_ID_8192DE 0x0
105 #define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
107 enum pci_bridge_vendor
{
108 PCI_BRIDGE_VENDOR_INTEL
= 0x0, /*0b'0000,0001 */
109 PCI_BRIDGE_VENDOR_ATI
, /*0b'0000,0010*/
110 PCI_BRIDGE_VENDOR_AMD
, /*0b'0000,0100*/
111 PCI_BRIDGE_VENDOR_SIS
, /*0b'0000,1000*/
112 PCI_BRIDGE_VENDOR_UNKNOWN
, /*0b'0100,0000*/
113 PCI_BRIDGE_VENDOR_MAX
,
116 struct rtl_pci_capabilities_header
{
121 /* In new TRX flow, Buffer_desc is new concept
122 * But TX wifi info == TX descriptor in old flow
123 * RX wifi info == RX descriptor in old flow
125 struct rtl_tx_buffer_desc
{
126 u32 dword
[4 * (1 << (BUFDESC_SEG_NUM
+ 1))];
133 struct rtl_rx_buffer_desc
{ /*rx buffer desc*/
137 struct rtl_rx_desc
{ /*old: rx desc new: rx wifi info*/
141 struct rtl_tx_cmd_desc
{
145 struct rtl8192_tx_ring
{
146 struct rtl_tx_desc
*desc
;
149 unsigned int entries
;
150 struct sk_buff_head queue
;
151 /*add for new trx flow*/
152 struct rtl_tx_buffer_desc
*buffer_desc
; /*tx buffer descriptor*/
153 dma_addr_t buffer_desc_dma
; /*tx bufferd desc dma memory*/
154 u16 cur_tx_wp
; /* current_tx_write_point */
155 u16 cur_tx_rp
; /* current_tx_read_point */
158 struct rtl8192_rx_ring
{
159 struct rtl_rx_desc
*desc
;
162 struct sk_buff
*rx_buf
[RTL_PCI_MAX_RX_COUNT
];
163 /*add for new trx flow*/
164 struct rtl_rx_buffer_desc
*buffer_desc
; /*rx buffer descriptor*/
165 u16 next_rx_rp
; /* next_rx_read_point */
169 struct pci_dev
*pdev
;
172 bool driver_is_goingto_unload
;
175 bool being_init_adapter
;
179 struct rtl8192_tx_ring tx_ring
[RTL_PCI_MAX_TX_QUEUE_COUNT
];
180 int txringcount
[RTL_PCI_MAX_TX_QUEUE_COUNT
];
184 struct rtl8192_rx_ring rx_ring
[RTL_PCI_MAX_RX_QUEUE
];
191 u32 irq_mask
[4]; /* 0-1: normal, 2: unused, 3: h2c */
194 /*Bcn control register setting */
195 u32 reg_bcn_ctrl_val
;
197 /*ASPM*/ u8 const_pci_aspm
;
198 u8 const_amdpci_aspm
;
199 u8 const_hwsw_rfoff_d3
;
200 u8 const_support_pciaspm
;
202 u8 const_hostpci_aspm_setting
;
204 u8 const_devicepci_aspm_setting
;
205 /* If it supports ASPM, Offset[560h] = 0x40,
206 * otherwise Offset[560h] = 0x00.
209 bool support_backdoor
;
212 enum acm_method acm_method
;
214 u16 shortretry_limit
;
220 /* interrupt clear before set */
233 u8 pcibridge_funcnum
;
236 u16 pcibridge_vendorid
;
237 u16 pcibridge_deviceid
;
241 u8 pcibridge_pciehdr_offset
;
242 u8 pcibridge_linkctrlreg
;
247 struct rtl_pci_priv
{
248 struct bt_coexist_info bt_coexist
;
249 struct rtl_led_ctl ledctl
;
251 struct mp_adapter ndis_adapter
;
254 #define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
255 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
257 int rtl_pci_reset_trx_ring(struct ieee80211_hw
*hw
);
259 extern const struct rtl_intf_ops rtl_pci_ops
;
261 int rtl_pci_probe(struct pci_dev
*pdev
,
262 const struct pci_device_id
*id
);
263 void rtl_pci_disconnect(struct pci_dev
*pdev
);
264 #ifdef CONFIG_PM_SLEEP
265 int rtl_pci_suspend(struct device
*dev
);
266 int rtl_pci_resume(struct device
*dev
);
267 #endif /* CONFIG_PM_SLEEP */
268 static inline u8
pci_read8_sync(struct rtl_priv
*rtlpriv
, u32 addr
)
270 return readb((u8 __iomem
*)rtlpriv
->io
.pci_mem_start
+ addr
);
273 static inline u16
pci_read16_sync(struct rtl_priv
*rtlpriv
, u32 addr
)
275 return readw((u8 __iomem
*)rtlpriv
->io
.pci_mem_start
+ addr
);
278 static inline u32
pci_read32_sync(struct rtl_priv
*rtlpriv
, u32 addr
)
280 return readl((u8 __iomem
*)rtlpriv
->io
.pci_mem_start
+ addr
);
283 static inline void pci_write8_async(struct rtl_priv
*rtlpriv
, u32 addr
, u8 val
)
285 writeb(val
, (u8 __iomem
*)rtlpriv
->io
.pci_mem_start
+ addr
);
288 static inline void pci_write16_async(struct rtl_priv
*rtlpriv
,
291 writew(val
, (u8 __iomem
*)rtlpriv
->io
.pci_mem_start
+ addr
);
294 static inline void pci_write32_async(struct rtl_priv
*rtlpriv
,
297 writel(val
, (u8 __iomem
*)rtlpriv
->io
.pci_mem_start
+ addr
);
300 static inline u16
calc_fifo_space(u16 rp
, u16 wp
, u16 size
)
303 return size
- 1 + rp
- wp
;