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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / rtl8821ae / hw.c
blob33ffc24d367595d0ca5de01fb5e2a8cd34431a70
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "dm.h"
15 #include "fw.h"
16 #include "led.h"
17 #include "hw.h"
18 #include "../pwrseqcmd.h"
19 #include "pwrseq.h"
20 #include "../btcoexist/rtl_btc.h"
21
22 #define LLT_CONFIG 5
23
24 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
25 {
26 struct rtl_priv *rtlpriv = rtl_priv(hw);
27 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
28 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
29 unsigned long flags;
30
31 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
32 while (skb_queue_len(&ring->queue)) {
33 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
34 struct sk_buff *skb = __skb_dequeue(&ring->queue);
35
36 dma_unmap_single(&rtlpci->pdev->dev,
37 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
38 true, HW_DESC_TXBUFF_ADDR),
39 skb->len, DMA_TO_DEVICE);
40 kfree_skb(skb);
41 ring->idx = (ring->idx + 1) % ring->entries;
42 }
43 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
44 }
45
46 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
47 u8 set_bits, u8 clear_bits)
48 {
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51
52 rtlpci->reg_bcn_ctrl_val |= set_bits;
53 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
54
55 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
56 }
57
58 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
59 {
60 struct rtl_priv *rtlpriv = rtl_priv(hw);
61 u8 tmp1byte;
62
63 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
64 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
65 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
66 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
67 tmp1byte &= ~(BIT(0));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
69 }
70
71 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
72 {
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 u8 tmp1byte;
75
76 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
77 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
79 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
80 tmp1byte |= BIT(0);
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
82 }
83
84 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
85 {
86 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
87 }
88
89 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
90 {
91 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
92 }
93
94 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
95 u8 rpwm_val, bool b_need_turn_off_ckk)
96 {
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
99 bool b_support_remote_wake_up;
100 u32 count = 0, isr_regaddr, content;
101 bool b_schedule_timer = b_need_turn_off_ckk;
102
103 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
104 (u8 *)(&b_support_remote_wake_up));
105
106 if (!rtlhal->fw_ready)
107 return;
108 if (!rtlpriv->psc.fw_current_inpsmode)
109 return;
110
111 while (1) {
112 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
113 if (rtlhal->fw_clk_change_in_progress) {
114 while (rtlhal->fw_clk_change_in_progress) {
115 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
116 count++;
117 udelay(100);
118 if (count > 1000)
119 goto change_done;
120 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
121 }
122 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
123 } else {
124 rtlhal->fw_clk_change_in_progress = false;
125 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
126 goto change_done;
127 }
128 }
129 change_done:
130 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
131 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
132 (u8 *)(&rpwm_val));
133 if (FW_PS_IS_ACK(rpwm_val)) {
134 isr_regaddr = REG_HISR;
135 content = rtl_read_dword(rtlpriv, isr_regaddr);
136 while (!(content & IMR_CPWM) && (count < 500)) {
137 udelay(50);
138 count++;
139 content = rtl_read_dword(rtlpriv, isr_regaddr);
140 }
141
142 if (content & IMR_CPWM) {
143 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
144 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
145 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
146 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
147 rtlhal->fw_ps_state);
148 }
149 }
150
151 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
152 rtlhal->fw_clk_change_in_progress = false;
153 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
154 if (b_schedule_timer)
155 mod_timer(&rtlpriv->works.fw_clockoff_timer,
156 jiffies + MSECS(10));
157 } else {
158 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
159 rtlhal->fw_clk_change_in_progress = false;
160 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
161 }
162 }
163
164 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
165 u8 rpwm_val)
166 {
167 struct rtl_priv *rtlpriv = rtl_priv(hw);
168 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
169 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
170 struct rtl8192_tx_ring *ring;
171 enum rf_pwrstate rtstate;
172 bool b_schedule_timer = false;
173 u8 queue;
174
175 if (!rtlhal->fw_ready)
176 return;
177 if (!rtlpriv->psc.fw_current_inpsmode)
178 return;
179 if (!rtlhal->allow_sw_to_change_hwclc)
180 return;
181 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
182 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
183 return;
184
185 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
186 ring = &rtlpci->tx_ring[queue];
187 if (skb_queue_len(&ring->queue)) {
188 b_schedule_timer = true;
189 break;
190 }
191 }
192
193 if (b_schedule_timer) {
194 mod_timer(&rtlpriv->works.fw_clockoff_timer,
195 jiffies + MSECS(10));
196 return;
197 }
198
199 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
200 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
201 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
202 if (!rtlhal->fw_clk_change_in_progress) {
203 rtlhal->fw_clk_change_in_progress = true;
204 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
205 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
206 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
207 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
208 (u8 *)(&rpwm_val));
209 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
210 rtlhal->fw_clk_change_in_progress = false;
211 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
212 } else {
213 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
214 mod_timer(&rtlpriv->works.fw_clockoff_timer,
215 jiffies + MSECS(10));
216 }
217 }
218 }
219
220 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
221 {
222 u8 rpwm_val = 0;
223
224 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
225 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
226 }
227
228 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
229 {
230 struct rtl_priv *rtlpriv = rtl_priv(hw);
231 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
232 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
233 bool fw_current_inps = false;
234 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
235
236 if (ppsc->low_power_enable) {
237 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
238 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
239 rtlhal->allow_sw_to_change_hwclc = false;
240 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
241 (u8 *)(&fw_pwrmode));
242 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
243 (u8 *)(&fw_current_inps));
244 } else {
245 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
246 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
247 (u8 *)(&rpwm_val));
248 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
249 (u8 *)(&fw_pwrmode));
250 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
251 (u8 *)(&fw_current_inps));
252 }
253 }
254
255 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
256 {
257 struct rtl_priv *rtlpriv = rtl_priv(hw);
258 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
259 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
260 bool fw_current_inps = true;
261 u8 rpwm_val;
262
263 if (ppsc->low_power_enable) {
264 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
265 rtlpriv->cfg->ops->set_hw_reg(hw,
266 HW_VAR_FW_PSMODE_STATUS,
267 (u8 *)(&fw_current_inps));
268 rtlpriv->cfg->ops->set_hw_reg(hw,
269 HW_VAR_H2C_FW_PWRMODE,
270 (u8 *)(&ppsc->fwctrl_psmode));
271 rtlhal->allow_sw_to_change_hwclc = true;
272 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
273 } else {
274 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
275 rtlpriv->cfg->ops->set_hw_reg(hw,
276 HW_VAR_FW_PSMODE_STATUS,
277 (u8 *)(&fw_current_inps));
278 rtlpriv->cfg->ops->set_hw_reg(hw,
279 HW_VAR_H2C_FW_PWRMODE,
280 (u8 *)(&ppsc->fwctrl_psmode));
281 rtlpriv->cfg->ops->set_hw_reg(hw,
282 HW_VAR_SET_RPWM,
283 (u8 *)(&rpwm_val));
284 }
285 }
286
287 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
288 bool dl_whole_packets)
289 {
290 struct rtl_priv *rtlpriv = rtl_priv(hw);
291 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
292 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
293 u8 count = 0, dlbcn_count = 0;
294 bool send_beacon = false;
295
296 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
297 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
298
299 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
300 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
301
302 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
303 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
304 tmp_reg422 & (~BIT(6)));
305 if (tmp_reg422 & BIT(6))
306 send_beacon = true;
307
308 do {
309 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
310 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
311 (bcnvalid_reg | BIT(0)));
312 _rtl8821ae_return_beacon_queue_skb(hw);
313
314 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
315 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
316 dl_whole_packets);
317 else
318 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
319 dl_whole_packets);
320
321 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
322 count = 0;
323 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
324 count++;
325 udelay(10);
326 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
327 }
328 dlbcn_count++;
329 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
330
331 if (!(bcnvalid_reg & BIT(0)))
332 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
333 "Download RSVD page failed!\n");
334 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
335 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
336 _rtl8821ae_return_beacon_queue_skb(hw);
337 if (send_beacon) {
338 dlbcn_count = 0;
339 do {
340 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
341 bcnvalid_reg | BIT(0));
342
343 _rtl8821ae_return_beacon_queue_skb(hw);
344
345 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
346 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
347 false);
348 else
349 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
350 false);
351
352 /* check rsvd page download OK. */
353 bcnvalid_reg = rtl_read_byte(rtlpriv,
354 REG_TDECTRL + 2);
355 count = 0;
356 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
357 count++;
358 udelay(10);
359 bcnvalid_reg =
360 rtl_read_byte(rtlpriv,
361 REG_TDECTRL + 2);
362 }
363 dlbcn_count++;
364 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
365
366 if (!(bcnvalid_reg & BIT(0)))
367 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
368 "2 Download RSVD page failed!\n");
369 }
370 }
371
372 if (bcnvalid_reg & BIT(0))
373 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
374
375 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
376 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
377
378 if (send_beacon)
379 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
380
381 if (!rtlhal->enter_pnp_sleep) {
382 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
383 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
384 }
385 }
386
387 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
388 {
389 struct rtl_priv *rtlpriv = rtl_priv(hw);
390 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
391 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
392 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
393
394 switch (variable) {
395 case HW_VAR_ETHER_ADDR:
396 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
397 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
398 break;
399 case HW_VAR_BSSID:
400 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
401 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
402 break;
403 case HW_VAR_MEDIA_STATUS:
404 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
405 break;
406 case HW_VAR_SLOT_TIME:
407 *((u8 *)(val)) = mac->slot_time;
408 break;
409 case HW_VAR_BEACON_INTERVAL:
410 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
411 break;
412 case HW_VAR_ATIM_WINDOW:
413 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
414 break;
415 case HW_VAR_RCR:
416 *((u32 *)(val)) = rtlpci->receive_config;
417 break;
418 case HW_VAR_RF_STATE:
419 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
420 break;
421 case HW_VAR_FWLPS_RF_ON:{
422 enum rf_pwrstate rfstate;
423 u32 val_rcr;
424
425 rtlpriv->cfg->ops->get_hw_reg(hw,
426 HW_VAR_RF_STATE,
427 (u8 *)(&rfstate));
428 if (rfstate == ERFOFF) {
429 *((bool *)(val)) = true;
430 } else {
431 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
432 val_rcr &= 0x00070000;
433 if (val_rcr)
434 *((bool *)(val)) = false;
435 else
436 *((bool *)(val)) = true;
437 }
438 break; }
439 case HW_VAR_FW_PSMODE_STATUS:
440 *((bool *)(val)) = ppsc->fw_current_inpsmode;
441 break;
442 case HW_VAR_CORRECT_TSF:{
443 u64 tsf;
444 u32 *ptsf_low = (u32 *)&tsf;
445 u32 *ptsf_high = ((u32 *)&tsf) + 1;
446
447 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
448 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
449
450 *((u64 *)(val)) = tsf;
451
452 break; }
453 case HAL_DEF_WOWLAN:
454 if (ppsc->wo_wlan_mode)
455 *((bool *)(val)) = true;
456 else
457 *((bool *)(val)) = false;
458 break;
459 default:
460 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
461 "switch case %#x not processed\n", variable);
462 break;
463 }
464 }
465
466 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
467 {
468 struct rtl_priv *rtlpriv = rtl_priv(hw);
469 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
471 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
472 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
473 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
474 u8 idx;
475
476 switch (variable) {
477 case HW_VAR_ETHER_ADDR:{
478 for (idx = 0; idx < ETH_ALEN; idx++) {
479 rtl_write_byte(rtlpriv, (REG_MACID + idx),
480 val[idx]);
481 }
482 break;
483 }
484 case HW_VAR_BASIC_RATE:{
485 u16 b_rate_cfg = ((u16 *)val)[0];
486 b_rate_cfg = b_rate_cfg & 0x15f;
487 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
488 break;
489 }
490 case HW_VAR_BSSID:{
491 for (idx = 0; idx < ETH_ALEN; idx++) {
492 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
493 val[idx]);
494 }
495 break;
496 }
497 case HW_VAR_SIFS:
498 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
499 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
500
501 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
502 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
503
504 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
505 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
506 break;
507 case HW_VAR_R2T_SIFS:
508 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
509 break;
510 case HW_VAR_SLOT_TIME:{
511 u8 e_aci;
512
513 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
514 "HW_VAR_SLOT_TIME %x\n", val[0]);
515
516 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
517
518 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
519 rtlpriv->cfg->ops->set_hw_reg(hw,
520 HW_VAR_AC_PARAM,
521 (u8 *)(&e_aci));
522 }
523 break; }
524 case HW_VAR_ACK_PREAMBLE:{
525 u8 reg_tmp;
526 u8 short_preamble = (bool)(*(u8 *)val);
527
528 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
529 if (short_preamble) {
530 reg_tmp |= BIT(1);
531 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
532 reg_tmp);
533 } else {
534 reg_tmp &= (~BIT(1));
535 rtl_write_byte(rtlpriv,
536 REG_TRXPTCL_CTL + 2,
537 reg_tmp);
538 }
539 break; }
540 case HW_VAR_WPA_CONFIG:
541 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
542 break;
543 case HW_VAR_AMPDU_MIN_SPACE:{
544 u8 min_spacing_to_set;
545 u8 sec_min_space;
546
547 min_spacing_to_set = *((u8 *)val);
548 if (min_spacing_to_set <= 7) {
549 sec_min_space = 0;
550
551 if (min_spacing_to_set < sec_min_space)
552 min_spacing_to_set = sec_min_space;
553
554 mac->min_space_cfg = ((mac->min_space_cfg &
555 0xf8) |
556 min_spacing_to_set);
557
558 *val = min_spacing_to_set;
559
560 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
561 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
562 mac->min_space_cfg);
563
564 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
565 mac->min_space_cfg);
566 }
567 break; }
568 case HW_VAR_SHORTGI_DENSITY:{
569 u8 density_to_set;
570
571 density_to_set = *((u8 *)val);
572 mac->min_space_cfg |= (density_to_set << 3);
573
574 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
575 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
576 mac->min_space_cfg);
577
578 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
579 mac->min_space_cfg);
580
581 break; }
582 case HW_VAR_AMPDU_FACTOR:{
583 u32 ampdu_len = (*((u8 *)val));
584
585 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
586 if (ampdu_len < VHT_AGG_SIZE_128K)
587 ampdu_len =
588 (0x2000 << (*((u8 *)val))) - 1;
589 else
590 ampdu_len = 0x1ffff;
591 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
592 if (ampdu_len < HT_AGG_SIZE_64K)
593 ampdu_len =
594 (0x2000 << (*((u8 *)val))) - 1;
595 else
596 ampdu_len = 0xffff;
597 }
598 ampdu_len |= BIT(31);
599
600 rtl_write_dword(rtlpriv,
601 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
602 break; }
603 case HW_VAR_AC_PARAM:{
604 u8 e_aci = *((u8 *)val);
605
606 rtl8821ae_dm_init_edca_turbo(hw);
607 if (rtlpci->acm_method != EACMWAY2_SW)
608 rtlpriv->cfg->ops->set_hw_reg(hw,
609 HW_VAR_ACM_CTRL,
610 (u8 *)(&e_aci));
611 break; }
612 case HW_VAR_ACM_CTRL:{
613 u8 e_aci = *((u8 *)val);
614 union aci_aifsn *p_aci_aifsn =
615 (union aci_aifsn *)(&mac->ac[0].aifs);
616 u8 acm = p_aci_aifsn->f.acm;
617 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
618
619 acm_ctrl =
620 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
621
622 if (acm) {
623 switch (e_aci) {
624 case AC0_BE:
625 acm_ctrl |= ACMHW_BEQEN;
626 break;
627 case AC2_VI:
628 acm_ctrl |= ACMHW_VIQEN;
629 break;
630 case AC3_VO:
631 acm_ctrl |= ACMHW_VOQEN;
632 break;
633 default:
634 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
635 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
636 acm);
637 break;
638 }
639 } else {
640 switch (e_aci) {
641 case AC0_BE:
642 acm_ctrl &= (~ACMHW_BEQEN);
643 break;
644 case AC2_VI:
645 acm_ctrl &= (~ACMHW_VIQEN);
646 break;
647 case AC3_VO:
648 acm_ctrl &= (~ACMHW_VOQEN);
649 break;
650 default:
651 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
652 "switch case %#x not processed\n",
653 e_aci);
654 break;
655 }
656 }
657
658 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
659 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
660 acm_ctrl);
661 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
662 break; }
663 case HW_VAR_RCR:
664 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
665 rtlpci->receive_config = ((u32 *)(val))[0];
666 break;
667 case HW_VAR_RETRY_LIMIT:{
668 u8 retry_limit = ((u8 *)(val))[0];
669
670 rtl_write_word(rtlpriv, REG_RL,
671 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
672 retry_limit << RETRY_LIMIT_LONG_SHIFT);
673 break; }
674 case HW_VAR_DUAL_TSF_RST:
675 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
676 break;
677 case HW_VAR_EFUSE_BYTES:
678 rtlefuse->efuse_usedbytes = *((u16 *)val);
679 break;
680 case HW_VAR_EFUSE_USAGE:
681 rtlefuse->efuse_usedpercentage = *((u8 *)val);
682 break;
683 case HW_VAR_IO_CMD:
684 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
685 break;
686 case HW_VAR_SET_RPWM:{
687 u8 rpwm_val;
688
689 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
690 udelay(1);
691
692 if (rpwm_val & BIT(7)) {
693 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
694 (*(u8 *)val));
695 } else {
696 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
697 ((*(u8 *)val) | BIT(7)));
698 }
699
700 break; }
701 case HW_VAR_H2C_FW_PWRMODE:
702 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
703 break;
704 case HW_VAR_FW_PSMODE_STATUS:
705 ppsc->fw_current_inpsmode = *((bool *)val);
706 break;
707 case HW_VAR_INIT_RTS_RATE:
708 break;
709 case HW_VAR_RESUME_CLK_ON:
710 _rtl8821ae_set_fw_ps_rf_on(hw);
711 break;
712 case HW_VAR_FW_LPS_ACTION:{
713 bool b_enter_fwlps = *((bool *)val);
714
715 if (b_enter_fwlps)
716 _rtl8821ae_fwlps_enter(hw);
717 else
718 _rtl8821ae_fwlps_leave(hw);
719 break; }
720 case HW_VAR_H2C_FW_JOINBSSRPT:{
721 u8 mstatus = (*(u8 *)val);
722
723 if (mstatus == RT_MEDIA_CONNECT) {
724 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
725 NULL);
726 _rtl8821ae_download_rsvd_page(hw, false);
727 }
728 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
729
730 break; }
731 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
732 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
733 break;
734 case HW_VAR_AID:{
735 u16 u2btmp;
736 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
737 u2btmp &= 0xC000;
738 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
739 mac->assoc_id));
740 break; }
741 case HW_VAR_CORRECT_TSF:{
742 u8 btype_ibss = ((u8 *)(val))[0];
743
744 if (btype_ibss)
745 _rtl8821ae_stop_tx_beacon(hw);
746
747 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
748
749 rtl_write_dword(rtlpriv, REG_TSFTR,
750 (u32)(mac->tsf & 0xffffffff));
751 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
752 (u32)((mac->tsf >> 32) & 0xffffffff));
753
754 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
755
756 if (btype_ibss)
757 _rtl8821ae_resume_tx_beacon(hw);
758 break; }
759 case HW_VAR_NAV_UPPER: {
760 u32 us_nav_upper = *(u32 *)val;
761
762 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
763 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
764 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
765 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
766 break;
767 }
768 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
769 ((u8)((us_nav_upper +
770 HAL_92C_NAV_UPPER_UNIT - 1) /
771 HAL_92C_NAV_UPPER_UNIT)));
772 break; }
773 case HW_VAR_KEEP_ALIVE: {
774 u8 array[2];
775 array[0] = 0xff;
776 array[1] = *((u8 *)val);
777 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
778 array);
779 break; }
780 default:
781 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
782 "switch case %#x not processed\n", variable);
783 break;
784 }
785 }
786
787 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
788 {
789 struct rtl_priv *rtlpriv = rtl_priv(hw);
790 bool status = true;
791 long count = 0;
792 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
793 _LLT_OP(_LLT_WRITE_ACCESS);
794
795 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
796
797 do {
798 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
799 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
800 break;
801
802 if (count > POLLING_LLT_THRESHOLD) {
803 pr_err("Failed to polling write LLT done at address %d!\n",
804 address);
805 status = false;
806 break;
807 }
808 } while (++count);
809
810 return status;
811 }
812
813 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
814 {
815 struct rtl_priv *rtlpriv = rtl_priv(hw);
816 unsigned short i;
817 u8 txpktbuf_bndy;
818 u32 rqpn;
819 u8 maxpage;
820 bool status;
821
822 maxpage = 255;
823 txpktbuf_bndy = 0xF7;
824 rqpn = 0x80e60808;
825
826 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
827 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
828
829 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
830
831 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
832 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
833
834 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
835 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
836
837 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
838 status = _rtl8821ae_llt_write(hw, i, i + 1);
839 if (!status)
840 return status;
841 }
842
843 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
844 if (!status)
845 return status;
846
847 for (i = txpktbuf_bndy; i < maxpage; i++) {
848 status = _rtl8821ae_llt_write(hw, i, (i + 1));
849 if (!status)
850 return status;
851 }
852
853 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
854 if (!status)
855 return status;
856
857 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
858
859 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
860
861 return true;
862 }
863
864 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
865 {
866 struct rtl_priv *rtlpriv = rtl_priv(hw);
867 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
868 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
869 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
870
871 if (rtlpriv->rtlhal.up_first_time)
872 return;
873
874 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
875 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
876 rtl8812ae_sw_led_on(hw, pled0);
877 else
878 rtl8821ae_sw_led_on(hw, pled0);
879 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
880 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
881 rtl8812ae_sw_led_on(hw, pled0);
882 else
883 rtl8821ae_sw_led_on(hw, pled0);
884 else
885 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
886 rtl8812ae_sw_led_off(hw, pled0);
887 else
888 rtl8821ae_sw_led_off(hw, pled0);
889 }
890
891 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
892 {
893 struct rtl_priv *rtlpriv = rtl_priv(hw);
894 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
895 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
896
897 u8 bytetmp = 0;
898 u16 wordtmp = 0;
899 bool mac_func_enable = rtlhal->mac_func_enable;
900
901 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
902
903 /*Auto Power Down to CHIP-off State*/
904 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
905 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
906
907 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
908 /* HW Power on sequence*/
909 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
910 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
911 RTL8812_NIC_ENABLE_FLOW)) {
912 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
913 "init 8812 MAC Fail as power on failure\n");
914 return false;
915 }
916 } else {
917 /* HW Power on sequence */
918 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
919 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
920 RTL8821A_NIC_ENABLE_FLOW)){
921 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
922 "init 8821 MAC Fail as power on failure\n");
923 return false;
924 }
925 }
926
927 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
928 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
929
930 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
931 bytetmp = 0xff;
932 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
933 mdelay(2);
934
935 bytetmp = 0xff;
936 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
937 mdelay(2);
938
939 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
940 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
941 if (bytetmp & BIT(0)) {
942 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
943 bytetmp |= BIT(6);
944 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
945 }
946 }
947
948 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
949 bytetmp &= ~BIT(4);
950 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
951
952 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
953
954 if (!mac_func_enable) {
955 if (!_rtl8821ae_llt_table_init(hw))
956 return false;
957 }
958
959 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
960 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
961
962 /* Enable FW Beamformer Interrupt */
963 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
964 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
965
966 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
967 wordtmp &= 0xf;
968 wordtmp |= 0xF5B1;
969 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
970
971 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
972 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
973 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
974 /*low address*/
975 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
976 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
977 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
978 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
979 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
980 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
981 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
982 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
983 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
984 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
985 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
986 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
987 rtl_write_dword(rtlpriv, REG_HQ_DESA,
988 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
989 rtl_write_dword(rtlpriv, REG_RX_DESA,
990 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
991
992 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
993
994 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
995
996 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
997
998 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
999 _rtl8821ae_gen_refresh_led_state(hw);
1000
1001 return true;
1002 }
1003
1004 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1005 {
1006 struct rtl_priv *rtlpriv = rtl_priv(hw);
1007 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1008 u32 reg_rrsr;
1009
1010 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1011
1012 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1013 /* ARFB table 9 for 11ac 5G 2SS */
1014 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1015 /* ARFB table 10 for 11ac 5G 1SS */
1016 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1017 /* ARFB table 11 for 11ac 24G 1SS */
1018 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1019 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1020 /* ARFB table 12 for 11ac 24G 1SS */
1021 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1022 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1023 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1024 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1025 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1026
1027 /*Set retry limit*/
1028 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1029
1030 /* Set Data / Response auto rate fallack retry count*/
1031 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1032 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1033 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1034 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1035
1036 rtlpci->reg_bcn_ctrl_val = 0x1d;
1037 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1038
1039 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1040 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1041
1042 /* AGGR_BK_TIME Reg51A 0x16 */
1043 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1044
1045 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1046 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1047
1048 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1049 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1050 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1051 }
1052
1053 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1054 {
1055 u16 ret = 0;
1056 u8 tmp = 0, count = 0;
1057
1058 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1059 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1060 count = 0;
1061 while (tmp && count < 20) {
1062 udelay(10);
1063 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1064 count++;
1065 }
1066 if (0 == tmp)
1067 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1068
1069 return ret;
1070 }
1071
1072 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1073 {
1074 u8 tmp = 0, count = 0;
1075
1076 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1077 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1078 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1079 count = 0;
1080 while (tmp && count < 20) {
1081 udelay(10);
1082 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1083 count++;
1084 }
1085 }
1086
1087 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1088 {
1089 u16 read_addr = addr & 0xfffc;
1090 u8 tmp = 0, count = 0, ret = 0;
1091
1092 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1093 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1094 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1095 count = 0;
1096 while (tmp && count < 20) {
1097 udelay(10);
1098 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1099 count++;
1100 }
1101 if (0 == tmp) {
1102 read_addr = REG_DBI_RDATA + addr % 4;
1103 ret = rtl_read_byte(rtlpriv, read_addr);
1104 }
1105 return ret;
1106 }
1107
1108 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1109 {
1110 u8 tmp = 0, count = 0;
1111 u16 write_addr, remainder = addr % 4;
1112
1113 write_addr = REG_DBI_WDATA + remainder;
1114 rtl_write_byte(rtlpriv, write_addr, data);
1115
1116 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1117 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1118
1119 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1120
1121 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1122 count = 0;
1123 while (tmp && count < 20) {
1124 udelay(10);
1125 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1126 count++;
1127 }
1128 }
1129
1130 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1131 {
1132 struct rtl_priv *rtlpriv = rtl_priv(hw);
1133 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1134 u8 tmp;
1135
1136 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1137 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1138 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1139
1140 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1141 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1142 }
1143
1144 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1145 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1146 ASPM_L1_LATENCY << 3);
1147
1148 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1149 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1150
1151 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1152 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1153 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1154 }
1155 }
1156
1157 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1158 {
1159 struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 u8 sec_reg_value;
1161 u8 tmp;
1162
1163 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1164 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1165 rtlpriv->sec.pairwise_enc_algorithm,
1166 rtlpriv->sec.group_enc_algorithm);
1167
1168 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1169 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1170 "not open hw encryption\n");
1171 return;
1172 }
1173
1174 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1175
1176 if (rtlpriv->sec.use_defaultkey) {
1177 sec_reg_value |= SCR_TXUSEDK;
1178 sec_reg_value |= SCR_RXUSEDK;
1179 }
1180
1181 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1182
1183 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1184 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1185
1186 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1187 "The SECR-value %x\n", sec_reg_value);
1188
1189 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1190 }
1191
1192 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1193 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1194 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1195 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1196 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1197 /* ----------------------------------------------------------- */
1198
1199 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1200 {
1201 struct rtl_priv *rtlpriv = rtl_priv(hw);
1202 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1203 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1204 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1205
1206 rtlpriv->cfg->ops->set_hw_reg(hw,
1207 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1208
1209 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1210 "Initialize MacId media status: from %d to %d\n",
1211 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1212 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1213 }
1214
1215 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1216 {
1217 struct rtl_priv *rtlpriv = rtl_priv(hw);
1218 u8 tmp;
1219
1220 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1221 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1222 if (!(tmp & BIT(2))) {
1223 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1224 mdelay(100);
1225 }
1226
1227 /* read reg 0x350 Bit[25] if 1 : RX hang */
1228 /* read reg 0x350 Bit[24] if 1 : TX hang */
1229 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1230 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1231 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1232 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1233 return true;
1234 } else {
1235 return false;
1236 }
1237 }
1238
1239 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1240 bool mac_power_on,
1241 bool in_watchdog)
1242 {
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1245 u8 tmp;
1246 bool release_mac_rx_pause;
1247 u8 backup_pcie_dma_pause;
1248
1249 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1250
1251 /* 1. Disable register write lock. 0x1c[1] = 0 */
1252 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1253 tmp &= ~(BIT(1));
1254 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1255 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1256 /* write 0xCC bit[2] = 1'b1 */
1257 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1258 tmp |= BIT(2);
1259 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1260 }
1261
1262 /* 2. Check and pause TRX DMA */
1263 /* write 0x284 bit[18] = 1'b1 */
1264 /* write 0x301 = 0xFF */
1265 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1266 if (tmp & BIT(2)) {
1267 /* Already pause before the function for another purpose. */
1268 release_mac_rx_pause = false;
1269 } else {
1270 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1271 release_mac_rx_pause = true;
1272 }
1273 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1274 if (backup_pcie_dma_pause != 0xFF)
1275 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1276
1277 if (mac_power_on) {
1278 /* 3. reset TRX function */
1279 /* write 0x100 = 0x00 */
1280 rtl_write_byte(rtlpriv, REG_CR, 0);
1281 }
1282
1283 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1284 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1285 tmp &= ~(BIT(0));
1286 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1287
1288 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1289 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1290 tmp |= BIT(0);
1291 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1292
1293 if (mac_power_on) {
1294 /* 6. enable TRX function */
1295 /* write 0x100 = 0xFF */
1296 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1297
1298 /* We should init LLT & RQPN and
1299 * prepare Tx/Rx descrptor address later
1300 * because MAC function is reset.*/
1301 }
1302
1303 /* 7. Restore PCIe autoload down bit */
1304 /* 8812AE does not has the defination. */
1305 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1306 /* write 0xF8 bit[17] = 1'b1 */
1307 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1308 tmp |= BIT(1);
1309 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1310 }
1311
1312 /* In MAC power on state, BB and RF maybe in ON state,
1313 * if we release TRx DMA here.
1314 * it will cause packets to be started to Tx/Rx,
1315 * so we release Tx/Rx DMA later.*/
1316 if (!mac_power_on/* || in_watchdog*/) {
1317 /* 8. release TRX DMA */
1318 /* write 0x284 bit[18] = 1'b0 */
1319 /* write 0x301 = 0x00 */
1320 if (release_mac_rx_pause) {
1321 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1322 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1323 tmp & (~BIT(2)));
1324 }
1325 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1326 backup_pcie_dma_pause);
1327 }
1328
1329 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1330 /* 9. lock system register */
1331 /* write 0xCC bit[2] = 1'b0 */
1332 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1333 tmp &= ~(BIT(2));
1334 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1335 }
1336 return true;
1337 }
1338
1339 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1340 {
1341 struct rtl_priv *rtlpriv = rtl_priv(hw);
1342 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1343 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1344 u8 fw_reason = 0;
1345
1346 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1347
1348 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1349 fw_reason);
1350
1351 ppsc->wakeup_reason = 0;
1352
1353 rtlhal->last_suspend_sec = ktime_get_real_seconds();
1354
1355 switch (fw_reason) {
1356 case FW_WOW_V2_PTK_UPDATE_EVENT:
1357 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1358 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1359 "It's a WOL PTK Key update event!\n");
1360 break;
1361 case FW_WOW_V2_GTK_UPDATE_EVENT:
1362 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1363 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1364 "It's a WOL GTK Key update event!\n");
1365 break;
1366 case FW_WOW_V2_DISASSOC_EVENT:
1367 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1368 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1369 "It's a disassociation event!\n");
1370 break;
1371 case FW_WOW_V2_DEAUTH_EVENT:
1372 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1373 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1374 "It's a deauth event!\n");
1375 break;
1376 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1377 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1378 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1379 "It's a Fw disconnect decision (AP lost) event!\n");
1380 break;
1381 case FW_WOW_V2_MAGIC_PKT_EVENT:
1382 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1383 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1384 "It's a magic packet event!\n");
1385 break;
1386 case FW_WOW_V2_UNICAST_PKT_EVENT:
1387 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1388 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1389 "It's an unicast packet event!\n");
1390 break;
1391 case FW_WOW_V2_PATTERN_PKT_EVENT:
1392 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1393 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1394 "It's a pattern match event!\n");
1395 break;
1396 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1397 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1398 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1399 "It's an RTD3 Ssid match event!\n");
1400 break;
1401 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1402 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1403 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1404 "It's an RealWoW wake packet event!\n");
1405 break;
1406 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1407 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1408 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1409 "It's an RealWoW ack lost event!\n");
1410 break;
1411 default:
1412 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1413 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1414 fw_reason);
1415 break;
1416 }
1417 }
1418
1419 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1420 {
1421 struct rtl_priv *rtlpriv = rtl_priv(hw);
1422 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1423
1424 /*low address*/
1425 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1426 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1427 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1428 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1429 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1430 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1431 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1432 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1433 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1434 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1435 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1436 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1437 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1438 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1439 rtl_write_dword(rtlpriv, REG_RX_DESA,
1440 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1441 }
1442
1443 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1444 {
1445 bool status = true;
1446 u32 i;
1447 u32 txpktbuf_bndy = boundary;
1448 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1449
1450 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1451 status = _rtl8821ae_llt_write(hw, i , i + 1);
1452 if (!status)
1453 return status;
1454 }
1455
1456 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1457 if (!status)
1458 return status;
1459
1460 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1461 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1462 if (!status)
1463 return status;
1464 }
1465
1466 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1467 txpktbuf_bndy);
1468 if (!status)
1469 return status;
1470
1471 return status;
1472 }
1473
1474 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1475 u16 npq_rqpn_value, u32 rqpn_val)
1476 {
1477 struct rtl_priv *rtlpriv = rtl_priv(hw);
1478 u8 tmp;
1479 bool ret = true;
1480 u16 count = 0, tmp16;
1481 bool support_remote_wakeup;
1482
1483 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1484 (u8 *)(&support_remote_wakeup));
1485
1486 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1487 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1488 boundary, npq_rqpn_value, rqpn_val);
1489
1490 /* stop PCIe DMA
1491 * 1. 0x301[7:0] = 0xFE */
1492 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1493
1494 /* wait TXFF empty
1495 * 2. polling till 0x41A[15:0]=0x07FF */
1496 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1497 while ((tmp16 & 0x07FF) != 0x07FF) {
1498 udelay(100);
1499 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1500 count++;
1501 if ((count % 200) == 0) {
1502 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1503 "Tx queue is not empty for 20ms!\n");
1504 }
1505 if (count >= 1000) {
1506 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1507 "Wait for Tx FIFO empty timeout!\n");
1508 break;
1509 }
1510 }
1511
1512 /* TX pause
1513 * 3. reg 0x522=0xFF */
1514 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1515
1516 /* Wait TX State Machine OK
1517 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1518 count = 0;
1519 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1520 udelay(100);
1521 count++;
1522 if (count >= 500) {
1523 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1524 "Wait for TX State Machine ready timeout !!\n");
1525 break;
1526 }
1527 }
1528
1529 /* stop RX DMA path
1530 * 5. 0x284[18] = 1
1531 * 6. wait till 0x284[17] == 1
1532 * wait RX DMA idle */
1533 count = 0;
1534 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1535 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1536 do {
1537 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1538 udelay(10);
1539 count++;
1540 } while (!(tmp & BIT(1)) && count < 100);
1541
1542 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1543 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1544 count, tmp);
1545
1546 /* reset BB
1547 * 7. 0x02 [0] = 0 */
1548 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1549 tmp &= ~(BIT(0));
1550 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1551
1552 /* Reset TRX MAC
1553 * 8. 0x100 = 0x00
1554 * Delay (1ms) */
1555 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1556 udelay(1000);
1557
1558 /* Disable MAC Security Engine
1559 * 9. 0x100 bit[9]=0 */
1560 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1561 tmp &= ~(BIT(1));
1562 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1563
1564 /* To avoid DD-Tim Circuit hang
1565 * 10. 0x553 bit[5]=1 */
1566 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1567 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1568
1569 /* Enable MAC Security Engine
1570 * 11. 0x100 bit[9]=1 */
1571 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1572 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1573
1574 /* Enable TRX MAC
1575 * 12. 0x100 = 0xFF
1576 * Delay (1ms) */
1577 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1578 udelay(1000);
1579
1580 /* Enable BB
1581 * 13. 0x02 [0] = 1 */
1582 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1583 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1584
1585 /* beacon setting
1586 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1587 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1588 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1589 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1590
1591 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1592 * WMAC_LBK_BF_HD */
1593 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1594 (u8)boundary);
1595
1596 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1597
1598 /* init LLT
1599 * 17. init LLT */
1600 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1601 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
1602 "Failed to init LLT table!\n");
1603 return false;
1604 }
1605
1606 /* reallocate RQPN
1607 * 18. reallocate RQPN and init LLT */
1608 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1609 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1610
1611 /* release Tx pause
1612 * 19. 0x522=0x00 */
1613 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1614
1615 /* enable PCIE DMA
1616 * 20. 0x301[7:0] = 0x00
1617 * 21. 0x284[18] = 0 */
1618 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1619 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1620 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1621
1622 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1623 return ret;
1624 }
1625
1626 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1627 {
1628 struct rtl_priv *rtlpriv = rtl_priv(hw);
1629 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1630 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1631
1632 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1633 /* Re-download normal Fw. */
1634 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1635 #endif
1636
1637 /* Re-Initialize LLT table. */
1638 if (rtlhal->re_init_llt_table) {
1639 u32 rqpn = 0x80e70808;
1640 u8 rqpn_npq = 0, boundary = 0xF8;
1641 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1642 rqpn = 0x80e90808;
1643 boundary = 0xFA;
1644 }
1645 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1646 rtlhal->re_init_llt_table = false;
1647 }
1648
1649 ppsc->rfpwr_state = ERFON;
1650 }
1651
1652 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1653 {
1654 u8 tmp = 0;
1655 struct rtl_priv *rtlpriv = rtl_priv(hw);
1656
1657 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1658
1659 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1660 if (!(tmp & (BIT(2) | BIT(3)))) {
1661 rtl_dbg(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1662 "0x160(%#x)return!!\n", tmp);
1663 return;
1664 }
1665
1666 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1667 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1668
1669 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1670 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1671
1672 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1673 }
1674
1675 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1676 {
1677 u8 tmp = 0;
1678 struct rtl_priv *rtlpriv = rtl_priv(hw);
1679
1680 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1681
1682 /* Check 0x98[10] */
1683 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1684 if (!(tmp & BIT(2))) {
1685 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1686 "<---0x99(%#x) return!!\n", tmp);
1687 return;
1688 }
1689
1690 /* LTR idle latency, 0x90 for 144us */
1691 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1692
1693 /* LTR active latency, 0x3c for 60us */
1694 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1695
1696 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1697 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1698
1699 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1700 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1701 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1702
1703 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1704 }
1705
1706 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1707 {
1708 struct rtl_priv *rtlpriv = rtl_priv(hw);
1709 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1710 bool init_finished = true;
1711 u8 tmp = 0;
1712
1713 /* Get Fw wake up reason. */
1714 _rtl8821ae_get_wakeup_reason(hw);
1715
1716 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1717 * The root cause has not be found. */
1718 if (_rtl8821ae_check_pcie_dma_hang(hw))
1719 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1720
1721 /* Prepare Tx/Rx Desc Hw address. */
1722 _rtl8821ae_init_trx_desc_hw_address(hw);
1723
1724 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1725 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1726 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1727
1728 /* Check wake up event.
1729 * We should check wake packet bit before disable wowlan by H2C or
1730 * Fw will clear the bit. */
1731 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1732 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1733 "Read REG_FTISR 0x13f = %#X\n", tmp);
1734
1735 /* Set the WoWLAN related function control disable. */
1736 rtl8821ae_set_fw_wowlan_mode(hw, false);
1737 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1738
1739 if (rtlhal->hw_rof_enable) {
1740 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1741 if (tmp & BIT(1)) {
1742 /* Clear GPIO9 ISR */
1743 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1744 init_finished = false;
1745 } else {
1746 init_finished = true;
1747 }
1748 }
1749
1750 if (init_finished) {
1751 _rtl8821ae_simple_initialize_adapter(hw);
1752
1753 /* Release Pcie Interface Tx DMA. */
1754 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1755 /* Release Pcie RX DMA */
1756 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1757
1758 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1759 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1760
1761 _rtl8821ae_enable_l1off(hw);
1762 _rtl8821ae_enable_ltr(hw);
1763 }
1764
1765 return init_finished;
1766 }
1767
1768 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1769 {
1770 /* BB OFDM RX Path_A */
1771 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1772 /* BB OFDM TX Path_A */
1773 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1774 /* BB CCK R/Rx Path_A */
1775 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1776 /* MCS support */
1777 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1778 /* RF Path_B HSSI OFF */
1779 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1780 /* RF Path_B Power Down */
1781 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1782 /* ADDA Path_B OFF */
1783 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1784 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1785 }
1786
1787 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1788 {
1789 struct rtl_priv *rtlpriv = rtl_priv(hw);
1790 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1791 u8 u1b_tmp;
1792
1793 rtlhal->mac_func_enable = false;
1794
1795 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1796 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1797 /* 1. Run LPS WL RFOFF flow */
1798 /* rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1799 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1800 */
1801 rtl_hal_pwrseqcmdparsing(rtlpriv,
1802 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1803 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1804 }
1805 /* 2. 0x1F[7:0] = 0 */
1806 /* turn off RF */
1807 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1808 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1809 rtlhal->fw_ready) {
1810 rtl8821ae_firmware_selfreset(hw);
1811 }
1812
1813 /* Reset MCU. Suggested by Filen. */
1814 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1815 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1816
1817 /* g. MCUFWDL 0x80[1:0]=0 */
1818 /* reset MCU ready status */
1819 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1820
1821 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1822 /* HW card disable configuration. */
1823 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1824 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1825 } else {
1826 /* HW card disable configuration. */
1827 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1828 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1829 }
1830
1831 /* Reset MCU IO Wrapper */
1832 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1833 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1834 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1835 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1836
1837 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1838 /* lock ISO/CLK/Power control register */
1839 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1840 }
1841
1842 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1843 {
1844 struct rtl_priv *rtlpriv = rtl_priv(hw);
1845 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1846 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1847 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1848 bool rtstatus = true;
1849 int err;
1850 u8 tmp_u1b;
1851 bool support_remote_wakeup;
1852 u32 nav_upper = WIFI_NAV_UPPER_US;
1853
1854 rtlhal->being_init_adapter = true;
1855 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1856 (u8 *)(&support_remote_wakeup));
1857 rtlpriv->intf_ops->disable_aspm(hw);
1858
1859 /*YP wowlan not considered*/
1860
1861 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1862 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1863 rtlhal->mac_func_enable = true;
1864 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1865 "MAC has already power on.\n");
1866 } else {
1867 rtlhal->mac_func_enable = false;
1868 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1869 }
1870
1871 if (support_remote_wakeup &&
1872 rtlhal->wake_from_pnp_sleep &&
1873 rtlhal->mac_func_enable) {
1874 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1875 rtlhal->being_init_adapter = false;
1876 return 0;
1877 }
1878 }
1879
1880 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1881 _rtl8821ae_reset_pcie_interface_dma(hw,
1882 rtlhal->mac_func_enable,
1883 false);
1884 rtlhal->mac_func_enable = false;
1885 }
1886
1887 /* Reset MAC/BB/RF status if it is not powered off
1888 * before calling initialize Hw flow to prevent
1889 * from interface and MAC status mismatch.
1890 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1891 if (rtlhal->mac_func_enable) {
1892 _rtl8821ae_poweroff_adapter(hw);
1893 rtlhal->mac_func_enable = false;
1894 }
1895
1896 rtstatus = _rtl8821ae_init_mac(hw);
1897 if (!rtstatus) {
1898 pr_err("Init MAC failed\n");
1899 err = 1;
1900 return err;
1901 }
1902
1903 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1904 tmp_u1b &= 0x7F;
1905 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1906
1907 err = rtl8821ae_download_fw(hw, false);
1908 if (err) {
1909 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1910 "Failed to download FW. Init HW without FW now\n");
1911 err = 1;
1912 rtlhal->fw_ready = false;
1913 return err;
1914 } else {
1915 rtlhal->fw_ready = true;
1916 }
1917 ppsc->fw_current_inpsmode = false;
1918 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1919 rtlhal->fw_clk_change_in_progress = false;
1920 rtlhal->allow_sw_to_change_hwclc = false;
1921 rtlhal->last_hmeboxnum = 0;
1922
1923 /*SIC_Init(Adapter);
1924 if(rtlhal->AMPDUBurstMode)
1925 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1926
1927 rtl8821ae_phy_mac_config(hw);
1928 /* because last function modify RCR, so we update
1929 * rcr var here, or TP will unstable for receive_config
1930 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1931 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1932 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1933 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1934 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1935 rtl8821ae_phy_bb_config(hw);
1936
1937 rtl8821ae_phy_rf_config(hw);
1938
1939 if (rtlpriv->phy.rf_type == RF_1T1R &&
1940 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1941 _rtl8812ae_bb8812_config_1t(hw);
1942
1943 _rtl8821ae_hw_configure(hw);
1944
1945 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1946
1947 /*set wireless mode*/
1948
1949 rtlhal->mac_func_enable = true;
1950
1951 rtl_cam_reset_all_entry(hw);
1952
1953 rtl8821ae_enable_hw_security_config(hw);
1954
1955 ppsc->rfpwr_state = ERFON;
1956
1957 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1958 _rtl8821ae_enable_aspm_back_door(hw);
1959 rtlpriv->intf_ops->enable_aspm(hw);
1960
1961 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1962 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1963 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1964
1965 rtl8821ae_bt_hw_init(hw);
1966 rtlpriv->rtlhal.being_init_adapter = false;
1967
1968 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1969
1970 /* rtl8821ae_dm_check_txpower_tracking(hw); */
1971 /* rtl8821ae_phy_lc_calibrate(hw); */
1972 if (support_remote_wakeup)
1973 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
1974
1975 /* Release Rx DMA*/
1976 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1977 if (tmp_u1b & BIT(2)) {
1978 /* Release Rx DMA if needed*/
1979 tmp_u1b &= ~BIT(2);
1980 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1981 }
1982
1983 /* Release Tx/Rx PCIE DMA if*/
1984 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1985
1986 rtl8821ae_dm_init(hw);
1987 rtl8821ae_macid_initialize_mediastatus(hw);
1988
1989 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s() <====\n", __func__);
1990 return err;
1991 }
1992
1993 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
1994 {
1995 struct rtl_priv *rtlpriv = rtl_priv(hw);
1996 struct rtl_phy *rtlphy = &rtlpriv->phy;
1997 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1998 enum version_8821ae version = VERSION_UNKNOWN;
1999 u32 value32;
2000
2001 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2002 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2003 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2004
2005 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2006 rtlphy->rf_type = RF_2T2R;
2007 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2008 rtlphy->rf_type = RF_1T1R;
2009
2010 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2011 "RF_Type is %x!!\n", rtlphy->rf_type);
2012
2013 if (value32 & TRP_VAUX_EN) {
2014 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2015 if (rtlphy->rf_type == RF_2T2R)
2016 version = VERSION_TEST_CHIP_2T2R_8812;
2017 else
2018 version = VERSION_TEST_CHIP_1T1R_8812;
2019 } else
2020 version = VERSION_TEST_CHIP_8821;
2021 } else {
2022 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2023 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2024
2025 if (rtlphy->rf_type == RF_2T2R)
2026 version =
2027 (enum version_8821ae)(CHIP_8812
2028 | NORMAL_CHIP |
2029 RF_TYPE_2T2R);
2030 else
2031 version = (enum version_8821ae)(CHIP_8812
2032 | NORMAL_CHIP);
2033
2034 version = (enum version_8821ae)(version | (rtl_id << 12));
2035 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2036 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2037
2038 version = (enum version_8821ae)(CHIP_8821
2039 | NORMAL_CHIP | rtl_id);
2040 }
2041 }
2042
2043 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2044 /*WL_HWROF_EN.*/
2045 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2046 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2047 }
2048
2049 switch (version) {
2050 case VERSION_TEST_CHIP_1T1R_8812:
2051 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2052 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2053 break;
2054 case VERSION_TEST_CHIP_2T2R_8812:
2055 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2056 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2057 break;
2058 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2059 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2060 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2061 break;
2062 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2063 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2064 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2065 break;
2066 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2067 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2068 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2069 break;
2070 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2071 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2072 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2073 break;
2074 case VERSION_TEST_CHIP_8821:
2075 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2076 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2077 break;
2078 case VERSION_NORMAL_TSMC_CHIP_8821:
2079 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2080 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2081 break;
2082 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2083 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2084 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2085 break;
2086 default:
2087 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2088 "Chip Version ID: Unknown (0x%X)\n", version);
2089 break;
2090 }
2091
2092 return version;
2093 }
2094
2095 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2096 enum nl80211_iftype type)
2097 {
2098 struct rtl_priv *rtlpriv = rtl_priv(hw);
2099 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2100 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2101 bt_msr &= 0xfc;
2102
2103 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2104 rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
2105 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2106
2107 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2108 type == NL80211_IFTYPE_STATION) {
2109 _rtl8821ae_stop_tx_beacon(hw);
2110 _rtl8821ae_enable_bcn_sub_func(hw);
2111 } else if (type == NL80211_IFTYPE_ADHOC ||
2112 type == NL80211_IFTYPE_AP) {
2113 _rtl8821ae_resume_tx_beacon(hw);
2114 _rtl8821ae_disable_bcn_sub_func(hw);
2115 } else {
2116 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2117 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2118 type);
2119 }
2120
2121 switch (type) {
2122 case NL80211_IFTYPE_UNSPECIFIED:
2123 bt_msr |= MSR_NOLINK;
2124 ledaction = LED_CTL_LINK;
2125 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2126 "Set Network type to NO LINK!\n");
2127 break;
2128 case NL80211_IFTYPE_ADHOC:
2129 bt_msr |= MSR_ADHOC;
2130 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2131 "Set Network type to Ad Hoc!\n");
2132 break;
2133 case NL80211_IFTYPE_STATION:
2134 bt_msr |= MSR_INFRA;
2135 ledaction = LED_CTL_LINK;
2136 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2137 "Set Network type to STA!\n");
2138 break;
2139 case NL80211_IFTYPE_AP:
2140 bt_msr |= MSR_AP;
2141 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2142 "Set Network type to AP!\n");
2143 break;
2144 default:
2145 pr_err("Network type %d not support!\n", type);
2146 return 1;
2147 }
2148
2149 rtl_write_byte(rtlpriv, MSR, bt_msr);
2150 rtlpriv->cfg->ops->led_control(hw, ledaction);
2151 if ((bt_msr & MSR_MASK) == MSR_AP)
2152 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2153 else
2154 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2155
2156 return 0;
2157 }
2158
2159 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2160 {
2161 struct rtl_priv *rtlpriv = rtl_priv(hw);
2162 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2163 u32 reg_rcr = rtlpci->receive_config;
2164
2165 if (rtlpriv->psc.rfpwr_state != ERFON)
2166 return;
2167
2168 if (check_bssid) {
2169 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2170 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2171 (u8 *)(&reg_rcr));
2172 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2173 } else if (!check_bssid) {
2174 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2175 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2176 rtlpriv->cfg->ops->set_hw_reg(hw,
2177 HW_VAR_RCR, (u8 *)(&reg_rcr));
2178 }
2179 }
2180
2181 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2182 {
2183 struct rtl_priv *rtlpriv = rtl_priv(hw);
2184
2185 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s!\n", __func__);
2186
2187 if (_rtl8821ae_set_media_status(hw, type))
2188 return -EOPNOTSUPP;
2189
2190 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2191 if (type != NL80211_IFTYPE_AP)
2192 rtl8821ae_set_check_bssid(hw, true);
2193 } else {
2194 rtl8821ae_set_check_bssid(hw, false);
2195 }
2196
2197 return 0;
2198 }
2199
2200 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2201 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2202 {
2203 struct rtl_priv *rtlpriv = rtl_priv(hw);
2204 rtl8821ae_dm_init_edca_turbo(hw);
2205 switch (aci) {
2206 case AC1_BK:
2207 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2208 break;
2209 case AC0_BE:
2210 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2211 break;
2212 case AC2_VI:
2213 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2214 break;
2215 case AC3_VO:
2216 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2217 break;
2218 default:
2219 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci);
2220 break;
2221 }
2222 }
2223
2224 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2225 {
2226 struct rtl_priv *rtlpriv = rtl_priv(hw);
2227 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2228
2229 rtl_write_dword(rtlpriv, REG_HISR, tmp);
2230
2231 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2232 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2233
2234 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2235 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2236 }
2237
2238 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2239 {
2240 struct rtl_priv *rtlpriv = rtl_priv(hw);
2241 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2242
2243 if (rtlpci->int_clear)
2244 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2245
2246 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2247 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2248 rtlpci->irq_enabled = true;
2249 /* there are some C2H CMDs have been sent before
2250 system interrupt is enabled, e.g., C2H, CPWM.
2251 *So we need to clear all C2H events that FW has
2252 notified, otherwise FW won't schedule any commands anymore.
2253 */
2254 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2255 /*enable system interrupt*/
2256 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2257 }
2258
2259 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2260 {
2261 struct rtl_priv *rtlpriv = rtl_priv(hw);
2262 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2263
2264 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2265 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2266 rtlpci->irq_enabled = false;
2267 /*synchronize_irq(rtlpci->pdev->irq);*/
2268 }
2269
2270 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2271 {
2272 struct rtl_priv *rtlpriv = rtl_priv(hw);
2273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2274 u16 cap_hdr;
2275 u8 cap_pointer;
2276 u8 cap_id = 0xff;
2277 u8 pmcs_reg;
2278 u8 cnt = 0;
2279
2280 /* Get the Capability pointer first,
2281 * the Capability Pointer is located at
2282 * offset 0x34 from the Function Header */
2283
2284 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2285 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2286 "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2287
2288 do {
2289 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2290 cap_id = cap_hdr & 0xFF;
2291
2292 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2293 "in pci configuration, cap_pointer%x = %x\n",
2294 cap_pointer, cap_id);
2295
2296 if (cap_id == 0x01) {
2297 break;
2298 } else {
2299 /* point to next Capability */
2300 cap_pointer = (cap_hdr >> 8) & 0xFF;
2301 /* 0: end of pci capability, 0xff: invalid value */
2302 if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2303 cap_id = 0xff;
2304 break;
2305 }
2306 }
2307 } while (cnt++ < 200);
2308
2309 if (cap_id == 0x01) {
2310 /* Get the PM CSR (Control/Status Register),
2311 * The PME_Status is located at PM Capatibility offset 5, bit 7
2312 */
2313 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2314
2315 if (pmcs_reg & BIT(7)) {
2316 /* PME event occured, clear the PM_Status by write 1 */
2317 pmcs_reg = pmcs_reg | BIT(7);
2318
2319 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2320 pmcs_reg);
2321 /* Read it back to check */
2322 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2323 &pmcs_reg);
2324 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2325 "Clear PME status 0x%2x to 0x%2x\n",
2326 cap_pointer + 5, pmcs_reg);
2327 } else {
2328 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2329 "PME status(0x%2x) = 0x%2x\n",
2330 cap_pointer + 5, pmcs_reg);
2331 }
2332 } else {
2333 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
2334 "Cannot find PME Capability\n");
2335 }
2336 }
2337
2338 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2339 {
2340 struct rtl_priv *rtlpriv = rtl_priv(hw);
2341 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2342 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2343 struct rtl_mac *mac = rtl_mac(rtlpriv);
2344 enum nl80211_iftype opmode;
2345 bool support_remote_wakeup;
2346 u8 tmp;
2347 u32 count = 0;
2348
2349 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2350 (u8 *)(&support_remote_wakeup));
2351
2352 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2353
2354 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2355 || !rtlhal->enter_pnp_sleep) {
2356 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2357 mac->link_state = MAC80211_NOLINK;
2358 opmode = NL80211_IFTYPE_UNSPECIFIED;
2359 _rtl8821ae_set_media_status(hw, opmode);
2360 _rtl8821ae_poweroff_adapter(hw);
2361 } else {
2362 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2363 /* 3 <1> Prepare for configuring wowlan related infomations */
2364 /* Clear Fw WoWLAN event. */
2365 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2366
2367 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2368 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2369 #endif
2370 /* Dynamically adjust Tx packet boundary
2371 * for download reserved page packet.
2372 * reserve 30 pages for rsvd page */
2373 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2374 rtlhal->re_init_llt_table = true;
2375
2376 /* 3 <2> Set Fw releted H2C cmd. */
2377
2378 /* Set WoWLAN related security information. */
2379 rtl8821ae_set_fw_global_info_cmd(hw);
2380
2381 _rtl8821ae_download_rsvd_page(hw, true);
2382
2383 /* Just enable AOAC related functions when we connect to AP. */
2384 printk("mac->link_state = %d\n", mac->link_state);
2385 if (mac->link_state >= MAC80211_LINKED &&
2386 mac->opmode == NL80211_IFTYPE_STATION) {
2387 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2388 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2389 RT_MEDIA_CONNECT);
2390
2391 rtl8821ae_set_fw_wowlan_mode(hw, true);
2392 /* Enable Fw Keep alive mechanism. */
2393 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2394
2395 /* Enable disconnect decision control. */
2396 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2397 }
2398
2399 /* 3 <3> Hw Configutations */
2400
2401 /* Wait untill Rx DMA Finished before host sleep.
2402 * FW Pause Rx DMA may happens when received packet doing dma.
2403 */
2404 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2405
2406 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2407 count = 0;
2408 while (!(tmp & BIT(1)) && (count++ < 100)) {
2409 udelay(10);
2410 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2411 }
2412 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2413 "Wait Rx DMA Finished before host sleep. count=%d\n",
2414 count);
2415
2416 /* reset trx ring */
2417 rtlpriv->intf_ops->reset_trx_ring(hw);
2418
2419 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2420
2421 _rtl8821ae_clear_pci_pme_status(hw);
2422 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2423 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2424 /* prevent 8051 to be reset by PERST */
2425 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2426 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2427 }
2428
2429 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2430 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2431 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2432 /* For wowlan+LPS+32k. */
2433 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2434 /* Set the WoWLAN related function control enable.
2435 * It should be the last H2C cmd in the WoWLAN flow. */
2436 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2437
2438 /* Stop Pcie Interface Tx DMA. */
2439 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2440 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2441
2442 /* Wait for TxDMA idle. */
2443 count = 0;
2444 do {
2445 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2446 udelay(10);
2447 count++;
2448 } while ((tmp != 0) && (count < 100));
2449 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2450 "Wait Tx DMA Finished before host sleep. count=%d\n",
2451 count);
2452
2453 if (rtlhal->hw_rof_enable) {
2454 printk("hw_rof_enable\n");
2455 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2456 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2457 }
2458 }
2459 /* after power off we should do iqk again */
2460 rtlpriv->phy.iqk_initialized = false;
2461 }
2462
2463 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2464 struct rtl_int *intvec)
2465 {
2466 struct rtl_priv *rtlpriv = rtl_priv(hw);
2467 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2468
2469 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2470 rtl_write_dword(rtlpriv, ISR, intvec->inta);
2471
2472 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2473 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
2474 }
2475
2476 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2477 {
2478 struct rtl_priv *rtlpriv = rtl_priv(hw);
2479 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2480 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2481 u16 bcn_interval, atim_window;
2482
2483 bcn_interval = mac->beacon_interval;
2484 atim_window = 2; /*FIX MERGE */
2485 rtl8821ae_disable_interrupt(hw);
2486 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2487 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2488 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2489 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2490 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2491 rtl_write_byte(rtlpriv, 0x606, 0x30);
2492 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2493 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2494 rtl8821ae_enable_interrupt(hw);
2495 }
2496
2497 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2498 {
2499 struct rtl_priv *rtlpriv = rtl_priv(hw);
2500 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2501 u16 bcn_interval = mac->beacon_interval;
2502
2503 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
2504 "beacon_interval:%d\n", bcn_interval);
2505 rtl8821ae_disable_interrupt(hw);
2506 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2507 rtl8821ae_enable_interrupt(hw);
2508 }
2509
2510 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2511 u32 add_msr, u32 rm_msr)
2512 {
2513 struct rtl_priv *rtlpriv = rtl_priv(hw);
2514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2515
2516 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
2517 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2518
2519 if (add_msr)
2520 rtlpci->irq_mask[0] |= add_msr;
2521 if (rm_msr)
2522 rtlpci->irq_mask[0] &= (~rm_msr);
2523 rtl8821ae_disable_interrupt(hw);
2524 rtl8821ae_enable_interrupt(hw);
2525 }
2526
2527 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2528 {
2529 u8 group = 0;
2530
2531 if (chnl <= 14) {
2532 if (1 <= chnl && chnl <= 2)
2533 group = 0;
2534 else if (3 <= chnl && chnl <= 5)
2535 group = 1;
2536 else if (6 <= chnl && chnl <= 8)
2537 group = 2;
2538 else if (9 <= chnl && chnl <= 11)
2539 group = 3;
2540 else /*if (12 <= chnl && chnl <= 14)*/
2541 group = 4;
2542 } else {
2543 if (36 <= chnl && chnl <= 42)
2544 group = 0;
2545 else if (44 <= chnl && chnl <= 48)
2546 group = 1;
2547 else if (50 <= chnl && chnl <= 58)
2548 group = 2;
2549 else if (60 <= chnl && chnl <= 64)
2550 group = 3;
2551 else if (100 <= chnl && chnl <= 106)
2552 group = 4;
2553 else if (108 <= chnl && chnl <= 114)
2554 group = 5;
2555 else if (116 <= chnl && chnl <= 122)
2556 group = 6;
2557 else if (124 <= chnl && chnl <= 130)
2558 group = 7;
2559 else if (132 <= chnl && chnl <= 138)
2560 group = 8;
2561 else if (140 <= chnl && chnl <= 144)
2562 group = 9;
2563 else if (149 <= chnl && chnl <= 155)
2564 group = 10;
2565 else if (157 <= chnl && chnl <= 161)
2566 group = 11;
2567 else if (165 <= chnl && chnl <= 171)
2568 group = 12;
2569 else if (173 <= chnl && chnl <= 177)
2570 group = 13;
2571 else
2572 WARN_ONCE(true,
2573 "rtl8821ae: 5G, Channel %d in Group not found\n",
2574 chnl);
2575 }
2576 return group;
2577 }
2578
2579 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2580 struct txpower_info_2g *pwrinfo24g,
2581 struct txpower_info_5g *pwrinfo5g,
2582 bool autoload_fail,
2583 u8 *hwinfo)
2584 {
2585 struct rtl_priv *rtlpriv = rtl_priv(hw);
2586 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0;
2587
2588 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2589 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2590 (eeaddr + 1), hwinfo[eeaddr + 1]);
2591 if (hwinfo[eeaddr + 1] == 0xFF) /*YJ,add,120316*/
2592 autoload_fail = true;
2593
2594 if (autoload_fail) {
2595 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2596 "auto load fail : Use Default value!\n");
2597 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
2598 /*2.4G default value*/
2599 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2600 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2601 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
2602 }
2603 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2604 if (txcount == 0) {
2605 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
2606 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
2607 } else {
2608 pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE;
2609 pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE;
2610 pwrinfo24g->cck_diff[rfpath][txcount] = 0xFE;
2611 pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE;
2612 }
2613 }
2614 /*5G default value*/
2615 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2616 pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A;
2617
2618 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2619 if (txcount == 0) {
2620 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
2621 pwrinfo5g->bw20_diff[rfpath][0] = 0x00;
2622 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2623 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
2624 } else {
2625 pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE;
2626 pwrinfo5g->bw20_diff[rfpath][0] = 0xFE;
2627 pwrinfo5g->bw40_diff[rfpath][0] = 0xFE;
2628 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2629 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
2630 }
2631 }
2632 }
2633 return;
2634 }
2635
2636 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2637
2638 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
2639 /*2.4G default value*/
2640 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2641 pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++];
2642 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
2643 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2644 }
2645 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2646 pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2647 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
2648 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
2649 }
2650 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2651 if (txcount == 0) {
2652 pwrinfo24g->bw40_diff[rfpath][txcount] = 0;
2653 /*bit sign number to 8 bit sign number*/
2654 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2655 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2656 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
2657 /*bit sign number to 8 bit sign number*/
2658 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2659 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2660 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
2661
2662 pwrinfo24g->cck_diff[rfpath][txcount] = 0;
2663 eeaddr++;
2664 } else {
2665 pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2666 if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3))
2667 pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0;
2668
2669 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2670 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2671 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
2672
2673 eeaddr++;
2674
2675 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2676 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2677 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
2678
2679 pwrinfo24g->cck_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2680 if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3))
2681 pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0;
2682
2683 eeaddr++;
2684 }
2685 }
2686
2687 /*5G default value*/
2688 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2689 pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2690 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
2691 pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE;
2692 }
2693
2694 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2695 if (txcount == 0) {
2696 pwrinfo5g->bw40_diff[rfpath][txcount] = 0;
2697
2698 pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4;
2699 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2700 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
2701
2702 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f);
2703 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2704 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
2705
2706 eeaddr++;
2707 } else {
2708 pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2709 if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3))
2710 pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0;
2711
2712 pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2713 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2714 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
2715
2716 eeaddr++;
2717 }
2718 }
2719
2720 pwrinfo5g->ofdm_diff[rfpath][1] = (hwinfo[eeaddr] & 0xf0) >> 4;
2721 pwrinfo5g->ofdm_diff[rfpath][2] = (hwinfo[eeaddr] & 0x0f);
2722
2723 eeaddr++;
2724
2725 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f);
2726
2727 eeaddr++;
2728
2729 for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) {
2730 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2731 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
2732 }
2733 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2734 pwrinfo5g->bw80_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2735 /* 4bit sign number to 8 bit sign number */
2736 if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3))
2737 pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0;
2738 /* 4bit sign number to 8 bit sign number */
2739 pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2740 if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3))
2741 pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0;
2742
2743 eeaddr++;
2744 }
2745 }
2746 }
2747 #if 0
2748 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2749 bool autoload_fail,
2750 u8 *hwinfo)
2751 {
2752 struct rtl_priv *rtlpriv = rtl_priv(hw);
2753 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2754 struct txpower_info_2g pwrinfo24g;
2755 struct txpower_info_5g pwrinfo5g;
2756 u8 rf_path, index;
2757 u8 i;
2758
2759 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2760 &pwrinfo5g, autoload_fail, hwinfo);
2761
2762 for (rf_path = 0; rf_path < 2; rf_path++) {
2763 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2764 index = _rtl8821ae_get_chnl_group(i + 1);
2765
2766 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2767 rtlefuse->txpwrlevel_cck[rf_path][i] =
2768 pwrinfo24g.index_cck_base[rf_path][5];
2769 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2770 pwrinfo24g.index_bw40_base[rf_path][index];
2771 } else {
2772 rtlefuse->txpwrlevel_cck[rf_path][i] =
2773 pwrinfo24g.index_cck_base[rf_path][index];
2774 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2775 pwrinfo24g.index_bw40_base[rf_path][index];
2776 }
2777 }
2778
2779 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2780 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2781 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2782 pwrinfo5g.index_bw40_base[rf_path][index];
2783 }
2784 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2785 u8 upper, lower;
2786 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2787 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2788 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2789
2790 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2791 }
2792 for (i = 0; i < MAX_TX_COUNT; i++) {
2793 rtlefuse->txpwr_cckdiff[rf_path][i] =
2794 pwrinfo24g.cck_diff[rf_path][i];
2795 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2796 pwrinfo24g.ofdm_diff[rf_path][i];
2797 rtlefuse->txpwr_ht20diff[rf_path][i] =
2798 pwrinfo24g.bw20_diff[rf_path][i];
2799 rtlefuse->txpwr_ht40diff[rf_path][i] =
2800 pwrinfo24g.bw40_diff[rf_path][i];
2801
2802 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2803 pwrinfo5g.ofdm_diff[rf_path][i];
2804 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2805 pwrinfo5g.bw20_diff[rf_path][i];
2806 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2807 pwrinfo5g.bw40_diff[rf_path][i];
2808 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2809 pwrinfo5g.bw80_diff[rf_path][i];
2810 }
2811 }
2812
2813 if (!autoload_fail) {
2814 rtlefuse->eeprom_regulatory =
2815 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2816 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2817 rtlefuse->eeprom_regulatory = 0;
2818 } else {
2819 rtlefuse->eeprom_regulatory = 0;
2820 }
2821
2822 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2823 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2824 }
2825 #endif
2826 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2827 bool autoload_fail,
2828 u8 *hwinfo)
2829 {
2830 struct rtl_priv *rtlpriv = rtl_priv(hw);
2831 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2832 struct txpower_info_2g pwrinfo24g;
2833 struct txpower_info_5g pwrinfo5g;
2834 u8 rf_path, index;
2835 u8 i;
2836
2837 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2838 &pwrinfo5g, autoload_fail, hwinfo);
2839
2840 for (rf_path = 0; rf_path < 2; rf_path++) {
2841 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2842 index = _rtl8821ae_get_chnl_group(i + 1);
2843
2844 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2845 rtlefuse->txpwrlevel_cck[rf_path][i] =
2846 pwrinfo24g.index_cck_base[rf_path][5];
2847 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2848 pwrinfo24g.index_bw40_base[rf_path][index];
2849 } else {
2850 rtlefuse->txpwrlevel_cck[rf_path][i] =
2851 pwrinfo24g.index_cck_base[rf_path][index];
2852 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2853 pwrinfo24g.index_bw40_base[rf_path][index];
2854 }
2855 }
2856
2857 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2858 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2859 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2860 pwrinfo5g.index_bw40_base[rf_path][index];
2861 }
2862 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2863 u8 upper, lower;
2864 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2865 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2866 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2867
2868 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2869 }
2870 for (i = 0; i < MAX_TX_COUNT; i++) {
2871 rtlefuse->txpwr_cckdiff[rf_path][i] =
2872 pwrinfo24g.cck_diff[rf_path][i];
2873 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2874 pwrinfo24g.ofdm_diff[rf_path][i];
2875 rtlefuse->txpwr_ht20diff[rf_path][i] =
2876 pwrinfo24g.bw20_diff[rf_path][i];
2877 rtlefuse->txpwr_ht40diff[rf_path][i] =
2878 pwrinfo24g.bw40_diff[rf_path][i];
2879
2880 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2881 pwrinfo5g.ofdm_diff[rf_path][i];
2882 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2883 pwrinfo5g.bw20_diff[rf_path][i];
2884 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2885 pwrinfo5g.bw40_diff[rf_path][i];
2886 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2887 pwrinfo5g.bw80_diff[rf_path][i];
2888 }
2889 }
2890 /*bit0~2*/
2891 if (!autoload_fail) {
2892 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2893 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2894 rtlefuse->eeprom_regulatory = 0;
2895 } else {
2896 rtlefuse->eeprom_regulatory = 0;
2897 }
2898
2899 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2900 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2901 }
2902
2903 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2904 bool autoload_fail)
2905 {
2906 struct rtl_priv *rtlpriv = rtl_priv(hw);
2907 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2908
2909 if (!autoload_fail) {
2910 rtlhal->pa_type_2g = hwinfo[0XBC];
2911 rtlhal->lna_type_2g = hwinfo[0XBD];
2912 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2913 rtlhal->pa_type_2g = 0;
2914 rtlhal->lna_type_2g = 0;
2915 }
2916 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2917 (rtlhal->pa_type_2g & BIT(4))) ?
2918 1 : 0;
2919 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2920 (rtlhal->lna_type_2g & BIT(3))) ?
2921 1 : 0;
2922
2923 rtlhal->pa_type_5g = hwinfo[0XBC];
2924 rtlhal->lna_type_5g = hwinfo[0XBF];
2925 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2926 rtlhal->pa_type_5g = 0;
2927 rtlhal->lna_type_5g = 0;
2928 }
2929 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2930 (rtlhal->pa_type_5g & BIT(0))) ?
2931 1 : 0;
2932 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2933 (rtlhal->lna_type_5g & BIT(3))) ?
2934 1 : 0;
2935 } else {
2936 rtlhal->external_pa_2g = 0;
2937 rtlhal->external_lna_2g = 0;
2938 rtlhal->external_pa_5g = 0;
2939 rtlhal->external_lna_5g = 0;
2940 }
2941 }
2942
2943 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
2944 bool autoload_fail)
2945 {
2946 struct rtl_priv *rtlpriv = rtl_priv(hw);
2947 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2948
2949 u8 ext_type_pa_2g_a = (hwinfo[0XBD] & BIT(2)) >> 2; /* 0XBD[2] */
2950 u8 ext_type_pa_2g_b = (hwinfo[0XBD] & BIT(6)) >> 6; /* 0XBD[6] */
2951 u8 ext_type_pa_5g_a = (hwinfo[0XBF] & BIT(2)) >> 2; /* 0XBF[2] */
2952 u8 ext_type_pa_5g_b = (hwinfo[0XBF] & BIT(6)) >> 6; /* 0XBF[6] */
2953 /* 0XBD[1:0] */
2954 u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0;
2955 /* 0XBD[5:4] */
2956 u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4;
2957 /* 0XBF[1:0] */
2958 u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0;
2959 /* 0XBF[5:4] */
2960 u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4;
2961
2962 _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
2963
2964 /* [2.4G] Path A and B are both extPA */
2965 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
2966 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a;
2967
2968 /* [5G] Path A and B are both extPA */
2969 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
2970 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a;
2971
2972 /* [2.4G] Path A and B are both extLNA */
2973 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2974 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
2975
2976 /* [5G] Path A and B are both extLNA */
2977 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2978 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
2979 }
2980
2981 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2982 bool autoload_fail)
2983 {
2984 struct rtl_priv *rtlpriv = rtl_priv(hw);
2985 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2986
2987 if (!autoload_fail) {
2988 rtlhal->pa_type_2g = hwinfo[0XBC];
2989 rtlhal->lna_type_2g = hwinfo[0XBD];
2990 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2991 rtlhal->pa_type_2g = 0;
2992 rtlhal->lna_type_2g = 0;
2993 }
2994 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2995 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2996
2997 rtlhal->pa_type_5g = hwinfo[0XBC];
2998 rtlhal->lna_type_5g = hwinfo[0XBF];
2999 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3000 rtlhal->pa_type_5g = 0;
3001 rtlhal->lna_type_5g = 0;
3002 }
3003 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3004 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3005 } else {
3006 rtlhal->external_pa_2g = 0;
3007 rtlhal->external_lna_2g = 0;
3008 rtlhal->external_pa_5g = 0;
3009 rtlhal->external_lna_5g = 0;
3010 }
3011 }
3012
3013 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3014 bool autoload_fail)
3015 {
3016 struct rtl_priv *rtlpriv = rtl_priv(hw);
3017 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3018
3019 if (!autoload_fail) {
3020 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3021 if (rtlhal->external_lna_5g) {
3022 if (rtlhal->external_pa_5g) {
3023 if (rtlhal->external_lna_2g &&
3024 rtlhal->external_pa_2g)
3025 rtlhal->rfe_type = 3;
3026 else
3027 rtlhal->rfe_type = 0;
3028 } else {
3029 rtlhal->rfe_type = 2;
3030 }
3031 } else {
3032 rtlhal->rfe_type = 4;
3033 }
3034 } else {
3035 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3036
3037 if (rtlhal->rfe_type == 4 &&
3038 (rtlhal->external_pa_5g ||
3039 rtlhal->external_pa_2g ||
3040 rtlhal->external_lna_5g ||
3041 rtlhal->external_lna_2g)) {
3042 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3043 rtlhal->rfe_type = 2;
3044 }
3045 }
3046 } else {
3047 rtlhal->rfe_type = 0x04;
3048 }
3049
3050 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3051 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3052 }
3053
3054 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3055 bool auto_load_fail, u8 *hwinfo)
3056 {
3057 struct rtl_priv *rtlpriv = rtl_priv(hw);
3058 u8 value;
3059
3060 if (!auto_load_fail) {
3061 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3062 if (((value & 0xe0) >> 5) == 0x1)
3063 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3064 else
3065 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3066 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3067
3068 value = hwinfo[EEPROM_RF_BT_SETTING];
3069 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3070 } else {
3071 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3072 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3073 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3074 }
3075 /*move BT_InitHalVars() to init_sw_vars*/
3076 }
3077
3078 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3079 bool auto_load_fail, u8 *hwinfo)
3080 {
3081 struct rtl_priv *rtlpriv = rtl_priv(hw);
3082 u8 value;
3083 u32 tmpu_32;
3084
3085 if (!auto_load_fail) {
3086 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3087 if (tmpu_32 & BIT(18))
3088 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3089 else
3090 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3091 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3092
3093 value = hwinfo[EEPROM_RF_BT_SETTING];
3094 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3095 } else {
3096 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3097 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3098 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3099 }
3100 /*move BT_InitHalVars() to init_sw_vars*/
3101 }
3102
3103 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3104 {
3105 struct rtl_priv *rtlpriv = rtl_priv(hw);
3106 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3107 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3108 int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3109 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3110 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3111 COUNTRY_CODE_WORLD_WIDE_13};
3112 u8 *hwinfo;
3113
3114 if (b_pseudo_test) {
3115 ;/* need add */
3116 }
3117
3118 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3119 if (!hwinfo)
3120 return;
3121
3122 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3123 goto exit;
3124
3125 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3126 hwinfo);
3127
3128 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3129 _rtl8812ae_read_amplifier_type(hw, hwinfo,
3130 rtlefuse->autoload_failflag);
3131 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3132 rtlefuse->autoload_failflag, hwinfo);
3133 } else {
3134 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3135 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3136 rtlefuse->autoload_failflag, hwinfo);
3137 }
3138
3139 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3140 /*board type*/
3141 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3142 if (rtlhal->external_lna_2g != 0)
3143 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3144 if (rtlhal->external_lna_5g != 0)
3145 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3146 if (rtlhal->external_pa_2g != 0)
3147 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3148 if (rtlhal->external_pa_5g != 0)
3149 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3150
3151 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3152 rtlefuse->board_type |= ODM_BOARD_BT;
3153
3154 rtlhal->board_type = rtlefuse->board_type;
3155 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3156 "board_type = 0x%x\n", rtlefuse->board_type);
3157
3158 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3159 if (rtlefuse->eeprom_channelplan == 0xff)
3160 rtlefuse->eeprom_channelplan = 0x7F;
3161
3162 /* set channel plan from efuse */
3163 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3164
3165 /*parse xtal*/
3166 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3167 if (rtlefuse->crystalcap == 0xFF)
3168 rtlefuse->crystalcap = 0x20;
3169
3170 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3171 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3172 rtlefuse->autoload_failflag) {
3173 rtlefuse->apk_thermalmeterignore = true;
3174 rtlefuse->eeprom_thermalmeter = 0xff;
3175 }
3176
3177 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3178 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3179 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3180
3181 if (!rtlefuse->autoload_failflag) {
3182 rtlefuse->antenna_div_cfg =
3183 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3184 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3185 rtlefuse->antenna_div_cfg = 0;
3186
3187 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3188 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3189 rtlefuse->antenna_div_cfg = 0;
3190
3191 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3192 if (rtlefuse->antenna_div_type == 0xff)
3193 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3194 } else {
3195 rtlefuse->antenna_div_cfg = 0;
3196 rtlefuse->antenna_div_type = 0;
3197 }
3198
3199 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3200 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3201 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3202
3203 rtlpriv->ledctl.led_opendrain = true;
3204
3205 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3206 switch (rtlefuse->eeprom_oemid) {
3207 case RT_CID_DEFAULT:
3208 break;
3209 case EEPROM_CID_TOSHIBA:
3210 rtlhal->oem_id = RT_CID_TOSHIBA;
3211 break;
3212 case EEPROM_CID_CCX:
3213 rtlhal->oem_id = RT_CID_CCX;
3214 break;
3215 case EEPROM_CID_QMI:
3216 rtlhal->oem_id = RT_CID_819X_QMI;
3217 break;
3218 case EEPROM_CID_WHQL:
3219 break;
3220 default:
3221 break;
3222 }
3223 }
3224 exit:
3225 kfree(hwinfo);
3226 }
3227
3228 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3229 {
3230 struct rtl_priv *rtlpriv = rtl_priv(hw);
3231 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3232 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3233
3234 rtlpriv->ledctl.led_opendrain = true;
3235 switch (rtlhal->oem_id) {
3236 case RT_CID_819X_HP:
3237 rtlpriv->ledctl.led_opendrain = true;
3238 break;
3239 case RT_CID_819X_LENOVO:
3240 case RT_CID_DEFAULT:
3241 case RT_CID_TOSHIBA:
3242 case RT_CID_CCX:
3243 case RT_CID_819X_ACER:
3244 case RT_CID_WHQL:
3245 default:
3246 break;
3247 }
3248 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
3249 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3250 }*/
3251
3252 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3253 {
3254 struct rtl_priv *rtlpriv = rtl_priv(hw);
3255 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3256 struct rtl_phy *rtlphy = &rtlpriv->phy;
3257 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3258 u8 tmp_u1b;
3259
3260 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3261 if (get_rf_type(rtlphy) == RF_1T1R)
3262 rtlpriv->dm.rfpath_rxenable[0] = true;
3263 else
3264 rtlpriv->dm.rfpath_rxenable[0] =
3265 rtlpriv->dm.rfpath_rxenable[1] = true;
3266 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3267 rtlhal->version);
3268
3269 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3270 if (tmp_u1b & BIT(4)) {
3271 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3272 rtlefuse->epromtype = EEPROM_93C46;
3273 } else {
3274 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3275 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3276 }
3277
3278 if (tmp_u1b & BIT(5)) {
3279 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3280 rtlefuse->autoload_failflag = false;
3281 _rtl8821ae_read_adapter_info(hw, false);
3282 } else {
3283 pr_err("Autoload ERR!!\n");
3284 }
3285 /*hal_ReadRFType_8812A()*/
3286 /* _rtl8821ae_hal_customized_behavior(hw); */
3287 }
3288
3289 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3290 struct ieee80211_sta *sta)
3291 {
3292 struct rtl_priv *rtlpriv = rtl_priv(hw);
3293 struct rtl_phy *rtlphy = &rtlpriv->phy;
3294 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3295 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3296 u32 ratr_value;
3297 u8 ratr_index = 0;
3298 u8 b_nmode = mac->ht_enable;
3299 u8 mimo_ps = IEEE80211_SMPS_OFF;
3300 u16 shortgi_rate;
3301 u32 tmp_ratr_value;
3302 u8 curtxbw_40mhz = mac->bw_40;
3303 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3304 1 : 0;
3305 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3306 1 : 0;
3307 enum wireless_mode wirelessmode = mac->mode;
3308
3309 if (rtlhal->current_bandtype == BAND_ON_5G)
3310 ratr_value = sta->supp_rates[1] << 4;
3311 else
3312 ratr_value = sta->supp_rates[0];
3313 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3314 ratr_value = 0xfff;
3315 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3316 sta->ht_cap.mcs.rx_mask[0] << 12);
3317 switch (wirelessmode) {
3318 case WIRELESS_MODE_B:
3319 if (ratr_value & 0x0000000c)
3320 ratr_value &= 0x0000000d;
3321 else
3322 ratr_value &= 0x0000000f;
3323 break;
3324 case WIRELESS_MODE_G:
3325 ratr_value &= 0x00000FF5;
3326 break;
3327 case WIRELESS_MODE_N_24G:
3328 case WIRELESS_MODE_N_5G:
3329 b_nmode = 1;
3330 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3331 ratr_value &= 0x0007F005;
3332 } else {
3333 u32 ratr_mask;
3334
3335 if (get_rf_type(rtlphy) == RF_1T2R ||
3336 get_rf_type(rtlphy) == RF_1T1R)
3337 ratr_mask = 0x000ff005;
3338 else
3339 ratr_mask = 0x0f0ff005;
3340
3341 ratr_value &= ratr_mask;
3342 }
3343 break;
3344 default:
3345 if (rtlphy->rf_type == RF_1T2R)
3346 ratr_value &= 0x000ff0ff;
3347 else
3348 ratr_value &= 0x0f0ff0ff;
3349
3350 break;
3351 }
3352
3353 if ((rtlpriv->btcoexist.bt_coexistence) &&
3354 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3355 (rtlpriv->btcoexist.bt_cur_state) &&
3356 (rtlpriv->btcoexist.bt_ant_isolation) &&
3357 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3358 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3359 ratr_value &= 0x0fffcfc0;
3360 else
3361 ratr_value &= 0x0FFFFFFF;
3362
3363 if (b_nmode && ((curtxbw_40mhz &&
3364 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3365 b_curshortgi_20mhz))) {
3366 ratr_value |= 0x10000000;
3367 tmp_ratr_value = (ratr_value >> 12);
3368
3369 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3370 if ((1 << shortgi_rate) & tmp_ratr_value)
3371 break;
3372 }
3373
3374 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3375 (shortgi_rate << 4) | (shortgi_rate);
3376 }
3377
3378 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3379
3380 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3381 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3382 }
3383
3384 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3385 {
3386 u8 i, j, tmp_rate;
3387 u32 rate_bitmap = 0;
3388
3389 for (i = j = 0; i < 4; i += 2, j += 10) {
3390 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3391
3392 switch (tmp_rate) {
3393 case 2:
3394 rate_bitmap = rate_bitmap | (0x03ff << j);
3395 break;
3396 case 1:
3397 rate_bitmap = rate_bitmap | (0x01ff << j);
3398 break;
3399 case 0:
3400 rate_bitmap = rate_bitmap | (0x00ff << j);
3401 break;
3402 default:
3403 break;
3404 }
3405 }
3406
3407 return rate_bitmap;
3408 }
3409
3410 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3411 enum wireless_mode wirelessmode,
3412 u32 ratr_bitmap)
3413 {
3414 struct rtl_priv *rtlpriv = rtl_priv(hw);
3415 struct rtl_phy *rtlphy = &rtlpriv->phy;
3416 u32 ret_bitmap = ratr_bitmap;
3417
3418 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3419 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3420 ret_bitmap = ratr_bitmap;
3421 else if (wirelessmode == WIRELESS_MODE_AC_5G
3422 || wirelessmode == WIRELESS_MODE_AC_24G) {
3423 if (rtlphy->rf_type == RF_1T1R)
3424 ret_bitmap = ratr_bitmap & (~BIT21);
3425 else
3426 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3427 }
3428
3429 return ret_bitmap;
3430 }
3431
3432 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3433 u32 ratr_bitmap)
3434 {
3435 u8 ret = 0;
3436 if (wirelessmode < WIRELESS_MODE_N_24G)
3437 ret = 0;
3438 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3439 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3440 ret = 3;
3441 else /* Mix, 1SS */
3442 ret = 2;
3443 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3444 ret = 1;
3445 } /* VHT */
3446
3447 return ret << 4;
3448 }
3449
3450 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3451 u8 mac_id, struct rtl_sta_info *sta_entry,
3452 enum wireless_mode wirelessmode)
3453 {
3454 u8 b_ldpc = 0;
3455 /*not support ldpc, do not open*/
3456 return b_ldpc << 2;
3457 }
3458
3459 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3460 enum wireless_mode wirelessmode,
3461 u32 ratr_bitmap)
3462 {
3463 struct rtl_priv *rtlpriv = rtl_priv(hw);
3464 struct rtl_phy *rtlphy = &rtlpriv->phy;
3465 u8 rf_type = RF_1T1R;
3466
3467 if (rtlphy->rf_type == RF_1T1R)
3468 rf_type = RF_1T1R;
3469 else if (wirelessmode == WIRELESS_MODE_AC_5G
3470 || wirelessmode == WIRELESS_MODE_AC_24G
3471 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3472 if (ratr_bitmap & 0xffc00000)
3473 rf_type = RF_2T2R;
3474 } else if (wirelessmode == WIRELESS_MODE_N_5G
3475 || wirelessmode == WIRELESS_MODE_N_24G) {
3476 if (ratr_bitmap & 0xfff00000)
3477 rf_type = RF_2T2R;
3478 }
3479
3480 return rf_type;
3481 }
3482
3483 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3484 u8 mac_id)
3485 {
3486 bool b_short_gi = false;
3487 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3488 1 : 0;
3489 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3490 1 : 0;
3491 u8 b_curshortgi_80mhz = 0;
3492 b_curshortgi_80mhz = (sta->vht_cap.cap &
3493 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3494
3495 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3496 b_short_gi = false;
3497
3498 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3499 || b_curshortgi_20mhz)
3500 b_short_gi = true;
3501
3502 return b_short_gi;
3503 }
3504
3505 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3506 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3507 {
3508 struct rtl_priv *rtlpriv = rtl_priv(hw);
3509 struct rtl_phy *rtlphy = &rtlpriv->phy;
3510 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3511 struct rtl_sta_info *sta_entry = NULL;
3512 u32 ratr_bitmap;
3513 u8 ratr_index;
3514 enum wireless_mode wirelessmode = 0;
3515 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3516 ? 1 : 0;
3517 bool b_shortgi = false;
3518 u8 rate_mask[7];
3519 u8 macid = 0;
3520 u8 mimo_ps = IEEE80211_SMPS_OFF;
3521 u8 rf_type;
3522
3523 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3524 wirelessmode = sta_entry->wireless_mode;
3525
3526 rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3527 "wireless mode = 0x%x\n", wirelessmode);
3528 if (mac->opmode == NL80211_IFTYPE_STATION ||
3529 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3530 curtxbw_40mhz = mac->bw_40;
3531 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3532 mac->opmode == NL80211_IFTYPE_ADHOC)
3533 macid = sta->aid + 1;
3534 if (wirelessmode == WIRELESS_MODE_N_5G ||
3535 wirelessmode == WIRELESS_MODE_AC_5G ||
3536 wirelessmode == WIRELESS_MODE_A)
3537 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3538 else
3539 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3540
3541 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3542 ratr_bitmap = 0xfff;
3543
3544 if (wirelessmode == WIRELESS_MODE_N_24G
3545 || wirelessmode == WIRELESS_MODE_N_5G)
3546 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3547 sta->ht_cap.mcs.rx_mask[0] << 12);
3548 else if (wirelessmode == WIRELESS_MODE_AC_24G
3549 || wirelessmode == WIRELESS_MODE_AC_5G
3550 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3551 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3552 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3553
3554 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3555 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3556
3557 /*mac id owner*/
3558 switch (wirelessmode) {
3559 case WIRELESS_MODE_B:
3560 ratr_index = RATR_INX_WIRELESS_B;
3561 if (ratr_bitmap & 0x0000000c)
3562 ratr_bitmap &= 0x0000000d;
3563 else
3564 ratr_bitmap &= 0x0000000f;
3565 break;
3566 case WIRELESS_MODE_G:
3567 ratr_index = RATR_INX_WIRELESS_GB;
3568
3569 if (rssi_level == 1)
3570 ratr_bitmap &= 0x00000f00;
3571 else if (rssi_level == 2)
3572 ratr_bitmap &= 0x00000ff0;
3573 else
3574 ratr_bitmap &= 0x00000ff5;
3575 break;
3576 case WIRELESS_MODE_A:
3577 ratr_index = RATR_INX_WIRELESS_G;
3578 ratr_bitmap &= 0x00000ff0;
3579 break;
3580 case WIRELESS_MODE_N_24G:
3581 case WIRELESS_MODE_N_5G:
3582 if (wirelessmode == WIRELESS_MODE_N_24G)
3583 ratr_index = RATR_INX_WIRELESS_NGB;
3584 else
3585 ratr_index = RATR_INX_WIRELESS_NG;
3586
3587 if (mimo_ps == IEEE80211_SMPS_STATIC
3588 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3589 if (rssi_level == 1)
3590 ratr_bitmap &= 0x000f0000;
3591 else if (rssi_level == 2)
3592 ratr_bitmap &= 0x000ff000;
3593 else
3594 ratr_bitmap &= 0x000ff005;
3595 } else {
3596 if (rf_type == RF_1T1R) {
3597 if (curtxbw_40mhz) {
3598 if (rssi_level == 1)
3599 ratr_bitmap &= 0x000f0000;
3600 else if (rssi_level == 2)
3601 ratr_bitmap &= 0x000ff000;
3602 else
3603 ratr_bitmap &= 0x000ff015;
3604 } else {
3605 if (rssi_level == 1)
3606 ratr_bitmap &= 0x000f0000;
3607 else if (rssi_level == 2)
3608 ratr_bitmap &= 0x000ff000;
3609 else
3610 ratr_bitmap &= 0x000ff005;
3611 }
3612 } else {
3613 if (curtxbw_40mhz) {
3614 if (rssi_level == 1)
3615 ratr_bitmap &= 0x0fff0000;
3616 else if (rssi_level == 2)
3617 ratr_bitmap &= 0x0ffff000;
3618 else
3619 ratr_bitmap &= 0x0ffff015;
3620 } else {
3621 if (rssi_level == 1)
3622 ratr_bitmap &= 0x0fff0000;
3623 else if (rssi_level == 2)
3624 ratr_bitmap &= 0x0ffff000;
3625 else
3626 ratr_bitmap &= 0x0ffff005;
3627 }
3628 }
3629 }
3630 break;
3631
3632 case WIRELESS_MODE_AC_24G:
3633 ratr_index = RATR_INX_WIRELESS_AC_24N;
3634 if (rssi_level == 1)
3635 ratr_bitmap &= 0xfc3f0000;
3636 else if (rssi_level == 2)
3637 ratr_bitmap &= 0xfffff000;
3638 else
3639 ratr_bitmap &= 0xffffffff;
3640 break;
3641
3642 case WIRELESS_MODE_AC_5G:
3643 ratr_index = RATR_INX_WIRELESS_AC_5N;
3644
3645 if (rf_type == RF_1T1R) {
3646 if (rssi_level == 1) /*add by Gary for ac-series*/
3647 ratr_bitmap &= 0x003f8000;
3648 else if (rssi_level == 2)
3649 ratr_bitmap &= 0x003ff000;
3650 else
3651 ratr_bitmap &= 0x003ff010;
3652 } else {
3653 if (rssi_level == 1)
3654 ratr_bitmap &= 0xfe3f8000;
3655 else if (rssi_level == 2)
3656 ratr_bitmap &= 0xfffff000;
3657 else
3658 ratr_bitmap &= 0xfffff010;
3659 }
3660 break;
3661
3662 default:
3663 ratr_index = RATR_INX_WIRELESS_NGB;
3664
3665 if (rf_type == RF_1T2R)
3666 ratr_bitmap &= 0x000ff0ff;
3667 else
3668 ratr_bitmap &= 0x0f8ff0ff;
3669 break;
3670 }
3671
3672 ratr_index = rtl_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3673 sta_entry->ratr_index = ratr_index;
3674 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3675 ratr_bitmap);
3676
3677 rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3678 "ratr_bitmap :%x\n", ratr_bitmap);
3679
3680 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3681 (ratr_index << 28)); */
3682
3683 rate_mask[0] = macid;
3684 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3685 rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3)
3686 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3687 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3688
3689 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3690 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3691 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3692 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3693
3694 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3695 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3696 ratr_index, ratr_bitmap,
3697 rate_mask[0], rate_mask[1],
3698 rate_mask[2], rate_mask[3],
3699 rate_mask[4], rate_mask[5],
3700 rate_mask[6]);
3701 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3702 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3703 }
3704
3705 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3706 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3707 {
3708 struct rtl_priv *rtlpriv = rtl_priv(hw);
3709 if (rtlpriv->dm.useramask)
3710 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
3711 else
3712 /*rtl_dbg(rtlpriv, COMP_RATR,DBG_LOUD,
3713 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3714 rtl8821ae_update_hal_rate_table(hw, sta);
3715 }
3716
3717 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3718 {
3719 struct rtl_priv *rtlpriv = rtl_priv(hw);
3720 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3721 u16 wireless_mode = mac->mode;
3722 u8 sifs_timer, r2t_sifs;
3723
3724 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3725 (u8 *)&mac->slot_time);
3726 if (wireless_mode == WIRELESS_MODE_G)
3727 sifs_timer = 0x0a;
3728 else
3729 sifs_timer = 0x0e;
3730 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3731
3732 r2t_sifs = 0xa;
3733
3734 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3735 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3736 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3737 if (mac->vendor == PEER_ATH)
3738 r2t_sifs = 0x8;
3739 else
3740 r2t_sifs = 0xa;
3741 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3742 r2t_sifs = 0xa;
3743 }
3744
3745 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3746 }
3747
3748 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3749 {
3750 struct rtl_priv *rtlpriv = rtl_priv(hw);
3751 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3752 struct rtl_phy *rtlphy = &rtlpriv->phy;
3753 enum rf_pwrstate e_rfpowerstate_toset;
3754 u8 u1tmp = 0;
3755 bool b_actuallyset = false;
3756
3757 if (rtlpriv->rtlhal.being_init_adapter)
3758 return false;
3759
3760 if (ppsc->swrf_processing)
3761 return false;
3762
3763 spin_lock(&rtlpriv->locks.rf_ps_lock);
3764 if (ppsc->rfchange_inprogress) {
3765 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3766 return false;
3767 } else {
3768 ppsc->rfchange_inprogress = true;
3769 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3770 }
3771
3772 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3773 rtl_read_byte(rtlpriv,
3774 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3775
3776 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3777
3778 if (rtlphy->polarity_ctl)
3779 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3780 else
3781 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3782
3783 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3784 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3785 "GPIOChangeRF - HW Radio ON, RF ON\n");
3786
3787 e_rfpowerstate_toset = ERFON;
3788 ppsc->hwradiooff = false;
3789 b_actuallyset = true;
3790 } else if ((!ppsc->hwradiooff)
3791 && (e_rfpowerstate_toset == ERFOFF)) {
3792 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3793 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3794
3795 e_rfpowerstate_toset = ERFOFF;
3796 ppsc->hwradiooff = true;
3797 b_actuallyset = true;
3798 }
3799
3800 if (b_actuallyset) {
3801 spin_lock(&rtlpriv->locks.rf_ps_lock);
3802 ppsc->rfchange_inprogress = false;
3803 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3804 } else {
3805 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3806 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3807
3808 spin_lock(&rtlpriv->locks.rf_ps_lock);
3809 ppsc->rfchange_inprogress = false;
3810 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3811 }
3812
3813 *valid = 1;
3814 return !ppsc->hwradiooff;
3815 }
3816
3817 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3818 u8 *p_macaddr, bool is_group, u8 enc_algo,
3819 bool is_wepkey, bool clear_all)
3820 {
3821 struct rtl_priv *rtlpriv = rtl_priv(hw);
3822 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3823 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3824 u8 *macaddr = p_macaddr;
3825 u32 entry_id = 0;
3826 bool is_pairwise = false;
3827
3828 static u8 cam_const_addr[4][6] = {
3829 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3830 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3831 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3832 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3833 };
3834 static u8 cam_const_broad[] = {
3835 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3836 };
3837
3838 if (clear_all) {
3839 u8 idx = 0;
3840 u8 cam_offset = 0;
3841 u8 clear_number = 5;
3842
3843 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3844
3845 for (idx = 0; idx < clear_number; idx++) {
3846 rtl_cam_mark_invalid(hw, cam_offset + idx);
3847 rtl_cam_empty_entry(hw, cam_offset + idx);
3848
3849 if (idx < 5) {
3850 memset(rtlpriv->sec.key_buf[idx], 0,
3851 MAX_KEY_LEN);
3852 rtlpriv->sec.key_len[idx] = 0;
3853 }
3854 }
3855 } else {
3856 switch (enc_algo) {
3857 case WEP40_ENCRYPTION:
3858 enc_algo = CAM_WEP40;
3859 break;
3860 case WEP104_ENCRYPTION:
3861 enc_algo = CAM_WEP104;
3862 break;
3863 case TKIP_ENCRYPTION:
3864 enc_algo = CAM_TKIP;
3865 break;
3866 case AESCCMP_ENCRYPTION:
3867 enc_algo = CAM_AES;
3868 break;
3869 default:
3870 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3871 "switch case %#x not processed\n", enc_algo);
3872 enc_algo = CAM_TKIP;
3873 break;
3874 }
3875
3876 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3877 macaddr = cam_const_addr[key_index];
3878 entry_id = key_index;
3879 } else {
3880 if (is_group) {
3881 macaddr = cam_const_broad;
3882 entry_id = key_index;
3883 } else {
3884 if (mac->opmode == NL80211_IFTYPE_AP) {
3885 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3886 if (entry_id >= TOTAL_CAM_ENTRY) {
3887 pr_err("an not find free hwsecurity cam entry\n");
3888 return;
3889 }
3890 } else {
3891 entry_id = CAM_PAIRWISE_KEY_POSITION;
3892 }
3893
3894 key_index = PAIRWISE_KEYIDX;
3895 is_pairwise = true;
3896 }
3897 }
3898
3899 if (rtlpriv->sec.key_len[key_index] == 0) {
3900 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3901 "delete one entry, entry_id is %d\n",
3902 entry_id);
3903 if (mac->opmode == NL80211_IFTYPE_AP)
3904 rtl_cam_del_entry(hw, p_macaddr);
3905 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3906 } else {
3907 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3908 "add one entry\n");
3909 if (is_pairwise) {
3910 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3911 "set Pairwise key\n");
3912
3913 rtl_cam_add_one_entry(hw, macaddr, key_index,
3914 entry_id, enc_algo,
3915 CAM_CONFIG_NO_USEDK,
3916 rtlpriv->sec.key_buf[key_index]);
3917 } else {
3918 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3919 "set group key\n");
3920
3921 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3922 rtl_cam_add_one_entry(hw,
3923 rtlefuse->dev_addr,
3924 PAIRWISE_KEYIDX,
3925 CAM_PAIRWISE_KEY_POSITION,
3926 enc_algo,
3927 CAM_CONFIG_NO_USEDK,
3928 rtlpriv->sec.key_buf
3929 [entry_id]);
3930 }
3931
3932 rtl_cam_add_one_entry(hw, macaddr, key_index,
3933 entry_id, enc_algo,
3934 CAM_CONFIG_NO_USEDK,
3935 rtlpriv->sec.key_buf[entry_id]);
3936 }
3937 }
3938 }
3939 }
3940
3941 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
3942 {
3943 struct rtl_priv *rtlpriv = rtl_priv(hw);
3944
3945 /* 0:Low, 1:High, 2:From Efuse. */
3946 rtlpriv->btcoexist.reg_bt_iso = 2;
3947 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3948 rtlpriv->btcoexist.reg_bt_sco = 3;
3949 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3950 rtlpriv->btcoexist.reg_bt_sco = 0;
3951 }
3952
3953 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
3954 {
3955 struct rtl_priv *rtlpriv = rtl_priv(hw);
3956
3957 if (rtlpriv->cfg->ops->get_btc_status())
3958 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3959 }
3960
3961 void rtl8821ae_suspend(struct ieee80211_hw *hw)
3962 {
3963 }
3964
3965 void rtl8821ae_resume(struct ieee80211_hw *hw)
3966 {
3967 }
3968
3969 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
3970 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3971 bool allow_all_da, bool write_into_reg)
3972 {
3973 struct rtl_priv *rtlpriv = rtl_priv(hw);
3974 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3975
3976 if (allow_all_da) /* Set BIT0 */
3977 rtlpci->receive_config |= RCR_AAP;
3978 else /* Clear BIT0 */
3979 rtlpci->receive_config &= ~RCR_AAP;
3980
3981 if (write_into_reg)
3982 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
3983
3984 rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
3985 "receive_config=0x%08X, write_into_reg=%d\n",
3986 rtlpci->receive_config, write_into_reg);
3987 }
3988
3989 /* WKFMCAMAddAllEntry8812 */
3990 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
3991 struct rtl_wow_pattern *rtl_pattern,
3992 u8 index)
3993 {
3994 struct rtl_priv *rtlpriv = rtl_priv(hw);
3995 u32 cam = 0;
3996 u8 addr = 0;
3997 u16 rxbuf_addr;
3998 u8 tmp, count = 0;
3999 u16 cam_start;
4000 u16 offset;
4001
4002 /* Count the WFCAM entry start offset. */
4003
4004 /* RX page size = 128 byte */
4005 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4006 /* We should start from the boundry */
4007 cam_start = offset * 128;
4008
4009 /* Enable Rx packet buffer access. */
4010 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4011 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4012 /* Set Rx packet buffer offset.
4013 * RXBufer pointer increases 1,
4014 * we can access 8 bytes in Rx packet buffer.
4015 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
4016 * RXBufer addr = (CAM start offset +
4017 * per entry offset of a WKFM CAM)/8
4018 * * index: The index of the wake up frame mask
4019 * * WKFMCAM_SIZE: the total size of one WKFM CAM
4020 * * per entry offset of a WKFM CAM: Addr*4 bytes
4021 */
4022 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4023 /* Set R/W start offset */
4024 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4025
4026 if (addr == 0) {
4027 cam = BIT(31) | rtl_pattern->crc;
4028
4029 if (rtl_pattern->type == UNICAST_PATTERN)
4030 cam |= BIT(24);
4031 else if (rtl_pattern->type == MULTICAST_PATTERN)
4032 cam |= BIT(25);
4033 else if (rtl_pattern->type == BROADCAST_PATTERN)
4034 cam |= BIT(26);
4035
4036 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4037 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4038 "WRITE entry[%d] 0x%x: %x\n", addr,
4039 REG_PKTBUF_DBG_DATA_L, cam);
4040
4041 /* Write to Rx packet buffer. */
4042 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4043 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4044 cam = rtl_pattern->mask[addr - 2];
4045
4046 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4047 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4048 "WRITE entry[%d] 0x%x: %x\n", addr,
4049 REG_PKTBUF_DBG_DATA_L, cam);
4050
4051 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4052 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4053 cam = rtl_pattern->mask[addr - 2];
4054
4055 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4056 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4057 "WRITE entry[%d] 0x%x: %x\n", addr,
4058 REG_PKTBUF_DBG_DATA_H, cam);
4059
4060 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4061 }
4062
4063 count = 0;
4064 do {
4065 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4066 udelay(2);
4067 count++;
4068 } while (tmp && count < 100);
4069
4070 WARN_ONCE((count >= 100),
4071 "rtl8821ae: Write wake up frame mask FAIL %d value!\n",
4072 tmp);
4073 }
4074 /* Disable Rx packet buffer access. */
4075 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4076 DISABLE_TRXPKT_BUF_ACCESS);
4077 }
Linux with added FPC-III support