drivers/phy/marvell/phy-pxa-28nm-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Linaro, Ltd.
   4  * Rob Herring <robh@kernel.org>
   5  *
   6  * Based on vendor driver:
   7  * Copyright (C) 2013 Marvell Inc.
   8  * Author: Chao Xie <xiechao.mail@gmail.com>
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/slab.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/phy/phy.h>
  22
  23 /* USB PXA1928 PHY mapping */
  24 #define PHY_28NM_PLL_REG0                       0x0
  25 #define PHY_28NM_PLL_REG1                       0x4
  26 #define PHY_28NM_CAL_REG                        0x8
  27 #define PHY_28NM_TX_REG0                        0x0c
  28 #define PHY_28NM_TX_REG1                        0x10
  29 #define PHY_28NM_RX_REG0                        0x14
  30 #define PHY_28NM_RX_REG1                        0x18
  31 #define PHY_28NM_DIG_REG0                       0x1c
  32 #define PHY_28NM_DIG_REG1                       0x20
  33 #define PHY_28NM_TEST_REG0                      0x24
  34 #define PHY_28NM_TEST_REG1                      0x28
  35 #define PHY_28NM_MOC_REG                        0x2c
  36 #define PHY_28NM_PHY_RESERVE                    0x30
  37 #define PHY_28NM_OTG_REG                        0x34
  38 #define PHY_28NM_CHRG_DET                       0x38
  39 #define PHY_28NM_CTRL_REG0                      0xc4
  40 #define PHY_28NM_CTRL_REG1                      0xc8
  41 #define PHY_28NM_CTRL_REG2                      0xd4
  42 #define PHY_28NM_CTRL_REG3                      0xdc
  43
  44 /* PHY_28NM_PLL_REG0 */
  45 #define PHY_28NM_PLL_READY                      BIT(31)
  46
  47 #define PHY_28NM_PLL_SELLPFR_SHIFT              28
  48 #define PHY_28NM_PLL_SELLPFR_MASK               (0x3 << 28)
  49
  50 #define PHY_28NM_PLL_FBDIV_SHIFT                16
  51 #define PHY_28NM_PLL_FBDIV_MASK                 (0x1ff << 16)
  52
  53 #define PHY_28NM_PLL_ICP_SHIFT                  8
  54 #define PHY_28NM_PLL_ICP_MASK                   (0x7 << 8)
  55
  56 #define PHY_28NM_PLL_REFDIV_SHIFT               0
  57 #define PHY_28NM_PLL_REFDIV_MASK                0x7f
  58
  59 /* PHY_28NM_PLL_REG1 */
  60 #define PHY_28NM_PLL_PU_BY_REG                  BIT(1)
  61
  62 #define PHY_28NM_PLL_PU_PLL                     BIT(0)
  63
  64 /* PHY_28NM_CAL_REG */
  65 #define PHY_28NM_PLL_PLLCAL_DONE                BIT(31)
  66
  67 #define PHY_28NM_PLL_IMPCAL_DONE                BIT(23)
  68
  69 #define PHY_28NM_PLL_KVCO_SHIFT                 16
  70 #define PHY_28NM_PLL_KVCO_MASK                  (0x7 << 16)
  71
  72 #define PHY_28NM_PLL_CAL12_SHIFT                20
  73 #define PHY_28NM_PLL_CAL12_MASK                 (0x3 << 20)
  74
  75 #define PHY_28NM_IMPCAL_VTH_SHIFT               8
  76 #define PHY_28NM_IMPCAL_VTH_MASK                (0x7 << 8)
  77
  78 #define PHY_28NM_PLLCAL_START_SHIFT             22
  79 #define PHY_28NM_IMPCAL_START_SHIFT             13
  80
  81 /* PHY_28NM_TX_REG0 */
  82 #define PHY_28NM_TX_PU_BY_REG                   BIT(25)
  83
  84 #define PHY_28NM_TX_PU_ANA                      BIT(24)
  85
  86 #define PHY_28NM_TX_AMP_SHIFT                   20
  87 #define PHY_28NM_TX_AMP_MASK                    (0x7 << 20)
  88
  89 /* PHY_28NM_RX_REG0 */
  90 #define PHY_28NM_RX_SQ_THRESH_SHIFT             0
  91 #define PHY_28NM_RX_SQ_THRESH_MASK              (0xf << 0)
  92
  93 /* PHY_28NM_RX_REG1 */
  94 #define PHY_28NM_RX_SQCAL_DONE                  BIT(31)
  95
  96 /* PHY_28NM_DIG_REG0 */
  97 #define PHY_28NM_DIG_BITSTAFFING_ERR            BIT(31)
  98 #define PHY_28NM_DIG_SYNC_ERR                   BIT(30)
  99
 100 #define PHY_28NM_DIG_SQ_FILT_SHIFT              16
 101 #define PHY_28NM_DIG_SQ_FILT_MASK               (0x7 << 16)
 102
 103 #define PHY_28NM_DIG_SQ_BLK_SHIFT               12
 104 #define PHY_28NM_DIG_SQ_BLK_MASK                (0x7 << 12)
 105
 106 #define PHY_28NM_DIG_SYNC_NUM_SHIFT             0
 107 #define PHY_28NM_DIG_SYNC_NUM_MASK              (0x3 << 0)
 108
 109 #define PHY_28NM_PLL_LOCK_BYPASS                BIT(7)
 110
 111 /* PHY_28NM_OTG_REG */
 112 #define PHY_28NM_OTG_CONTROL_BY_PIN             BIT(5)
 113 #define PHY_28NM_OTG_PU_OTG                     BIT(4)
 114
 115 #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 13
 116 #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 12
 117 #define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28    10
 118 #define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28    8
 119 #define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 7
 120 #define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28     6
 121 #define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28    5
 122 #define PHY_28NM_CHGDTC_PD_EN_SHIFT_28          4
 123 #define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28         3
 124 #define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28         2
 125 #define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 0
 126
 127 #define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28    4
 128 #define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28     2
 129
 130 #define PHY_28NM_CTRL3_OVERWRITE                BIT(0)
 131 #define PHY_28NM_CTRL3_VBUS_VALID               BIT(4)
 132 #define PHY_28NM_CTRL3_AVALID                   BIT(5)
 133 #define PHY_28NM_CTRL3_BVALID                   BIT(6)
 134
 135 struct mv_usb2_phy {
 136         struct phy              *phy;
 137         struct platform_device  *pdev;
 138         void __iomem            *base;
 139         struct clk              *clk;
 140 };
 141
 142 static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
 143 {
 144         u32 val;
 145
 146         return readl_poll_timeout(reg, val, ((val & mask) == mask),
 147                                    1000, 1000 * ms);
 148 }
 149
 150 static int mv_usb2_phy_28nm_init(struct phy *phy)
 151 {
 152         struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
 153         struct platform_device *pdev = mv_phy->pdev;
 154         void __iomem *base = mv_phy->base;
 155         u32 reg;
 156         int ret;
 157
 158         clk_prepare_enable(mv_phy->clk);
 159
 160         /* PHY_28NM_PLL_REG0 */
 161         reg = readl(base + PHY_28NM_PLL_REG0) &
 162                 ~(PHY_28NM_PLL_SELLPFR_MASK | PHY_28NM_PLL_FBDIV_MASK
 163                 | PHY_28NM_PLL_ICP_MASK | PHY_28NM_PLL_REFDIV_MASK);
 164         writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT
 165                 | 0xf0 << PHY_28NM_PLL_FBDIV_SHIFT
 166                 | 0x3 << PHY_28NM_PLL_ICP_SHIFT
 167                 | 0xd << PHY_28NM_PLL_REFDIV_SHIFT),
 168                 base + PHY_28NM_PLL_REG0);
 169
 170         /* PHY_28NM_PLL_REG1 */
 171         reg = readl(base + PHY_28NM_PLL_REG1);
 172         writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG,
 173                 base + PHY_28NM_PLL_REG1);
 174
 175         /* PHY_28NM_TX_REG0 */
 176         reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK;
 177         writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT |
 178                 PHY_28NM_TX_PU_ANA,
 179                 base + PHY_28NM_TX_REG0);
 180
 181         /* PHY_28NM_RX_REG0 */
 182         reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK;
 183         writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT,
 184                 base + PHY_28NM_RX_REG0);
 185
 186         /* PHY_28NM_DIG_REG0 */
 187         reg = readl(base + PHY_28NM_DIG_REG0) &
 188                 ~(PHY_28NM_DIG_BITSTAFFING_ERR | PHY_28NM_DIG_SYNC_ERR |
 189                 PHY_28NM_DIG_SQ_FILT_MASK | PHY_28NM_DIG_SQ_BLK_MASK |
 190                 PHY_28NM_DIG_SYNC_NUM_MASK);
 191         writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT |
 192                 PHY_28NM_PLL_LOCK_BYPASS),
 193                 base + PHY_28NM_DIG_REG0);
 194
 195         /* PHY_28NM_OTG_REG */
 196         reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG;
 197         writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG);
 198
 199         /*
 200          *  Calibration Timing
 201          *                 ____________________________
 202          *  CAL START   ___|
 203          *                         ____________________
 204          *  CAL_DONE    ___________|
 205          *                 | 400us |
 206          */
 207
 208         /* Make sure PHY Calibration is ready */
 209         ret = wait_for_reg(base + PHY_28NM_CAL_REG,
 210                            PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
 211                            100);
 212         if (ret) {
 213                 dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");
 214                 goto err_clk;
 215         }
 216         ret = wait_for_reg(base + PHY_28NM_RX_REG1,
 217                            PHY_28NM_RX_SQCAL_DONE, 100);
 218         if (ret) {
 219                 dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");
 220                 goto err_clk;
 221         }
 222         /* Make sure PHY PLL is ready */
 223         ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);
 224         if (ret) {
 225                 dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");
 226                 goto err_clk;
 227         }
 228
 229         return 0;
 230 err_clk:
 231         clk_disable_unprepare(mv_phy->clk);
 232         return ret;
 233 }
 234
 235 static int mv_usb2_phy_28nm_power_on(struct phy *phy)
 236 {
 237         struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
 238         void __iomem *base = mv_phy->base;
 239
 240         writel(readl(base + PHY_28NM_CTRL_REG3) |
 241                 (PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID |
 242                 PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
 243                 base + PHY_28NM_CTRL_REG3);
 244
 245         return 0;
 246 }
 247
 248 static int mv_usb2_phy_28nm_power_off(struct phy *phy)
 249 {
 250         struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
 251         void __iomem *base = mv_phy->base;
 252
 253         writel(readl(base + PHY_28NM_CTRL_REG3) |
 254                 ~(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID
 255                 | PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
 256                 base + PHY_28NM_CTRL_REG3);
 257
 258         return 0;
 259 }
 260
 261 static int mv_usb2_phy_28nm_exit(struct phy *phy)
 262 {
 263         struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
 264         void __iomem *base = mv_phy->base;
 265         unsigned int val;
 266
 267         val = readw(base + PHY_28NM_PLL_REG1);
 268         val &= ~PHY_28NM_PLL_PU_PLL;
 269         writew(val, base + PHY_28NM_PLL_REG1);
 270
 271         /* power down PHY Analog part */
 272         val = readw(base + PHY_28NM_TX_REG0);
 273         val &= ~PHY_28NM_TX_PU_ANA;
 274         writew(val, base + PHY_28NM_TX_REG0);
 275
 276         /* power down PHY OTG part */
 277         val = readw(base + PHY_28NM_OTG_REG);
 278         val &= ~PHY_28NM_OTG_PU_OTG;
 279         writew(val, base + PHY_28NM_OTG_REG);
 280
 281         clk_disable_unprepare(mv_phy->clk);
 282         return 0;
 283 }
 284
 285 static const struct phy_ops usb_ops = {
 286         .init           = mv_usb2_phy_28nm_init,
 287         .power_on       = mv_usb2_phy_28nm_power_on,
 288         .power_off      = mv_usb2_phy_28nm_power_off,
 289         .exit           = mv_usb2_phy_28nm_exit,
 290         .owner          = THIS_MODULE,
 291 };
 292
 293 static int mv_usb2_phy_probe(struct platform_device *pdev)
 294 {
 295         struct phy_provider *phy_provider;
 296         struct mv_usb2_phy *mv_phy;
 297
 298         mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
 299         if (!mv_phy)
 300                 return -ENOMEM;
 301
 302         mv_phy->pdev = pdev;
 303
 304         mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
 305         if (IS_ERR(mv_phy->clk)) {
 306                 dev_err(&pdev->dev, "failed to get clock.\n");
 307                 return PTR_ERR(mv_phy->clk);
 308         }
 309
 310         mv_phy->base = devm_platform_ioremap_resource(pdev, 0);
 311         if (IS_ERR(mv_phy->base))
 312                 return PTR_ERR(mv_phy->base);
 313
 314         mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &usb_ops);
 315         if (IS_ERR(mv_phy->phy))
 316                 return PTR_ERR(mv_phy->phy);
 317
 318         phy_set_drvdata(mv_phy->phy, mv_phy);
 319
 320         phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
 321         return PTR_ERR_OR_ZERO(phy_provider);
 322 }
 323
 324 static const struct of_device_id mv_usbphy_dt_match[] = {
 325         { .compatible = "marvell,pxa1928-usb-phy", },
 326         {},
 327 };
 328 MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match);
 329
 330 static struct platform_driver mv_usb2_phy_driver = {
 331         .probe  = mv_usb2_phy_probe,
 332         .driver = {
 333                 .name   = "mv-usb2-phy",
 334                 .of_match_table = of_match_ptr(mv_usbphy_dt_match),
 335         },
 336 };
 337 module_platform_driver(mv_usb2_phy_driver);
 338
 339 MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
 340 MODULE_DESCRIPTION("Marvell USB2 phy driver");
 341 MODULE_LICENSE("GPL v2");