WIP FPC-III support
[linux/fpc-iii.git] / drivers / pinctrl / cirrus / pinctrl-cs47l92.c
blob4e409734334e97a593a43d0a98583d16f68af1d9
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl for Cirrus Logic CS47L92
5 * Copyright (C) 2018-2019 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
9 #include <linux/err.h>
10 #include <linux/mfd/madera/core.h>
12 #include "pinctrl-madera.h"
15 * The alt func groups are the most commonly used functions we place these at
16 * the lower function indexes for convenience, and the less commonly used gpio
17 * functions at higher indexes.
19 * To stay consistent with the datasheet the function names are the same as
20 * the group names for that function's pins
22 * Note - all 1 less than in datasheet because these are zero-indexed
24 static const unsigned int cs47l92_spk1_pins[] = { 2, 3 };
25 static const unsigned int cs47l92_aif1_pins[] = { 4, 5, 6, 7 };
26 static const unsigned int cs47l92_aif2_pins[] = { 8, 9, 10, 11 };
27 static const unsigned int cs47l92_aif3_pins[] = { 12, 13, 14, 15 };
29 static const struct madera_pin_groups cs47l92_pin_groups[] = {
30 { "aif1", cs47l92_aif1_pins, ARRAY_SIZE(cs47l92_aif1_pins) },
31 { "aif2", cs47l92_aif2_pins, ARRAY_SIZE(cs47l92_aif2_pins) },
32 { "aif3", cs47l92_aif3_pins, ARRAY_SIZE(cs47l92_aif3_pins) },
33 { "pdmspk1", cs47l92_spk1_pins, ARRAY_SIZE(cs47l92_spk1_pins) },
36 const struct madera_pin_chip cs47l92_pin_chip = {
37 .n_pins = CS47L92_NUM_GPIOS,
38 .pin_groups = cs47l92_pin_groups,
39 .n_pin_groups = ARRAY_SIZE(cs47l92_pin_groups),