?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-msm8x74.c
blob3d193acee6a374c0d2bcf104686b79f6fc4f9850
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10
11 #include "pinctrl-msm.h"
12
13 static const struct pinctrl_pin_desc msm8x74_pins[] = {
14 PINCTRL_PIN(0, "GPIO_0"),
15 PINCTRL_PIN(1, "GPIO_1"),
16 PINCTRL_PIN(2, "GPIO_2"),
17 PINCTRL_PIN(3, "GPIO_3"),
18 PINCTRL_PIN(4, "GPIO_4"),
19 PINCTRL_PIN(5, "GPIO_5"),
20 PINCTRL_PIN(6, "GPIO_6"),
21 PINCTRL_PIN(7, "GPIO_7"),
22 PINCTRL_PIN(8, "GPIO_8"),
23 PINCTRL_PIN(9, "GPIO_9"),
24 PINCTRL_PIN(10, "GPIO_10"),
25 PINCTRL_PIN(11, "GPIO_11"),
26 PINCTRL_PIN(12, "GPIO_12"),
27 PINCTRL_PIN(13, "GPIO_13"),
28 PINCTRL_PIN(14, "GPIO_14"),
29 PINCTRL_PIN(15, "GPIO_15"),
30 PINCTRL_PIN(16, "GPIO_16"),
31 PINCTRL_PIN(17, "GPIO_17"),
32 PINCTRL_PIN(18, "GPIO_18"),
33 PINCTRL_PIN(19, "GPIO_19"),
34 PINCTRL_PIN(20, "GPIO_20"),
35 PINCTRL_PIN(21, "GPIO_21"),
36 PINCTRL_PIN(22, "GPIO_22"),
37 PINCTRL_PIN(23, "GPIO_23"),
38 PINCTRL_PIN(24, "GPIO_24"),
39 PINCTRL_PIN(25, "GPIO_25"),
40 PINCTRL_PIN(26, "GPIO_26"),
41 PINCTRL_PIN(27, "GPIO_27"),
42 PINCTRL_PIN(28, "GPIO_28"),
43 PINCTRL_PIN(29, "GPIO_29"),
44 PINCTRL_PIN(30, "GPIO_30"),
45 PINCTRL_PIN(31, "GPIO_31"),
46 PINCTRL_PIN(32, "GPIO_32"),
47 PINCTRL_PIN(33, "GPIO_33"),
48 PINCTRL_PIN(34, "GPIO_34"),
49 PINCTRL_PIN(35, "GPIO_35"),
50 PINCTRL_PIN(36, "GPIO_36"),
51 PINCTRL_PIN(37, "GPIO_37"),
52 PINCTRL_PIN(38, "GPIO_38"),
53 PINCTRL_PIN(39, "GPIO_39"),
54 PINCTRL_PIN(40, "GPIO_40"),
55 PINCTRL_PIN(41, "GPIO_41"),
56 PINCTRL_PIN(42, "GPIO_42"),
57 PINCTRL_PIN(43, "GPIO_43"),
58 PINCTRL_PIN(44, "GPIO_44"),
59 PINCTRL_PIN(45, "GPIO_45"),
60 PINCTRL_PIN(46, "GPIO_46"),
61 PINCTRL_PIN(47, "GPIO_47"),
62 PINCTRL_PIN(48, "GPIO_48"),
63 PINCTRL_PIN(49, "GPIO_49"),
64 PINCTRL_PIN(50, "GPIO_50"),
65 PINCTRL_PIN(51, "GPIO_51"),
66 PINCTRL_PIN(52, "GPIO_52"),
67 PINCTRL_PIN(53, "GPIO_53"),
68 PINCTRL_PIN(54, "GPIO_54"),
69 PINCTRL_PIN(55, "GPIO_55"),
70 PINCTRL_PIN(56, "GPIO_56"),
71 PINCTRL_PIN(57, "GPIO_57"),
72 PINCTRL_PIN(58, "GPIO_58"),
73 PINCTRL_PIN(59, "GPIO_59"),
74 PINCTRL_PIN(60, "GPIO_60"),
75 PINCTRL_PIN(61, "GPIO_61"),
76 PINCTRL_PIN(62, "GPIO_62"),
77 PINCTRL_PIN(63, "GPIO_63"),
78 PINCTRL_PIN(64, "GPIO_64"),
79 PINCTRL_PIN(65, "GPIO_65"),
80 PINCTRL_PIN(66, "GPIO_66"),
81 PINCTRL_PIN(67, "GPIO_67"),
82 PINCTRL_PIN(68, "GPIO_68"),
83 PINCTRL_PIN(69, "GPIO_69"),
84 PINCTRL_PIN(70, "GPIO_70"),
85 PINCTRL_PIN(71, "GPIO_71"),
86 PINCTRL_PIN(72, "GPIO_72"),
87 PINCTRL_PIN(73, "GPIO_73"),
88 PINCTRL_PIN(74, "GPIO_74"),
89 PINCTRL_PIN(75, "GPIO_75"),
90 PINCTRL_PIN(76, "GPIO_76"),
91 PINCTRL_PIN(77, "GPIO_77"),
92 PINCTRL_PIN(78, "GPIO_78"),
93 PINCTRL_PIN(79, "GPIO_79"),
94 PINCTRL_PIN(80, "GPIO_80"),
95 PINCTRL_PIN(81, "GPIO_81"),
96 PINCTRL_PIN(82, "GPIO_82"),
97 PINCTRL_PIN(83, "GPIO_83"),
98 PINCTRL_PIN(84, "GPIO_84"),
99 PINCTRL_PIN(85, "GPIO_85"),
100 PINCTRL_PIN(86, "GPIO_86"),
101 PINCTRL_PIN(87, "GPIO_87"),
102 PINCTRL_PIN(88, "GPIO_88"),
103 PINCTRL_PIN(89, "GPIO_89"),
104 PINCTRL_PIN(90, "GPIO_90"),
105 PINCTRL_PIN(91, "GPIO_91"),
106 PINCTRL_PIN(92, "GPIO_92"),
107 PINCTRL_PIN(93, "GPIO_93"),
108 PINCTRL_PIN(94, "GPIO_94"),
109 PINCTRL_PIN(95, "GPIO_95"),
110 PINCTRL_PIN(96, "GPIO_96"),
111 PINCTRL_PIN(97, "GPIO_97"),
112 PINCTRL_PIN(98, "GPIO_98"),
113 PINCTRL_PIN(99, "GPIO_99"),
114 PINCTRL_PIN(100, "GPIO_100"),
115 PINCTRL_PIN(101, "GPIO_101"),
116 PINCTRL_PIN(102, "GPIO_102"),
117 PINCTRL_PIN(103, "GPIO_103"),
118 PINCTRL_PIN(104, "GPIO_104"),
119 PINCTRL_PIN(105, "GPIO_105"),
120 PINCTRL_PIN(106, "GPIO_106"),
121 PINCTRL_PIN(107, "GPIO_107"),
122 PINCTRL_PIN(108, "GPIO_108"),
123 PINCTRL_PIN(109, "GPIO_109"),
124 PINCTRL_PIN(110, "GPIO_110"),
125 PINCTRL_PIN(111, "GPIO_111"),
126 PINCTRL_PIN(112, "GPIO_112"),
127 PINCTRL_PIN(113, "GPIO_113"),
128 PINCTRL_PIN(114, "GPIO_114"),
129 PINCTRL_PIN(115, "GPIO_115"),
130 PINCTRL_PIN(116, "GPIO_116"),
131 PINCTRL_PIN(117, "GPIO_117"),
132 PINCTRL_PIN(118, "GPIO_118"),
133 PINCTRL_PIN(119, "GPIO_119"),
134 PINCTRL_PIN(120, "GPIO_120"),
135 PINCTRL_PIN(121, "GPIO_121"),
136 PINCTRL_PIN(122, "GPIO_122"),
137 PINCTRL_PIN(123, "GPIO_123"),
138 PINCTRL_PIN(124, "GPIO_124"),
139 PINCTRL_PIN(125, "GPIO_125"),
140 PINCTRL_PIN(126, "GPIO_126"),
141 PINCTRL_PIN(127, "GPIO_127"),
142 PINCTRL_PIN(128, "GPIO_128"),
143 PINCTRL_PIN(129, "GPIO_129"),
144 PINCTRL_PIN(130, "GPIO_130"),
145 PINCTRL_PIN(131, "GPIO_131"),
146 PINCTRL_PIN(132, "GPIO_132"),
147 PINCTRL_PIN(133, "GPIO_133"),
148 PINCTRL_PIN(134, "GPIO_134"),
149 PINCTRL_PIN(135, "GPIO_135"),
150 PINCTRL_PIN(136, "GPIO_136"),
151 PINCTRL_PIN(137, "GPIO_137"),
152 PINCTRL_PIN(138, "GPIO_138"),
153 PINCTRL_PIN(139, "GPIO_139"),
154 PINCTRL_PIN(140, "GPIO_140"),
155 PINCTRL_PIN(141, "GPIO_141"),
156 PINCTRL_PIN(142, "GPIO_142"),
157 PINCTRL_PIN(143, "GPIO_143"),
158 PINCTRL_PIN(144, "GPIO_144"),
159 PINCTRL_PIN(145, "GPIO_145"),
160
161 PINCTRL_PIN(146, "SDC1_CLK"),
162 PINCTRL_PIN(147, "SDC1_CMD"),
163 PINCTRL_PIN(148, "SDC1_DATA"),
164 PINCTRL_PIN(149, "SDC2_CLK"),
165 PINCTRL_PIN(150, "SDC2_CMD"),
166 PINCTRL_PIN(151, "SDC2_DATA"),
167 PINCTRL_PIN(152, "HSIC_STROBE"),
168 PINCTRL_PIN(153, "HSIC_DATA"),
169 };
170
171 #define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
172 DECLARE_MSM_GPIO_PINS(0);
173 DECLARE_MSM_GPIO_PINS(1);
174 DECLARE_MSM_GPIO_PINS(2);
175 DECLARE_MSM_GPIO_PINS(3);
176 DECLARE_MSM_GPIO_PINS(4);
177 DECLARE_MSM_GPIO_PINS(5);
178 DECLARE_MSM_GPIO_PINS(6);
179 DECLARE_MSM_GPIO_PINS(7);
180 DECLARE_MSM_GPIO_PINS(8);
181 DECLARE_MSM_GPIO_PINS(9);
182 DECLARE_MSM_GPIO_PINS(10);
183 DECLARE_MSM_GPIO_PINS(11);
184 DECLARE_MSM_GPIO_PINS(12);
185 DECLARE_MSM_GPIO_PINS(13);
186 DECLARE_MSM_GPIO_PINS(14);
187 DECLARE_MSM_GPIO_PINS(15);
188 DECLARE_MSM_GPIO_PINS(16);
189 DECLARE_MSM_GPIO_PINS(17);
190 DECLARE_MSM_GPIO_PINS(18);
191 DECLARE_MSM_GPIO_PINS(19);
192 DECLARE_MSM_GPIO_PINS(20);
193 DECLARE_MSM_GPIO_PINS(21);
194 DECLARE_MSM_GPIO_PINS(22);
195 DECLARE_MSM_GPIO_PINS(23);
196 DECLARE_MSM_GPIO_PINS(24);
197 DECLARE_MSM_GPIO_PINS(25);
198 DECLARE_MSM_GPIO_PINS(26);
199 DECLARE_MSM_GPIO_PINS(27);
200 DECLARE_MSM_GPIO_PINS(28);
201 DECLARE_MSM_GPIO_PINS(29);
202 DECLARE_MSM_GPIO_PINS(30);
203 DECLARE_MSM_GPIO_PINS(31);
204 DECLARE_MSM_GPIO_PINS(32);
205 DECLARE_MSM_GPIO_PINS(33);
206 DECLARE_MSM_GPIO_PINS(34);
207 DECLARE_MSM_GPIO_PINS(35);
208 DECLARE_MSM_GPIO_PINS(36);
209 DECLARE_MSM_GPIO_PINS(37);
210 DECLARE_MSM_GPIO_PINS(38);
211 DECLARE_MSM_GPIO_PINS(39);
212 DECLARE_MSM_GPIO_PINS(40);
213 DECLARE_MSM_GPIO_PINS(41);
214 DECLARE_MSM_GPIO_PINS(42);
215 DECLARE_MSM_GPIO_PINS(43);
216 DECLARE_MSM_GPIO_PINS(44);
217 DECLARE_MSM_GPIO_PINS(45);
218 DECLARE_MSM_GPIO_PINS(46);
219 DECLARE_MSM_GPIO_PINS(47);
220 DECLARE_MSM_GPIO_PINS(48);
221 DECLARE_MSM_GPIO_PINS(49);
222 DECLARE_MSM_GPIO_PINS(50);
223 DECLARE_MSM_GPIO_PINS(51);
224 DECLARE_MSM_GPIO_PINS(52);
225 DECLARE_MSM_GPIO_PINS(53);
226 DECLARE_MSM_GPIO_PINS(54);
227 DECLARE_MSM_GPIO_PINS(55);
228 DECLARE_MSM_GPIO_PINS(56);
229 DECLARE_MSM_GPIO_PINS(57);
230 DECLARE_MSM_GPIO_PINS(58);
231 DECLARE_MSM_GPIO_PINS(59);
232 DECLARE_MSM_GPIO_PINS(60);
233 DECLARE_MSM_GPIO_PINS(61);
234 DECLARE_MSM_GPIO_PINS(62);
235 DECLARE_MSM_GPIO_PINS(63);
236 DECLARE_MSM_GPIO_PINS(64);
237 DECLARE_MSM_GPIO_PINS(65);
238 DECLARE_MSM_GPIO_PINS(66);
239 DECLARE_MSM_GPIO_PINS(67);
240 DECLARE_MSM_GPIO_PINS(68);
241 DECLARE_MSM_GPIO_PINS(69);
242 DECLARE_MSM_GPIO_PINS(70);
243 DECLARE_MSM_GPIO_PINS(71);
244 DECLARE_MSM_GPIO_PINS(72);
245 DECLARE_MSM_GPIO_PINS(73);
246 DECLARE_MSM_GPIO_PINS(74);
247 DECLARE_MSM_GPIO_PINS(75);
248 DECLARE_MSM_GPIO_PINS(76);
249 DECLARE_MSM_GPIO_PINS(77);
250 DECLARE_MSM_GPIO_PINS(78);
251 DECLARE_MSM_GPIO_PINS(79);
252 DECLARE_MSM_GPIO_PINS(80);
253 DECLARE_MSM_GPIO_PINS(81);
254 DECLARE_MSM_GPIO_PINS(82);
255 DECLARE_MSM_GPIO_PINS(83);
256 DECLARE_MSM_GPIO_PINS(84);
257 DECLARE_MSM_GPIO_PINS(85);
258 DECLARE_MSM_GPIO_PINS(86);
259 DECLARE_MSM_GPIO_PINS(87);
260 DECLARE_MSM_GPIO_PINS(88);
261 DECLARE_MSM_GPIO_PINS(89);
262 DECLARE_MSM_GPIO_PINS(90);
263 DECLARE_MSM_GPIO_PINS(91);
264 DECLARE_MSM_GPIO_PINS(92);
265 DECLARE_MSM_GPIO_PINS(93);
266 DECLARE_MSM_GPIO_PINS(94);
267 DECLARE_MSM_GPIO_PINS(95);
268 DECLARE_MSM_GPIO_PINS(96);
269 DECLARE_MSM_GPIO_PINS(97);
270 DECLARE_MSM_GPIO_PINS(98);
271 DECLARE_MSM_GPIO_PINS(99);
272 DECLARE_MSM_GPIO_PINS(100);
273 DECLARE_MSM_GPIO_PINS(101);
274 DECLARE_MSM_GPIO_PINS(102);
275 DECLARE_MSM_GPIO_PINS(103);
276 DECLARE_MSM_GPIO_PINS(104);
277 DECLARE_MSM_GPIO_PINS(105);
278 DECLARE_MSM_GPIO_PINS(106);
279 DECLARE_MSM_GPIO_PINS(107);
280 DECLARE_MSM_GPIO_PINS(108);
281 DECLARE_MSM_GPIO_PINS(109);
282 DECLARE_MSM_GPIO_PINS(110);
283 DECLARE_MSM_GPIO_PINS(111);
284 DECLARE_MSM_GPIO_PINS(112);
285 DECLARE_MSM_GPIO_PINS(113);
286 DECLARE_MSM_GPIO_PINS(114);
287 DECLARE_MSM_GPIO_PINS(115);
288 DECLARE_MSM_GPIO_PINS(116);
289 DECLARE_MSM_GPIO_PINS(117);
290 DECLARE_MSM_GPIO_PINS(118);
291 DECLARE_MSM_GPIO_PINS(119);
292 DECLARE_MSM_GPIO_PINS(120);
293 DECLARE_MSM_GPIO_PINS(121);
294 DECLARE_MSM_GPIO_PINS(122);
295 DECLARE_MSM_GPIO_PINS(123);
296 DECLARE_MSM_GPIO_PINS(124);
297 DECLARE_MSM_GPIO_PINS(125);
298 DECLARE_MSM_GPIO_PINS(126);
299 DECLARE_MSM_GPIO_PINS(127);
300 DECLARE_MSM_GPIO_PINS(128);
301 DECLARE_MSM_GPIO_PINS(129);
302 DECLARE_MSM_GPIO_PINS(130);
303 DECLARE_MSM_GPIO_PINS(131);
304 DECLARE_MSM_GPIO_PINS(132);
305 DECLARE_MSM_GPIO_PINS(133);
306 DECLARE_MSM_GPIO_PINS(134);
307 DECLARE_MSM_GPIO_PINS(135);
308 DECLARE_MSM_GPIO_PINS(136);
309 DECLARE_MSM_GPIO_PINS(137);
310 DECLARE_MSM_GPIO_PINS(138);
311 DECLARE_MSM_GPIO_PINS(139);
312 DECLARE_MSM_GPIO_PINS(140);
313 DECLARE_MSM_GPIO_PINS(141);
314 DECLARE_MSM_GPIO_PINS(142);
315 DECLARE_MSM_GPIO_PINS(143);
316 DECLARE_MSM_GPIO_PINS(144);
317 DECLARE_MSM_GPIO_PINS(145);
318
319 static const unsigned int sdc1_clk_pins[] = { 146 };
320 static const unsigned int sdc1_cmd_pins[] = { 147 };
321 static const unsigned int sdc1_data_pins[] = { 148 };
322 static const unsigned int sdc2_clk_pins[] = { 149 };
323 static const unsigned int sdc2_cmd_pins[] = { 150 };
324 static const unsigned int sdc2_data_pins[] = { 151 };
325 static const unsigned int hsic_strobe_pins[] = { 152 };
326 static const unsigned int hsic_data_pins[] = { 153 };
327
328 #define FUNCTION(fname) \
329 [MSM_MUX_##fname] = { \
330 .name = #fname, \
331 .groups = fname##_groups, \
332 .ngroups = ARRAY_SIZE(fname##_groups), \
333 }
334
335 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
336 { \
337 .name = "gpio" #id, \
338 .pins = gpio##id##_pins, \
339 .npins = ARRAY_SIZE(gpio##id##_pins), \
340 .funcs = (int[]){ \
341 MSM_MUX_gpio, \
342 MSM_MUX_##f1, \
343 MSM_MUX_##f2, \
344 MSM_MUX_##f3, \
345 MSM_MUX_##f4, \
346 MSM_MUX_##f5, \
347 MSM_MUX_##f6, \
348 MSM_MUX_##f7 \
349 }, \
350 .nfuncs = 8, \
351 .ctl_reg = 0x1000 + 0x10 * id, \
352 .io_reg = 0x1004 + 0x10 * id, \
353 .intr_cfg_reg = 0x1008 + 0x10 * id, \
354 .intr_status_reg = 0x100c + 0x10 * id, \
355 .intr_target_reg = 0x1008 + 0x10 * id, \
356 .mux_bit = 2, \
357 .pull_bit = 0, \
358 .drv_bit = 6, \
359 .oe_bit = 9, \
360 .in_bit = 0, \
361 .out_bit = 1, \
362 .intr_enable_bit = 0, \
363 .intr_status_bit = 0, \
364 .intr_target_bit = 5, \
365 .intr_target_kpss_val = 4, \
366 .intr_raw_status_bit = 4, \
367 .intr_polarity_bit = 1, \
368 .intr_detection_bit = 2, \
369 .intr_detection_width = 2, \
370 }
371
372 #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
373 { \
374 .name = #pg_name, \
375 .pins = pg_name##_pins, \
376 .npins = ARRAY_SIZE(pg_name##_pins), \
377 .ctl_reg = ctl, \
378 .io_reg = 0, \
379 .intr_cfg_reg = 0, \
380 .intr_status_reg = 0, \
381 .intr_target_reg = 0, \
382 .mux_bit = -1, \
383 .pull_bit = pull, \
384 .drv_bit = drv, \
385 .oe_bit = -1, \
386 .in_bit = -1, \
387 .out_bit = -1, \
388 .intr_enable_bit = -1, \
389 .intr_status_bit = -1, \
390 .intr_target_bit = -1, \
391 .intr_target_kpss_val = -1, \
392 .intr_raw_status_bit = -1, \
393 .intr_polarity_bit = -1, \
394 .intr_detection_bit = -1, \
395 .intr_detection_width = -1, \
396 }
397
398 #define HSIC_PINGROUP(pg_name, ctl) \
399 { \
400 .name = #pg_name, \
401 .pins = pg_name##_pins, \
402 .npins = ARRAY_SIZE(pg_name##_pins), \
403 .funcs = (int[]){ \
404 MSM_MUX_gpio, \
405 MSM_MUX_hsic_ctl, \
406 }, \
407 .nfuncs = 2, \
408 .ctl_reg = ctl, \
409 .io_reg = 0, \
410 .intr_cfg_reg = 0, \
411 .intr_status_reg = 0, \
412 .intr_target_reg = 0, \
413 .mux_bit = 25, \
414 .pull_bit = -1, \
415 .drv_bit = -1, \
416 .oe_bit = -1, \
417 .in_bit = -1, \
418 .out_bit = -1, \
419 .intr_enable_bit = -1, \
420 .intr_status_bit = -1, \
421 .intr_target_bit = -1, \
422 .intr_target_kpss_val = -1, \
423 .intr_raw_status_bit = -1, \
424 .intr_polarity_bit = -1, \
425 .intr_detection_bit = -1, \
426 .intr_detection_width = -1, \
427 }
428
429 /*
430 * TODO: Add the rest of the possible functions and fill out
431 * the pingroup table below.
432 */
433 enum msm8x74_functions {
434 MSM_MUX_gpio,
435 MSM_MUX_cci_i2c0,
436 MSM_MUX_cci_i2c1,
437 MSM_MUX_blsp_i2c1,
438 MSM_MUX_blsp_i2c2,
439 MSM_MUX_blsp_i2c3,
440 MSM_MUX_blsp_i2c4,
441 MSM_MUX_blsp_i2c5,
442 MSM_MUX_blsp_i2c6,
443 MSM_MUX_blsp_i2c7,
444 MSM_MUX_blsp_i2c8,
445 MSM_MUX_blsp_i2c9,
446 MSM_MUX_blsp_i2c10,
447 MSM_MUX_blsp_i2c11,
448 MSM_MUX_blsp_i2c12,
449 MSM_MUX_blsp_spi1,
450 MSM_MUX_blsp_spi1_cs1,
451 MSM_MUX_blsp_spi1_cs2,
452 MSM_MUX_blsp_spi1_cs3,
453 MSM_MUX_blsp_spi2,
454 MSM_MUX_blsp_spi2_cs1,
455 MSM_MUX_blsp_spi2_cs2,
456 MSM_MUX_blsp_spi2_cs3,
457 MSM_MUX_blsp_spi3,
458 MSM_MUX_blsp_spi4,
459 MSM_MUX_blsp_spi5,
460 MSM_MUX_blsp_spi6,
461 MSM_MUX_blsp_spi7,
462 MSM_MUX_blsp_spi8,
463 MSM_MUX_blsp_spi9,
464 MSM_MUX_blsp_spi10,
465 MSM_MUX_blsp_spi10_cs1,
466 MSM_MUX_blsp_spi10_cs2,
467 MSM_MUX_blsp_spi10_cs3,
468 MSM_MUX_blsp_spi11,
469 MSM_MUX_blsp_spi12,
470 MSM_MUX_blsp_uart1,
471 MSM_MUX_blsp_uart2,
472 MSM_MUX_blsp_uart3,
473 MSM_MUX_blsp_uart4,
474 MSM_MUX_blsp_uart5,
475 MSM_MUX_blsp_uart6,
476 MSM_MUX_blsp_uart7,
477 MSM_MUX_blsp_uart8,
478 MSM_MUX_blsp_uart9,
479 MSM_MUX_blsp_uart10,
480 MSM_MUX_blsp_uart11,
481 MSM_MUX_blsp_uart12,
482 MSM_MUX_blsp_uim1,
483 MSM_MUX_blsp_uim2,
484 MSM_MUX_blsp_uim3,
485 MSM_MUX_blsp_uim4,
486 MSM_MUX_blsp_uim5,
487 MSM_MUX_blsp_uim6,
488 MSM_MUX_blsp_uim7,
489 MSM_MUX_blsp_uim8,
490 MSM_MUX_blsp_uim9,
491 MSM_MUX_blsp_uim10,
492 MSM_MUX_blsp_uim11,
493 MSM_MUX_blsp_uim12,
494 MSM_MUX_uim1,
495 MSM_MUX_uim2,
496 MSM_MUX_uim_batt_alarm,
497 MSM_MUX_sdc3,
498 MSM_MUX_sdc4,
499 MSM_MUX_gcc_gp_clk1,
500 MSM_MUX_gcc_gp_clk2,
501 MSM_MUX_gcc_gp_clk3,
502 MSM_MUX_qua_mi2s,
503 MSM_MUX_pri_mi2s,
504 MSM_MUX_spkr_mi2s,
505 MSM_MUX_ter_mi2s,
506 MSM_MUX_sec_mi2s,
507 MSM_MUX_hdmi_cec,
508 MSM_MUX_hdmi_ddc,
509 MSM_MUX_hdmi_hpd,
510 MSM_MUX_edp_hpd,
511 MSM_MUX_mdp_vsync,
512 MSM_MUX_cam_mclk0,
513 MSM_MUX_cam_mclk1,
514 MSM_MUX_cam_mclk2,
515 MSM_MUX_cam_mclk3,
516 MSM_MUX_cci_timer0,
517 MSM_MUX_cci_timer1,
518 MSM_MUX_cci_timer2,
519 MSM_MUX_cci_timer3,
520 MSM_MUX_cci_timer4,
521 MSM_MUX_cci_async_in0,
522 MSM_MUX_cci_async_in1,
523 MSM_MUX_cci_async_in2,
524 MSM_MUX_gp_pdm0,
525 MSM_MUX_gp_pdm1,
526 MSM_MUX_gp_pdm2,
527 MSM_MUX_gp0_clk,
528 MSM_MUX_gp1_clk,
529 MSM_MUX_gp_mn,
530 MSM_MUX_tsif1,
531 MSM_MUX_tsif2,
532 MSM_MUX_hsic,
533 MSM_MUX_grfc,
534 MSM_MUX_audio_ref_clk,
535 MSM_MUX_bt,
536 MSM_MUX_fm,
537 MSM_MUX_wlan,
538 MSM_MUX_slimbus,
539 MSM_MUX_hsic_ctl,
540 MSM_MUX_NA,
541 };
542
543 static const char * const gpio_groups[] = {
544 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
545 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
546 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
547 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
548 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
549 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
550 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
551 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
552 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
553 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
554 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
555 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
556 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
557 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
558 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
559 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
560 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
561 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
562 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
563 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
564 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
565 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "hsic_data",
566 "hsic_strobe",
567 };
568
569 static const char * const blsp_uart1_groups[] = {
570 "gpio0", "gpio1", "gpio2", "gpio3"
571 };
572 static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
573 static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
574 static const char * const blsp_spi1_groups[] = {
575 "gpio0", "gpio1", "gpio2", "gpio3"
576 };
577 static const char * const blsp_spi1_cs1_groups[] = { "gpio8" };
578 static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" };
579 static const char * const blsp_spi1_cs3_groups[] = { "gpio10" };
580
581 static const char * const blsp_uart2_groups[] = {
582 "gpio4", "gpio5", "gpio6", "gpio7"
583 };
584 static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
585 static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
586 static const char * const blsp_spi2_groups[] = {
587 "gpio4", "gpio5", "gpio6", "gpio7"
588 };
589 static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" };
590 static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" };
591 static const char * const blsp_spi2_cs3_groups[] = { "gpio66" };
592
593 static const char * const blsp_uart3_groups[] = {
594 "gpio8", "gpio9", "gpio10", "gpio11"
595 };
596 static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
597 static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
598 static const char * const blsp_spi3_groups[] = {
599 "gpio8", "gpio9", "gpio10", "gpio11"
600 };
601
602 static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" };
603 static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" };
604
605 static const char * const blsp_uart4_groups[] = {
606 "gpio19", "gpio20", "gpio21", "gpio22"
607 };
608 static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" };
609 static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" };
610 static const char * const blsp_spi4_groups[] = {
611 "gpio19", "gpio20", "gpio21", "gpio22"
612 };
613
614 static const char * const blsp_uart5_groups[] = {
615 "gpio23", "gpio24", "gpio25", "gpio26"
616 };
617 static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" };
618 static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" };
619 static const char * const blsp_spi5_groups[] = {
620 "gpio23", "gpio24", "gpio25", "gpio26"
621 };
622
623 static const char * const blsp_uart6_groups[] = {
624 "gpio27", "gpio28", "gpio29", "gpio30"
625 };
626 static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" };
627 static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
628 static const char * const blsp_spi6_groups[] = {
629 "gpio27", "gpio28", "gpio29", "gpio30"
630 };
631
632 static const char * const blsp_uart7_groups[] = {
633 "gpio41", "gpio42", "gpio43", "gpio44"
634 };
635 static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" };
636 static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" };
637 static const char * const blsp_spi7_groups[] = {
638 "gpio41", "gpio42", "gpio43", "gpio44"
639 };
640
641 static const char * const blsp_uart8_groups[] = {
642 "gpio45", "gpio46", "gpio47", "gpio48"
643 };
644 static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" };
645 static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" };
646 static const char * const blsp_spi8_groups[] = {
647 "gpio45", "gpio46", "gpio47", "gpio48"
648 };
649
650 static const char * const blsp_uart9_groups[] = {
651 "gpio49", "gpio50", "gpio51", "gpio52"
652 };
653 static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" };
654 static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" };
655 static const char * const blsp_spi9_groups[] = {
656 "gpio49", "gpio50", "gpio51", "gpio52"
657 };
658
659 static const char * const blsp_uart10_groups[] = {
660 "gpio53", "gpio54", "gpio55", "gpio56"
661 };
662 static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" };
663 static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" };
664 static const char * const blsp_spi10_groups[] = {
665 "gpio53", "gpio54", "gpio55", "gpio56"
666 };
667 static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" };
668 static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" };
669 static const char * const blsp_spi10_cs3_groups[] = { "gpio90" };
670
671 static const char * const blsp_uart11_groups[] = {
672 "gpio81", "gpio82", "gpio83", "gpio84"
673 };
674 static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" };
675 static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
676 static const char * const blsp_spi11_groups[] = {
677 "gpio81", "gpio82", "gpio83", "gpio84"
678 };
679
680 static const char * const blsp_uart12_groups[] = {
681 "gpio85", "gpio86", "gpio87", "gpio88"
682 };
683 static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" };
684 static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" };
685 static const char * const blsp_spi12_groups[] = {
686 "gpio85", "gpio86", "gpio87", "gpio88"
687 };
688
689 static const char * const uim1_groups[] = {
690 "gpio97", "gpio98", "gpio99", "gpio100"
691 };
692
693 static const char * const uim2_groups[] = {
694 "gpio49", "gpio50", "gpio51", "gpio52"
695 };
696
697 static const char * const uim_batt_alarm_groups[] = { "gpio101" };
698
699 static const char * const sdc3_groups[] = {
700 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
701 };
702
703 static const char * const sdc4_groups[] = {
704 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96"
705 };
706
707 static const char * const gp0_clk_groups[] = { "gpio26" };
708 static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" };
709 static const char * const gp_mn_groups[] = { "gpio29" };
710 static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" };
711 static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" };
712 static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" };
713
714 static const char * const qua_mi2s_groups[] = {
715 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
716 };
717
718 static const char * const pri_mi2s_groups[] = {
719 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
720 };
721
722 static const char * const spkr_mi2s_groups[] = {
723 "gpio69", "gpio70", "gpio71", "gpio72"
724 };
725
726 static const char * const ter_mi2s_groups[] = {
727 "gpio73", "gpio74", "gpio75", "gpio76", "gpio77"
728 };
729
730 static const char * const sec_mi2s_groups[] = {
731 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
732 };
733
734 static const char * const hdmi_cec_groups[] = { "gpio31" };
735 static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" };
736 static const char * const hdmi_hpd_groups[] = { "gpio34" };
737 static const char * const edp_hpd_groups[] = { "gpio102" };
738
739 static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" };
740 static const char * const cam_mclk0_groups[] = { "gpio15" };
741 static const char * const cam_mclk1_groups[] = { "gpio16" };
742 static const char * const cam_mclk2_groups[] = { "gpio17" };
743 static const char * const cam_mclk3_groups[] = { "gpio18" };
744
745 static const char * const cci_timer0_groups[] = { "gpio23" };
746 static const char * const cci_timer1_groups[] = { "gpio24" };
747 static const char * const cci_timer2_groups[] = { "gpio25" };
748 static const char * const cci_timer3_groups[] = { "gpio26" };
749 static const char * const cci_timer4_groups[] = { "gpio27" };
750 static const char * const cci_async_in0_groups[] = { "gpio28" };
751 static const char * const cci_async_in1_groups[] = { "gpio26" };
752 static const char * const cci_async_in2_groups[] = { "gpio27" };
753
754 static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" };
755 static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" };
756 static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" };
757
758 static const char * const tsif1_groups[] = {
759 "gpio89", "gpio90", "gpio91", "gpio92"
760 };
761
762 static const char * const tsif2_groups[] = {
763 "gpio93", "gpio94", "gpio95", "gpio96"
764 };
765
766 static const char * const hsic_groups[] = { "gpio144", "gpio145" };
767 static const char * const grfc_groups[] = {
768 "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
769 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
770 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
771 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
772 "gpio128", "gpio136", "gpio137", "gpio141", "gpio143"
773 };
774
775 static const char * const audio_ref_clk_groups[] = { "gpio69" };
776
777 static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" };
778
779 static const char * const fm_groups[] = { "gpio41", "gpio42" };
780
781 static const char * const wlan_groups[] = {
782 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
783 };
784
785 static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
786 static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" };
787
788 static const struct msm_function msm8x74_functions[] = {
789 FUNCTION(gpio),
790 FUNCTION(cci_i2c0),
791 FUNCTION(cci_i2c1),
792 FUNCTION(uim1),
793 FUNCTION(uim2),
794 FUNCTION(uim_batt_alarm),
795 FUNCTION(blsp_uim1),
796 FUNCTION(blsp_uim2),
797 FUNCTION(blsp_uim3),
798 FUNCTION(blsp_uim4),
799 FUNCTION(blsp_uim5),
800 FUNCTION(blsp_uim6),
801 FUNCTION(blsp_uim7),
802 FUNCTION(blsp_uim8),
803 FUNCTION(blsp_uim9),
804 FUNCTION(blsp_uim10),
805 FUNCTION(blsp_uim11),
806 FUNCTION(blsp_uim12),
807 FUNCTION(blsp_i2c1),
808 FUNCTION(blsp_i2c2),
809 FUNCTION(blsp_i2c3),
810 FUNCTION(blsp_i2c4),
811 FUNCTION(blsp_i2c5),
812 FUNCTION(blsp_i2c6),
813 FUNCTION(blsp_i2c7),
814 FUNCTION(blsp_i2c8),
815 FUNCTION(blsp_i2c9),
816 FUNCTION(blsp_i2c10),
817 FUNCTION(blsp_i2c11),
818 FUNCTION(blsp_i2c12),
819 FUNCTION(blsp_spi1),
820 FUNCTION(blsp_spi1_cs1),
821 FUNCTION(blsp_spi1_cs2),
822 FUNCTION(blsp_spi1_cs3),
823 FUNCTION(blsp_spi2),
824 FUNCTION(blsp_spi2_cs1),
825 FUNCTION(blsp_spi2_cs2),
826 FUNCTION(blsp_spi2_cs3),
827 FUNCTION(blsp_spi3),
828 FUNCTION(blsp_spi4),
829 FUNCTION(blsp_spi5),
830 FUNCTION(blsp_spi6),
831 FUNCTION(blsp_spi7),
832 FUNCTION(blsp_spi8),
833 FUNCTION(blsp_spi9),
834 FUNCTION(blsp_spi10),
835 FUNCTION(blsp_spi10_cs1),
836 FUNCTION(blsp_spi10_cs2),
837 FUNCTION(blsp_spi10_cs3),
838 FUNCTION(blsp_spi11),
839 FUNCTION(blsp_spi12),
840 FUNCTION(blsp_uart1),
841 FUNCTION(blsp_uart2),
842 FUNCTION(blsp_uart3),
843 FUNCTION(blsp_uart4),
844 FUNCTION(blsp_uart5),
845 FUNCTION(blsp_uart6),
846 FUNCTION(blsp_uart7),
847 FUNCTION(blsp_uart8),
848 FUNCTION(blsp_uart9),
849 FUNCTION(blsp_uart10),
850 FUNCTION(blsp_uart11),
851 FUNCTION(blsp_uart12),
852 FUNCTION(sdc3),
853 FUNCTION(sdc4),
854 FUNCTION(gcc_gp_clk1),
855 FUNCTION(gcc_gp_clk2),
856 FUNCTION(gcc_gp_clk3),
857 FUNCTION(qua_mi2s),
858 FUNCTION(pri_mi2s),
859 FUNCTION(spkr_mi2s),
860 FUNCTION(ter_mi2s),
861 FUNCTION(sec_mi2s),
862 FUNCTION(mdp_vsync),
863 FUNCTION(cam_mclk0),
864 FUNCTION(cam_mclk1),
865 FUNCTION(cam_mclk2),
866 FUNCTION(cam_mclk3),
867 FUNCTION(cci_timer0),
868 FUNCTION(cci_timer1),
869 FUNCTION(cci_timer2),
870 FUNCTION(cci_timer3),
871 FUNCTION(cci_timer4),
872 FUNCTION(cci_async_in0),
873 FUNCTION(cci_async_in1),
874 FUNCTION(cci_async_in2),
875 FUNCTION(hdmi_cec),
876 FUNCTION(hdmi_ddc),
877 FUNCTION(hdmi_hpd),
878 FUNCTION(edp_hpd),
879 FUNCTION(gp_pdm0),
880 FUNCTION(gp_pdm1),
881 FUNCTION(gp_pdm2),
882 FUNCTION(gp0_clk),
883 FUNCTION(gp1_clk),
884 FUNCTION(gp_mn),
885 FUNCTION(tsif1),
886 FUNCTION(tsif2),
887 FUNCTION(hsic),
888 FUNCTION(grfc),
889 FUNCTION(audio_ref_clk),
890 FUNCTION(bt),
891 FUNCTION(fm),
892 FUNCTION(wlan),
893 FUNCTION(slimbus),
894 FUNCTION(hsic_ctl),
895 };
896
897 static const struct msm_pingroup msm8x74_groups[] = {
898 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
899 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
900 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
901 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
902 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
903 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
904 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
905 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
906 PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA),
907 PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA),
908 PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA),
909 PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA),
910 PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
911 PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
912 PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
913 PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
914 PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
915 PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
916 PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
917 PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
918 PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
919 PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
920 PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
921 PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
922 PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
923 PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA),
924 PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA),
925 PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA),
926 PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA),
927 PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA),
928 PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
929 PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
930 PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
931 PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
932 PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA),
933 PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA),
934 PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA),
935 PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA),
936 PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA),
937 PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA),
938 PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA),
939 PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
940 PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
941 PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
942 PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
943 PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
944 PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
945 PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA),
946 PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA),
947 PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
948 PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
949 PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
950 PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
951 PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA),
952 PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA),
953 PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
954 PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
955 PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
956 PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA),
957 PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA),
958 PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA),
959 PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA),
960 PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA),
961 PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA),
962 PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA),
963 PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA),
964 PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA),
965 PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA),
966 PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA),
967 PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA),
968 PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
969 PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
970 PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA),
971 PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA),
972 PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA),
973 PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA),
974 PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA),
975 PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA),
976 PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
977 PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA),
978 PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA),
979 PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA),
980 PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA),
981 PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
982 PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
983 PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
984 PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA),
985 PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
986 PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
987 PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA),
988 PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA),
989 PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA),
990 PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA),
991 PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA),
992 PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA),
993 PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA),
994 PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA),
995 PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA),
996 PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA),
997 PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA),
998 PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA),
999 PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
1000 PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA),
1001 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
1002 PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA),
1003 PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA),
1004 PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA),
1005 PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA),
1006 PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA),
1007 PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA),
1008 PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA),
1009 PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA),
1010 PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA),
1011 PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA),
1012 PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA),
1013 PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA),
1014 PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA),
1015 PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA),
1016 PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA),
1017 PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA),
1018 PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA),
1019 PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA),
1020 PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA),
1021 PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA),
1022 PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA),
1023 PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA),
1024 PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA),
1025 PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA),
1026 PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA),
1027 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA),
1028 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA),
1029 PINGROUP(131, NA, NA, NA, NA, NA, NA, NA),
1030 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA),
1031 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA),
1032 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA),
1033 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA),
1034 PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA),
1035 PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA),
1036 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
1037 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
1038 PINGROUP(140, NA, NA, NA, NA, NA, NA, NA),
1039 PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA),
1040 PINGROUP(142, NA, NA, NA, NA, NA, NA, NA),
1041 PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA),
1042 PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA),
1043 PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA),
1044 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
1045 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
1046 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
1047 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
1048 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
1049 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
1050 HSIC_PINGROUP(hsic_strobe, 0x2050),
1051 HSIC_PINGROUP(hsic_data, 0x2054),
1052 };
1053
1054 #define NUM_GPIO_PINGROUPS 146
1055
1056 static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
1057 .pins = msm8x74_pins,
1058 .npins = ARRAY_SIZE(msm8x74_pins),
1059 .functions = msm8x74_functions,
1060 .nfunctions = ARRAY_SIZE(msm8x74_functions),
1061 .groups = msm8x74_groups,
1062 .ngroups = ARRAY_SIZE(msm8x74_groups),
1063 .ngpios = NUM_GPIO_PINGROUPS,
1064 };
1065
1066 static int msm8x74_pinctrl_probe(struct platform_device *pdev)
1067 {
1068 return msm_pinctrl_probe(pdev, &msm8x74_pinctrl);
1069 }
1070
1071 static const struct of_device_id msm8x74_pinctrl_of_match[] = {
1072 { .compatible = "qcom,msm8974-pinctrl", },
1073 { },
1074 };
1075
1076 static struct platform_driver msm8x74_pinctrl_driver = {
1077 .driver = {
1078 .name = "msm8x74-pinctrl",
1079 .of_match_table = msm8x74_pinctrl_of_match,
1080 },
1081 .probe = msm8x74_pinctrl_probe,
1082 .remove = msm_pinctrl_remove,
1083 };
1084
1085 static int __init msm8x74_pinctrl_init(void)
1086 {
1087 return platform_driver_register(&msm8x74_pinctrl_driver);
1088 }
1089 arch_initcall(msm8x74_pinctrl_init);
1090
1091 static void __exit msm8x74_pinctrl_exit(void)
1092 {
1093 platform_driver_unregister(&msm8x74_pinctrl_driver);
1094 }
1095 module_exit(msm8x74_pinctrl_exit);
1096
1097 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
1098 MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");
1099 MODULE_LICENSE("GPL v2");
1100 MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
1101
Linux with added FPC-III support