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WIP FPC-III support
[linux/fpc-iii.git] / drivers / pinctrl / renesas / pfc-r8a77951.c
blobcf14420794c7f5c9e0707fae0b3d6c99bc44f07b
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77951 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
6 */
7
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/sys_soc.h>
11
12 #include "core.h"
13 #include "sh_pfc.h"
14
15 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
16
17 #define CPU_ALL_GP(fn, sfx) \
18 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
21 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
22 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
30
31 #define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
75
76 /*
77 * F_() : just information
78 * FM() : macro for FN_xxx / xxx_MARK
79 */
80
81 /* GPSR0 */
82 #define GPSR0_15 F_(D15, IP7_11_8)
83 #define GPSR0_14 F_(D14, IP7_7_4)
84 #define GPSR0_13 F_(D13, IP7_3_0)
85 #define GPSR0_12 F_(D12, IP6_31_28)
86 #define GPSR0_11 F_(D11, IP6_27_24)
87 #define GPSR0_10 F_(D10, IP6_23_20)
88 #define GPSR0_9 F_(D9, IP6_19_16)
89 #define GPSR0_8 F_(D8, IP6_15_12)
90 #define GPSR0_7 F_(D7, IP6_11_8)
91 #define GPSR0_6 F_(D6, IP6_7_4)
92 #define GPSR0_5 F_(D5, IP6_3_0)
93 #define GPSR0_4 F_(D4, IP5_31_28)
94 #define GPSR0_3 F_(D3, IP5_27_24)
95 #define GPSR0_2 F_(D2, IP5_23_20)
96 #define GPSR0_1 F_(D1, IP5_19_16)
97 #define GPSR0_0 F_(D0, IP5_15_12)
98
99 /* GPSR1 */
100 #define GPSR1_28 FM(CLKOUT)
101 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
102 #define GPSR1_26 F_(WE1_N, IP5_7_4)
103 #define GPSR1_25 F_(WE0_N, IP5_3_0)
104 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
105 #define GPSR1_23 F_(RD_N, IP4_27_24)
106 #define GPSR1_22 F_(BS_N, IP4_23_20)
107 #define GPSR1_21 F_(CS1_N, IP4_19_16)
108 #define GPSR1_20 F_(CS0_N, IP4_15_12)
109 #define GPSR1_19 F_(A19, IP4_11_8)
110 #define GPSR1_18 F_(A18, IP4_7_4)
111 #define GPSR1_17 F_(A17, IP4_3_0)
112 #define GPSR1_16 F_(A16, IP3_31_28)
113 #define GPSR1_15 F_(A15, IP3_27_24)
114 #define GPSR1_14 F_(A14, IP3_23_20)
115 #define GPSR1_13 F_(A13, IP3_19_16)
116 #define GPSR1_12 F_(A12, IP3_15_12)
117 #define GPSR1_11 F_(A11, IP3_11_8)
118 #define GPSR1_10 F_(A10, IP3_7_4)
119 #define GPSR1_9 F_(A9, IP3_3_0)
120 #define GPSR1_8 F_(A8, IP2_31_28)
121 #define GPSR1_7 F_(A7, IP2_27_24)
122 #define GPSR1_6 F_(A6, IP2_23_20)
123 #define GPSR1_5 F_(A5, IP2_19_16)
124 #define GPSR1_4 F_(A4, IP2_15_12)
125 #define GPSR1_3 F_(A3, IP2_11_8)
126 #define GPSR1_2 F_(A2, IP2_7_4)
127 #define GPSR1_1 F_(A1, IP2_3_0)
128 #define GPSR1_0 F_(A0, IP1_31_28)
129
130 /* GPSR2 */
131 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
132 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
133 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
134 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
135 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
136 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
137 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
138 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
139 #define GPSR2_6 F_(PWM0, IP1_19_16)
140 #define GPSR2_5 F_(IRQ5, IP1_15_12)
141 #define GPSR2_4 F_(IRQ4, IP1_11_8)
142 #define GPSR2_3 F_(IRQ3, IP1_7_4)
143 #define GPSR2_2 F_(IRQ2, IP1_3_0)
144 #define GPSR2_1 F_(IRQ1, IP0_31_28)
145 #define GPSR2_0 F_(IRQ0, IP0_27_24)
146
147 /* GPSR3 */
148 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
149 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
150 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
151 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
152 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
153 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
154 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
155 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
156 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
157 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
158 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
159 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
160 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
161 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
162 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
163 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
164
165 /* GPSR4 */
166 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
167 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
168 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
169 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
170 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
171 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
172 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
173 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
174 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
175 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
176 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
177 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
178 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
179 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
180 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
181 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
182 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
183 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
184
185 /* GPSR5 */
186 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
187 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
188 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
189 #define GPSR5_22 FM(MSIOF0_RXD)
190 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
191 #define GPSR5_20 FM(MSIOF0_TXD)
192 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
193 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
194 #define GPSR5_17 FM(MSIOF0_SCK)
195 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
196 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
197 #define GPSR5_14 F_(HTX0, IP13_19_16)
198 #define GPSR5_13 F_(HRX0, IP13_15_12)
199 #define GPSR5_12 F_(HSCK0, IP13_11_8)
200 #define GPSR5_11 F_(RX2_A, IP13_7_4)
201 #define GPSR5_10 F_(TX2_A, IP13_3_0)
202 #define GPSR5_9 F_(SCK2, IP12_31_28)
203 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
204 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
205 #define GPSR5_6 F_(TX1_A, IP12_19_16)
206 #define GPSR5_5 F_(RX1_A, IP12_15_12)
207 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
208 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
209 #define GPSR5_2 F_(TX0, IP12_3_0)
210 #define GPSR5_1 F_(RX0, IP11_31_28)
211 #define GPSR5_0 F_(SCK0, IP11_27_24)
212
213 /* GPSR6 */
214 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
215 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
216 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
217 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
218 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
219 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
220 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
221 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
222 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
223 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
224 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
225 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
226 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
227 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
228 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
229 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
230 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
231 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
232 #define GPSR6_13 FM(SSI_SDATA5)
233 #define GPSR6_12 FM(SSI_WS5)
234 #define GPSR6_11 FM(SSI_SCK5)
235 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
236 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
237 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
238 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
239 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
240 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
241 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
242 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
243 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
244 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
245 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
246
247 /* GPSR7 */
248 #define GPSR7_3 FM(GP7_03)
249 #define GPSR7_2 FM(GP7_02)
250 #define GPSR7_1 FM(AVS2)
251 #define GPSR7_0 FM(AVS1)
252
253
254 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
255 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349
350 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
351 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
372 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379
380 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
381 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
401 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
402 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
403 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
404 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
405 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
407 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
408
409 #define PINMUX_GPSR \
410 \
411 GPSR6_31 \
412 GPSR6_30 \
413 GPSR6_29 \
414 GPSR1_28 GPSR6_28 \
415 GPSR1_27 GPSR6_27 \
416 GPSR1_26 GPSR6_26 \
417 GPSR1_25 GPSR5_25 GPSR6_25 \
418 GPSR1_24 GPSR5_24 GPSR6_24 \
419 GPSR1_23 GPSR5_23 GPSR6_23 \
420 GPSR1_22 GPSR5_22 GPSR6_22 \
421 GPSR1_21 GPSR5_21 GPSR6_21 \
422 GPSR1_20 GPSR5_20 GPSR6_20 \
423 GPSR1_19 GPSR5_19 GPSR6_19 \
424 GPSR1_18 GPSR5_18 GPSR6_18 \
425 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
426 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
427 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
428 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
429 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
430 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
431 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
432 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
433 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
434 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
435 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
436 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
437 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
438 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
439 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
440 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
441 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
442 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
443
444 #define PINMUX_IPSR \
445 \
446 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
447 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
448 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
449 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
450 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
451 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
452 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
453 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
454 \
455 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
456 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
457 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
458 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
459 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
460 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
462 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
463 \
464 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
465 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
466 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
467 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
468 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
469 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
470 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
471 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
472 \
473 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
474 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
475 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
476 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
477 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
478 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
479 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
480 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
481 \
482 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
483 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
484 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
485 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
486 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
487 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
488 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
489 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
490
491 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
492 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
494 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
495 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
496 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
497 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
498 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
499 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
500 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
501 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
502 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
503 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
504 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
505 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
506 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
507 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
508 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
509 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
510
511 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
512 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
513 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
514 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
515 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
516 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
517 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
518 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
519 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
520 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
521 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
522 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
523 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
524 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
525 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
526 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
527 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
528 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
529 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
530 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
531 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
532 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
533 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
534
535 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
536 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
537 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
538 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
539 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
540 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
541 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
542 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
543 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
544 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
545 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
546 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
547 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
548
549 #define PINMUX_MOD_SELS \
550 \
551 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
552 MOD_SEL2_30 \
553 MOD_SEL1_29_28_27 MOD_SEL2_29 \
554 MOD_SEL0_28_27 MOD_SEL2_28_27 \
555 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
556 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
557 MOD_SEL0_23 MOD_SEL1_23_22_21 \
558 MOD_SEL0_22 \
559 MOD_SEL0_21 MOD_SEL2_21 \
560 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
561 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
562 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
563 MOD_SEL2_17 \
564 MOD_SEL0_16 MOD_SEL1_16 \
565 MOD_SEL1_15_14 \
566 MOD_SEL0_14_13 \
567 MOD_SEL1_13 \
568 MOD_SEL0_12 MOD_SEL1_12 \
569 MOD_SEL0_11 MOD_SEL1_11 \
570 MOD_SEL0_10 MOD_SEL1_10 \
571 MOD_SEL0_9_8 MOD_SEL1_9 \
572 MOD_SEL0_7_6 \
573 MOD_SEL1_6 \
574 MOD_SEL0_5 MOD_SEL1_5 \
575 MOD_SEL0_4_3 MOD_SEL1_4 \
576 MOD_SEL1_3 \
577 MOD_SEL1_2 \
578 MOD_SEL1_1 \
579 MOD_SEL1_0 MOD_SEL2_0
580
581 /*
582 * These pins are not able to be muxed but have other properties
583 * that can be set, such as drive-strength or pull-up/pull-down enable.
584 */
585 #define PINMUX_STATIC \
586 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
587 FM(QSPI0_IO2) FM(QSPI0_IO3) \
588 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
589 FM(QSPI1_IO2) FM(QSPI1_IO3) \
590 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
591 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
592 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
593 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
594 FM(PRESETOUT) \
595 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
596 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
597
598 #define PINMUX_PHYS \
599 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
600
601 enum {
602 PINMUX_RESERVED = 0,
603
604 PINMUX_DATA_BEGIN,
605 GP_ALL(DATA),
606 PINMUX_DATA_END,
607
608 #define F_(x, y)
609 #define FM(x) FN_##x,
610 PINMUX_FUNCTION_BEGIN,
611 GP_ALL(FN),
612 PINMUX_GPSR
613 PINMUX_IPSR
614 PINMUX_MOD_SELS
615 PINMUX_FUNCTION_END,
616 #undef F_
617 #undef FM
618
619 #define F_(x, y)
620 #define FM(x) x##_MARK,
621 PINMUX_MARK_BEGIN,
622 PINMUX_GPSR
623 PINMUX_IPSR
624 PINMUX_MOD_SELS
625 PINMUX_STATIC
626 PINMUX_PHYS
627 PINMUX_MARK_END,
628 #undef F_
629 #undef FM
630 };
631
632 static const u16 pinmux_data[] = {
633 PINMUX_DATA_GP_ALL(),
634
635 PINMUX_SINGLE(AVS1),
636 PINMUX_SINGLE(AVS2),
637 PINMUX_SINGLE(CLKOUT),
638 PINMUX_SINGLE(GP7_02),
639 PINMUX_SINGLE(GP7_03),
640 PINMUX_SINGLE(MSIOF0_RXD),
641 PINMUX_SINGLE(MSIOF0_SCK),
642 PINMUX_SINGLE(MSIOF0_TXD),
643 PINMUX_SINGLE(SSI_SCK5),
644 PINMUX_SINGLE(SSI_SDATA5),
645 PINMUX_SINGLE(SSI_WS5),
646
647 /* IPSR0 */
648 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
649 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
650
651 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
652 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
653 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
654
655 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
656 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
657 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
658
659 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
660 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
661 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
662
663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
665 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
666 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
667 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
668
669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
672 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
673
674 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
675 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
676 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
677 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
679 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
680 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
681
682 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
683 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
684 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
685 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
687 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
688 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
689
690 /* IPSR1 */
691 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
692 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
693 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
694 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
695 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
696 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
697
698 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
699 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
700 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
701 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
702 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
703 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
704
705 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
706 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
707 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
708 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
709 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
710 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
711
712 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
713 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
714 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
715 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
716 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
717 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
718 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
719
720 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
721 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
722 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
723 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
724
725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
729 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
730
731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
734 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
735
736 PINMUX_IPSR_GPSR(IP1_31_28, A0),
737 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
738 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
739 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
740 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
741 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
742
743 /* IPSR2 */
744 PINMUX_IPSR_GPSR(IP2_3_0, A1),
745 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
746 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
747 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
748 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
749 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
750
751 PINMUX_IPSR_GPSR(IP2_7_4, A2),
752 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
753 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
754 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
755 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
756 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
757
758 PINMUX_IPSR_GPSR(IP2_11_8, A3),
759 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
760 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
761 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
762 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
763 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
764
765 PINMUX_IPSR_GPSR(IP2_15_12, A4),
766 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
767 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
768 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
769 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
770 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
771
772 PINMUX_IPSR_GPSR(IP2_19_16, A5),
773 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
774 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
775 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
776 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
777 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
778 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
779
780 PINMUX_IPSR_GPSR(IP2_23_20, A6),
781 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
782 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
783 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
784 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
785 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
786 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
787
788 PINMUX_IPSR_GPSR(IP2_27_24, A7),
789 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
790 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
791 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
792 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
793 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
794 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
795
796 PINMUX_IPSR_GPSR(IP2_31_28, A8),
797 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
798 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
799 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
800 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
801 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
802 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
803
804 /* IPSR3 */
805 PINMUX_IPSR_GPSR(IP3_3_0, A9),
806 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
807 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
808 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
809
810 PINMUX_IPSR_GPSR(IP3_7_4, A10),
811 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
812 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
813 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
814
815 PINMUX_IPSR_GPSR(IP3_11_8, A11),
816 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
817 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
818 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
819 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
820 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
821 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
822 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
823 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
824
825 PINMUX_IPSR_GPSR(IP3_15_12, A12),
826 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
827 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
828 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
829 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
830 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
831
832 PINMUX_IPSR_GPSR(IP3_19_16, A13),
833 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
834 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
835 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
836 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
837 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
838
839 PINMUX_IPSR_GPSR(IP3_23_20, A14),
840 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
841 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
842 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
843 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
844 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
845
846 PINMUX_IPSR_GPSR(IP3_27_24, A15),
847 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
848 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
849 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
850 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
851 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
852
853 PINMUX_IPSR_GPSR(IP3_31_28, A16),
854 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
855 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
856 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
857
858 /* IPSR4 */
859 PINMUX_IPSR_GPSR(IP4_3_0, A17),
860 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
861 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
862 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
863
864 PINMUX_IPSR_GPSR(IP4_7_4, A18),
865 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
866 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
867 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
868
869 PINMUX_IPSR_GPSR(IP4_11_8, A19),
870 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
871 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
872 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
873
874 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
875 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
876
877 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
878 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
879 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
880
881 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
882 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
883 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
884 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
885 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
886 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
887 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
888 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
889
890 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
891 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
892 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
894 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
895 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
896
897 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
898 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
899 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
901 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
902 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
903
904 /* IPSR5 */
905 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
906 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
907 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
908 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
909 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
910 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
911 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
912
913 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
914 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
915 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
916 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
917 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
918 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
919 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
920 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
921
922 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
923 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
924 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
925 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
926
927 PINMUX_IPSR_GPSR(IP5_15_12, D0),
928 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
929 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
930 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
931 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
932
933 PINMUX_IPSR_GPSR(IP5_19_16, D1),
934 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
935 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
936 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
937 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
938
939 PINMUX_IPSR_GPSR(IP5_23_20, D2),
940 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
941 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
942 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
943
944 PINMUX_IPSR_GPSR(IP5_27_24, D3),
945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
948
949 PINMUX_IPSR_GPSR(IP5_31_28, D4),
950 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
951 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
952 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
953
954 /* IPSR6 */
955 PINMUX_IPSR_GPSR(IP6_3_0, D5),
956 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
957 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
958 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
959
960 PINMUX_IPSR_GPSR(IP6_7_4, D6),
961 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
962 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
963 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
964
965 PINMUX_IPSR_GPSR(IP6_11_8, D7),
966 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
967 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
968 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
969
970 PINMUX_IPSR_GPSR(IP6_15_12, D8),
971 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
972 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
973 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
974 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
975 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
976
977 PINMUX_IPSR_GPSR(IP6_19_16, D9),
978 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
979 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
980 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
982
983 PINMUX_IPSR_GPSR(IP6_23_20, D10),
984 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
985 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
987 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
988 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
989 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
990
991 PINMUX_IPSR_GPSR(IP6_27_24, D11),
992 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
993 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
994 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
995 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
996 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
997 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
998
999 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1000 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1001 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1002 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1004 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1005
1006 /* IPSR7 */
1007 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1008 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1009 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1010 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1011 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1012 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1013
1014 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1015 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1016 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1017 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1018 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1019 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1020 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1021
1022 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1023 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1024 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1025 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1026 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1027 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1028 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1029
1030 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1031 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1032 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1033
1034 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1035 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1036 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1037
1038 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1039 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1041 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1042
1043 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1044 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1045 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1046 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1047
1048 /* IPSR8 */
1049 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1050 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1051 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1052 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1053
1054 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1055 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1056 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1057 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1058
1059 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1060 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1061 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1062
1063 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1064 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1065 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1066 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1067 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1068
1069 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1070 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1071 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1072 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1073 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1074 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1075
1076 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1077 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1078 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1079 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1080 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1081 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1082
1083 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1084 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1085 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1086 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1087 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1088 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1089
1090 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1091 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1092 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1093 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1094 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1095 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1096
1097 /* IPSR9 */
1098 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1099 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1100
1101 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1102 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1103
1104 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1105 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1106
1107 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1108 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1109
1110 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1111 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1112
1113 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1114 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1115
1116 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1117 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1118 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1119
1120 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1121 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1122
1123 /* IPSR10 */
1124 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1125 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1126
1127 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1128 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1129
1130 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1131 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1132
1133 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1134 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1135
1136 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1137 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1138
1139 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1140 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1141 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1142
1143 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1144 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1145 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1146
1147 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1149 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1150
1151 /* IPSR11 */
1152 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1154 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1155
1156 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1157 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1158
1159 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1160 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1161 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1162
1163 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1164 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1165
1166 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1167 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1168 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1169
1170 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1171 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1172 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1173
1174 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1175 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1176 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1177 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1178 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1179 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1180 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1182 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1183 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1184
1185 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1186 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1187 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1188 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1190
1191 /* IPSR12 */
1192 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1193 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1194 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1195 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1196 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1197
1198 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1199 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1200 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1201 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1203 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1204 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1205 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1206
1207 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1208 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1209 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1210 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1211 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1212 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1213 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1214 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1215
1216 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1217 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1218 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1219 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1220 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1221
1222 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1223 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1225 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1226 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1227
1228 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1229 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1231 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1232 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1233 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1234 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1235
1236 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1237 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1238 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1239 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1240 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1241 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1242 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1243
1244 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1245 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1246 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1247 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1248 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1249 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1250 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1251
1252 /* IPSR13 */
1253 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1254 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1255 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1256 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1257 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1258 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1259
1260 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1261 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1262 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1263 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1264 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1265 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1266
1267 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1268 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1269 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1270 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1271 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1272 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1273 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1274 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1275
1276 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1277 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1278 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1279 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1280 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1281 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1282
1283 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1284 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1285 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1286 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1287 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1288 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1289
1290 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1291 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1292 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1293 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1294 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1295 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1296 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1297 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1298
1299 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1300 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1301 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1302 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1303 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1304 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1305 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1306
1307 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1308 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1309 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1310 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1311
1312 /* IPSR14 */
1313 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1314 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1315 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1316 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1317 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1318 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1319 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1320 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1321
1322 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1323 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1324 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1325 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1326 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1327 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1328 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1329 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1330
1331 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1332 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1333 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1334
1335 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1336 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1337 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1338 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1339
1340 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1341 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1342 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1343
1344 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1345 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1346
1347 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1348 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1349
1350 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1351 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1352
1353 /* IPSR15 */
1354 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1355
1356 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1357 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1358
1359 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1360 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1361 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1362
1363 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1364 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1365 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1367
1368 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1369 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1370 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1371 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1372 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1373 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1374 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1375
1376 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1377 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1378 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1379 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1380 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1381 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1382 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1383
1384 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1385 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1386 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1387 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1388 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1389 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1390 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1391
1392 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1393 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1394 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1395 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1397 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1398 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1399
1400 /* IPSR16 */
1401 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1402 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1403 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1404
1405 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1406 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1407 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1408
1409 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1410 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1411 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1412
1413 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1414 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1415 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1416 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1417 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1418 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1419 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1420
1421 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1422 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1423 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1424 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1425 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1426 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1428
1429 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1430 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1431 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1432 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1433 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1434 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1436 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1437
1438 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1439 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1440 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1441 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1442 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1443 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1444 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1445
1446 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1447 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1448 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1451 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1452 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1453 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1454
1455 /* IPSR17 */
1456 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1457
1458 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1459 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1460 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1461 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1462 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1463
1464 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1465 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1466 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1467 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1468 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1469 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1470 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1471
1472 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1473 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1474 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1477 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1478
1479 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1480 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1481 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1482 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1483 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1484 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1485 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1486 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1487 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1488
1489 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1490 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1491 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1492 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1495 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1496 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1497 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1498
1499 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1500 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1501 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1502 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1503 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1504 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1505 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1506 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1507 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1508 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1509 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1510
1511 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1512 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1513 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1514 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1515 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1516 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1517 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1518 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1519 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1520
1521 /* IPSR18 */
1522 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1523 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1524 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1525 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1526 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1527 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1528 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1529 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1530 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1531
1532 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1533 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1534 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1535 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1536 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1537 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1538 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1539 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1540 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1541
1542 /*
1543 * Static pins can not be muxed between different functions but
1544 * still need mark entries in the pinmux list. Add each static
1545 * pin to the list without an associated function. The sh-pfc
1546 * core will do the right thing and skip trying to mux the pin
1547 * while still applying configuration to it.
1548 */
1549 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1550 PINMUX_STATIC
1551 #undef FM
1552 };
1553
1554 /*
1555 * Pins not associated with a GPIO port.
1556 */
1557 enum {
1558 GP_ASSIGN_LAST(),
1559 NOGP_ALL(),
1560 };
1561
1562 static const struct sh_pfc_pin pinmux_pins[] = {
1563 PINMUX_GPIO_GP_ALL(),
1564 PINMUX_NOGP_ALL(),
1565 };
1566
1567 /* - AUDIO CLOCK ------------------------------------------------------------ */
1568 static const unsigned int audio_clk_a_a_pins[] = {
1569 /* CLK A */
1570 RCAR_GP_PIN(6, 22),
1571 };
1572 static const unsigned int audio_clk_a_a_mux[] = {
1573 AUDIO_CLKA_A_MARK,
1574 };
1575 static const unsigned int audio_clk_a_b_pins[] = {
1576 /* CLK A */
1577 RCAR_GP_PIN(5, 4),
1578 };
1579 static const unsigned int audio_clk_a_b_mux[] = {
1580 AUDIO_CLKA_B_MARK,
1581 };
1582 static const unsigned int audio_clk_a_c_pins[] = {
1583 /* CLK A */
1584 RCAR_GP_PIN(5, 19),
1585 };
1586 static const unsigned int audio_clk_a_c_mux[] = {
1587 AUDIO_CLKA_C_MARK,
1588 };
1589 static const unsigned int audio_clk_b_a_pins[] = {
1590 /* CLK B */
1591 RCAR_GP_PIN(5, 12),
1592 };
1593 static const unsigned int audio_clk_b_a_mux[] = {
1594 AUDIO_CLKB_A_MARK,
1595 };
1596 static const unsigned int audio_clk_b_b_pins[] = {
1597 /* CLK B */
1598 RCAR_GP_PIN(6, 23),
1599 };
1600 static const unsigned int audio_clk_b_b_mux[] = {
1601 AUDIO_CLKB_B_MARK,
1602 };
1603 static const unsigned int audio_clk_c_a_pins[] = {
1604 /* CLK C */
1605 RCAR_GP_PIN(5, 21),
1606 };
1607 static const unsigned int audio_clk_c_a_mux[] = {
1608 AUDIO_CLKC_A_MARK,
1609 };
1610 static const unsigned int audio_clk_c_b_pins[] = {
1611 /* CLK C */
1612 RCAR_GP_PIN(5, 0),
1613 };
1614 static const unsigned int audio_clk_c_b_mux[] = {
1615 AUDIO_CLKC_B_MARK,
1616 };
1617 static const unsigned int audio_clkout_a_pins[] = {
1618 /* CLKOUT */
1619 RCAR_GP_PIN(5, 18),
1620 };
1621 static const unsigned int audio_clkout_a_mux[] = {
1622 AUDIO_CLKOUT_A_MARK,
1623 };
1624 static const unsigned int audio_clkout_b_pins[] = {
1625 /* CLKOUT */
1626 RCAR_GP_PIN(6, 28),
1627 };
1628 static const unsigned int audio_clkout_b_mux[] = {
1629 AUDIO_CLKOUT_B_MARK,
1630 };
1631 static const unsigned int audio_clkout_c_pins[] = {
1632 /* CLKOUT */
1633 RCAR_GP_PIN(5, 3),
1634 };
1635 static const unsigned int audio_clkout_c_mux[] = {
1636 AUDIO_CLKOUT_C_MARK,
1637 };
1638 static const unsigned int audio_clkout_d_pins[] = {
1639 /* CLKOUT */
1640 RCAR_GP_PIN(5, 21),
1641 };
1642 static const unsigned int audio_clkout_d_mux[] = {
1643 AUDIO_CLKOUT_D_MARK,
1644 };
1645 static const unsigned int audio_clkout1_a_pins[] = {
1646 /* CLKOUT1 */
1647 RCAR_GP_PIN(5, 15),
1648 };
1649 static const unsigned int audio_clkout1_a_mux[] = {
1650 AUDIO_CLKOUT1_A_MARK,
1651 };
1652 static const unsigned int audio_clkout1_b_pins[] = {
1653 /* CLKOUT1 */
1654 RCAR_GP_PIN(6, 29),
1655 };
1656 static const unsigned int audio_clkout1_b_mux[] = {
1657 AUDIO_CLKOUT1_B_MARK,
1658 };
1659 static const unsigned int audio_clkout2_a_pins[] = {
1660 /* CLKOUT2 */
1661 RCAR_GP_PIN(5, 16),
1662 };
1663 static const unsigned int audio_clkout2_a_mux[] = {
1664 AUDIO_CLKOUT2_A_MARK,
1665 };
1666 static const unsigned int audio_clkout2_b_pins[] = {
1667 /* CLKOUT2 */
1668 RCAR_GP_PIN(6, 30),
1669 };
1670 static const unsigned int audio_clkout2_b_mux[] = {
1671 AUDIO_CLKOUT2_B_MARK,
1672 };
1673 static const unsigned int audio_clkout3_a_pins[] = {
1674 /* CLKOUT3 */
1675 RCAR_GP_PIN(5, 19),
1676 };
1677 static const unsigned int audio_clkout3_a_mux[] = {
1678 AUDIO_CLKOUT3_A_MARK,
1679 };
1680 static const unsigned int audio_clkout3_b_pins[] = {
1681 /* CLKOUT3 */
1682 RCAR_GP_PIN(6, 31),
1683 };
1684 static const unsigned int audio_clkout3_b_mux[] = {
1685 AUDIO_CLKOUT3_B_MARK,
1686 };
1687
1688 /* - EtherAVB --------------------------------------------------------------- */
1689 static const unsigned int avb_link_pins[] = {
1690 /* AVB_LINK */
1691 RCAR_GP_PIN(2, 12),
1692 };
1693 static const unsigned int avb_link_mux[] = {
1694 AVB_LINK_MARK,
1695 };
1696 static const unsigned int avb_magic_pins[] = {
1697 /* AVB_MAGIC_ */
1698 RCAR_GP_PIN(2, 10),
1699 };
1700 static const unsigned int avb_magic_mux[] = {
1701 AVB_MAGIC_MARK,
1702 };
1703 static const unsigned int avb_phy_int_pins[] = {
1704 /* AVB_PHY_INT */
1705 RCAR_GP_PIN(2, 11),
1706 };
1707 static const unsigned int avb_phy_int_mux[] = {
1708 AVB_PHY_INT_MARK,
1709 };
1710 static const unsigned int avb_mdio_pins[] = {
1711 /* AVB_MDC, AVB_MDIO */
1712 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1713 };
1714 static const unsigned int avb_mdio_mux[] = {
1715 AVB_MDC_MARK, AVB_MDIO_MARK,
1716 };
1717 static const unsigned int avb_mii_pins[] = {
1718 /*
1719 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1720 * AVB_TD1, AVB_TD2, AVB_TD3,
1721 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1722 * AVB_RD1, AVB_RD2, AVB_RD3,
1723 * AVB_TXCREFCLK
1724 */
1725 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1726 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1727 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1728 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1729 PIN_AVB_TXCREFCLK,
1730
1731 };
1732 static const unsigned int avb_mii_mux[] = {
1733 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1734 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1735 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1736 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1737 AVB_TXCREFCLK_MARK,
1738 };
1739 static const unsigned int avb_avtp_pps_pins[] = {
1740 /* AVB_AVTP_PPS */
1741 RCAR_GP_PIN(2, 6),
1742 };
1743 static const unsigned int avb_avtp_pps_mux[] = {
1744 AVB_AVTP_PPS_MARK,
1745 };
1746 static const unsigned int avb_avtp_match_a_pins[] = {
1747 /* AVB_AVTP_MATCH_A */
1748 RCAR_GP_PIN(2, 13),
1749 };
1750 static const unsigned int avb_avtp_match_a_mux[] = {
1751 AVB_AVTP_MATCH_A_MARK,
1752 };
1753 static const unsigned int avb_avtp_capture_a_pins[] = {
1754 /* AVB_AVTP_CAPTURE_A */
1755 RCAR_GP_PIN(2, 14),
1756 };
1757 static const unsigned int avb_avtp_capture_a_mux[] = {
1758 AVB_AVTP_CAPTURE_A_MARK,
1759 };
1760 static const unsigned int avb_avtp_match_b_pins[] = {
1761 /* AVB_AVTP_MATCH_B */
1762 RCAR_GP_PIN(1, 8),
1763 };
1764 static const unsigned int avb_avtp_match_b_mux[] = {
1765 AVB_AVTP_MATCH_B_MARK,
1766 };
1767 static const unsigned int avb_avtp_capture_b_pins[] = {
1768 /* AVB_AVTP_CAPTURE_B */
1769 RCAR_GP_PIN(1, 11),
1770 };
1771 static const unsigned int avb_avtp_capture_b_mux[] = {
1772 AVB_AVTP_CAPTURE_B_MARK,
1773 };
1774
1775 /* - CAN ------------------------------------------------------------------ */
1776 static const unsigned int can0_data_a_pins[] = {
1777 /* TX, RX */
1778 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1779 };
1780 static const unsigned int can0_data_a_mux[] = {
1781 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1782 };
1783 static const unsigned int can0_data_b_pins[] = {
1784 /* TX, RX */
1785 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1786 };
1787 static const unsigned int can0_data_b_mux[] = {
1788 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1789 };
1790 static const unsigned int can1_data_pins[] = {
1791 /* TX, RX */
1792 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1793 };
1794 static const unsigned int can1_data_mux[] = {
1795 CAN1_TX_MARK, CAN1_RX_MARK,
1796 };
1797
1798 /* - CAN Clock -------------------------------------------------------------- */
1799 static const unsigned int can_clk_pins[] = {
1800 /* CLK */
1801 RCAR_GP_PIN(1, 25),
1802 };
1803 static const unsigned int can_clk_mux[] = {
1804 CAN_CLK_MARK,
1805 };
1806
1807 /* - CAN FD --------------------------------------------------------------- */
1808 static const unsigned int canfd0_data_a_pins[] = {
1809 /* TX, RX */
1810 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1811 };
1812 static const unsigned int canfd0_data_a_mux[] = {
1813 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1814 };
1815 static const unsigned int canfd0_data_b_pins[] = {
1816 /* TX, RX */
1817 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1818 };
1819 static const unsigned int canfd0_data_b_mux[] = {
1820 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1821 };
1822 static const unsigned int canfd1_data_pins[] = {
1823 /* TX, RX */
1824 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1825 };
1826 static const unsigned int canfd1_data_mux[] = {
1827 CANFD1_TX_MARK, CANFD1_RX_MARK,
1828 };
1829
1830 #ifdef CONFIG_PINCTRL_PFC_R8A77951
1831 /* - DRIF0 --------------------------------------------------------------- */
1832 static const unsigned int drif0_ctrl_a_pins[] = {
1833 /* CLK, SYNC */
1834 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1835 };
1836 static const unsigned int drif0_ctrl_a_mux[] = {
1837 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1838 };
1839 static const unsigned int drif0_data0_a_pins[] = {
1840 /* D0 */
1841 RCAR_GP_PIN(6, 10),
1842 };
1843 static const unsigned int drif0_data0_a_mux[] = {
1844 RIF0_D0_A_MARK,
1845 };
1846 static const unsigned int drif0_data1_a_pins[] = {
1847 /* D1 */
1848 RCAR_GP_PIN(6, 7),
1849 };
1850 static const unsigned int drif0_data1_a_mux[] = {
1851 RIF0_D1_A_MARK,
1852 };
1853 static const unsigned int drif0_ctrl_b_pins[] = {
1854 /* CLK, SYNC */
1855 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1856 };
1857 static const unsigned int drif0_ctrl_b_mux[] = {
1858 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1859 };
1860 static const unsigned int drif0_data0_b_pins[] = {
1861 /* D0 */
1862 RCAR_GP_PIN(5, 1),
1863 };
1864 static const unsigned int drif0_data0_b_mux[] = {
1865 RIF0_D0_B_MARK,
1866 };
1867 static const unsigned int drif0_data1_b_pins[] = {
1868 /* D1 */
1869 RCAR_GP_PIN(5, 2),
1870 };
1871 static const unsigned int drif0_data1_b_mux[] = {
1872 RIF0_D1_B_MARK,
1873 };
1874 static const unsigned int drif0_ctrl_c_pins[] = {
1875 /* CLK, SYNC */
1876 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1877 };
1878 static const unsigned int drif0_ctrl_c_mux[] = {
1879 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1880 };
1881 static const unsigned int drif0_data0_c_pins[] = {
1882 /* D0 */
1883 RCAR_GP_PIN(5, 13),
1884 };
1885 static const unsigned int drif0_data0_c_mux[] = {
1886 RIF0_D0_C_MARK,
1887 };
1888 static const unsigned int drif0_data1_c_pins[] = {
1889 /* D1 */
1890 RCAR_GP_PIN(5, 14),
1891 };
1892 static const unsigned int drif0_data1_c_mux[] = {
1893 RIF0_D1_C_MARK,
1894 };
1895 /* - DRIF1 --------------------------------------------------------------- */
1896 static const unsigned int drif1_ctrl_a_pins[] = {
1897 /* CLK, SYNC */
1898 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1899 };
1900 static const unsigned int drif1_ctrl_a_mux[] = {
1901 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1902 };
1903 static const unsigned int drif1_data0_a_pins[] = {
1904 /* D0 */
1905 RCAR_GP_PIN(6, 19),
1906 };
1907 static const unsigned int drif1_data0_a_mux[] = {
1908 RIF1_D0_A_MARK,
1909 };
1910 static const unsigned int drif1_data1_a_pins[] = {
1911 /* D1 */
1912 RCAR_GP_PIN(6, 20),
1913 };
1914 static const unsigned int drif1_data1_a_mux[] = {
1915 RIF1_D1_A_MARK,
1916 };
1917 static const unsigned int drif1_ctrl_b_pins[] = {
1918 /* CLK, SYNC */
1919 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1920 };
1921 static const unsigned int drif1_ctrl_b_mux[] = {
1922 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1923 };
1924 static const unsigned int drif1_data0_b_pins[] = {
1925 /* D0 */
1926 RCAR_GP_PIN(5, 7),
1927 };
1928 static const unsigned int drif1_data0_b_mux[] = {
1929 RIF1_D0_B_MARK,
1930 };
1931 static const unsigned int drif1_data1_b_pins[] = {
1932 /* D1 */
1933 RCAR_GP_PIN(5, 8),
1934 };
1935 static const unsigned int drif1_data1_b_mux[] = {
1936 RIF1_D1_B_MARK,
1937 };
1938 static const unsigned int drif1_ctrl_c_pins[] = {
1939 /* CLK, SYNC */
1940 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1941 };
1942 static const unsigned int drif1_ctrl_c_mux[] = {
1943 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1944 };
1945 static const unsigned int drif1_data0_c_pins[] = {
1946 /* D0 */
1947 RCAR_GP_PIN(5, 6),
1948 };
1949 static const unsigned int drif1_data0_c_mux[] = {
1950 RIF1_D0_C_MARK,
1951 };
1952 static const unsigned int drif1_data1_c_pins[] = {
1953 /* D1 */
1954 RCAR_GP_PIN(5, 10),
1955 };
1956 static const unsigned int drif1_data1_c_mux[] = {
1957 RIF1_D1_C_MARK,
1958 };
1959 /* - DRIF2 --------------------------------------------------------------- */
1960 static const unsigned int drif2_ctrl_a_pins[] = {
1961 /* CLK, SYNC */
1962 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1963 };
1964 static const unsigned int drif2_ctrl_a_mux[] = {
1965 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1966 };
1967 static const unsigned int drif2_data0_a_pins[] = {
1968 /* D0 */
1969 RCAR_GP_PIN(6, 7),
1970 };
1971 static const unsigned int drif2_data0_a_mux[] = {
1972 RIF2_D0_A_MARK,
1973 };
1974 static const unsigned int drif2_data1_a_pins[] = {
1975 /* D1 */
1976 RCAR_GP_PIN(6, 10),
1977 };
1978 static const unsigned int drif2_data1_a_mux[] = {
1979 RIF2_D1_A_MARK,
1980 };
1981 static const unsigned int drif2_ctrl_b_pins[] = {
1982 /* CLK, SYNC */
1983 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1984 };
1985 static const unsigned int drif2_ctrl_b_mux[] = {
1986 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1987 };
1988 static const unsigned int drif2_data0_b_pins[] = {
1989 /* D0 */
1990 RCAR_GP_PIN(6, 30),
1991 };
1992 static const unsigned int drif2_data0_b_mux[] = {
1993 RIF2_D0_B_MARK,
1994 };
1995 static const unsigned int drif2_data1_b_pins[] = {
1996 /* D1 */
1997 RCAR_GP_PIN(6, 31),
1998 };
1999 static const unsigned int drif2_data1_b_mux[] = {
2000 RIF2_D1_B_MARK,
2001 };
2002 /* - DRIF3 --------------------------------------------------------------- */
2003 static const unsigned int drif3_ctrl_a_pins[] = {
2004 /* CLK, SYNC */
2005 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2006 };
2007 static const unsigned int drif3_ctrl_a_mux[] = {
2008 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2009 };
2010 static const unsigned int drif3_data0_a_pins[] = {
2011 /* D0 */
2012 RCAR_GP_PIN(6, 19),
2013 };
2014 static const unsigned int drif3_data0_a_mux[] = {
2015 RIF3_D0_A_MARK,
2016 };
2017 static const unsigned int drif3_data1_a_pins[] = {
2018 /* D1 */
2019 RCAR_GP_PIN(6, 20),
2020 };
2021 static const unsigned int drif3_data1_a_mux[] = {
2022 RIF3_D1_A_MARK,
2023 };
2024 static const unsigned int drif3_ctrl_b_pins[] = {
2025 /* CLK, SYNC */
2026 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2027 };
2028 static const unsigned int drif3_ctrl_b_mux[] = {
2029 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2030 };
2031 static const unsigned int drif3_data0_b_pins[] = {
2032 /* D0 */
2033 RCAR_GP_PIN(6, 28),
2034 };
2035 static const unsigned int drif3_data0_b_mux[] = {
2036 RIF3_D0_B_MARK,
2037 };
2038 static const unsigned int drif3_data1_b_pins[] = {
2039 /* D1 */
2040 RCAR_GP_PIN(6, 29),
2041 };
2042 static const unsigned int drif3_data1_b_mux[] = {
2043 RIF3_D1_B_MARK,
2044 };
2045 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2046
2047 /* - DU --------------------------------------------------------------------- */
2048 static const unsigned int du_rgb666_pins[] = {
2049 /* R[7:2], G[7:2], B[7:2] */
2050 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2051 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2052 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2053 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2054 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2055 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2056 };
2057 static const unsigned int du_rgb666_mux[] = {
2058 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2059 DU_DR3_MARK, DU_DR2_MARK,
2060 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2061 DU_DG3_MARK, DU_DG2_MARK,
2062 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2063 DU_DB3_MARK, DU_DB2_MARK,
2064 };
2065 static const unsigned int du_rgb888_pins[] = {
2066 /* R[7:0], G[7:0], B[7:0] */
2067 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2068 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2069 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2070 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2071 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2072 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2073 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2074 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2075 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2076 };
2077 static const unsigned int du_rgb888_mux[] = {
2078 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2079 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2080 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2081 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2082 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2083 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2084 };
2085 static const unsigned int du_clk_out_0_pins[] = {
2086 /* CLKOUT */
2087 RCAR_GP_PIN(1, 27),
2088 };
2089 static const unsigned int du_clk_out_0_mux[] = {
2090 DU_DOTCLKOUT0_MARK
2091 };
2092 static const unsigned int du_clk_out_1_pins[] = {
2093 /* CLKOUT */
2094 RCAR_GP_PIN(2, 3),
2095 };
2096 static const unsigned int du_clk_out_1_mux[] = {
2097 DU_DOTCLKOUT1_MARK
2098 };
2099 static const unsigned int du_sync_pins[] = {
2100 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2101 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2102 };
2103 static const unsigned int du_sync_mux[] = {
2104 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2105 };
2106 static const unsigned int du_oddf_pins[] = {
2107 /* EXDISP/EXODDF/EXCDE */
2108 RCAR_GP_PIN(2, 2),
2109 };
2110 static const unsigned int du_oddf_mux[] = {
2111 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2112 };
2113 static const unsigned int du_cde_pins[] = {
2114 /* CDE */
2115 RCAR_GP_PIN(2, 0),
2116 };
2117 static const unsigned int du_cde_mux[] = {
2118 DU_CDE_MARK,
2119 };
2120 static const unsigned int du_disp_pins[] = {
2121 /* DISP */
2122 RCAR_GP_PIN(2, 1),
2123 };
2124 static const unsigned int du_disp_mux[] = {
2125 DU_DISP_MARK,
2126 };
2127
2128 /* - HSCIF0 ----------------------------------------------------------------- */
2129 static const unsigned int hscif0_data_pins[] = {
2130 /* RX, TX */
2131 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2132 };
2133 static const unsigned int hscif0_data_mux[] = {
2134 HRX0_MARK, HTX0_MARK,
2135 };
2136 static const unsigned int hscif0_clk_pins[] = {
2137 /* SCK */
2138 RCAR_GP_PIN(5, 12),
2139 };
2140 static const unsigned int hscif0_clk_mux[] = {
2141 HSCK0_MARK,
2142 };
2143 static const unsigned int hscif0_ctrl_pins[] = {
2144 /* RTS, CTS */
2145 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2146 };
2147 static const unsigned int hscif0_ctrl_mux[] = {
2148 HRTS0_N_MARK, HCTS0_N_MARK,
2149 };
2150 /* - HSCIF1 ----------------------------------------------------------------- */
2151 static const unsigned int hscif1_data_a_pins[] = {
2152 /* RX, TX */
2153 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2154 };
2155 static const unsigned int hscif1_data_a_mux[] = {
2156 HRX1_A_MARK, HTX1_A_MARK,
2157 };
2158 static const unsigned int hscif1_clk_a_pins[] = {
2159 /* SCK */
2160 RCAR_GP_PIN(6, 21),
2161 };
2162 static const unsigned int hscif1_clk_a_mux[] = {
2163 HSCK1_A_MARK,
2164 };
2165 static const unsigned int hscif1_ctrl_a_pins[] = {
2166 /* RTS, CTS */
2167 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2168 };
2169 static const unsigned int hscif1_ctrl_a_mux[] = {
2170 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2171 };
2172
2173 static const unsigned int hscif1_data_b_pins[] = {
2174 /* RX, TX */
2175 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2176 };
2177 static const unsigned int hscif1_data_b_mux[] = {
2178 HRX1_B_MARK, HTX1_B_MARK,
2179 };
2180 static const unsigned int hscif1_clk_b_pins[] = {
2181 /* SCK */
2182 RCAR_GP_PIN(5, 0),
2183 };
2184 static const unsigned int hscif1_clk_b_mux[] = {
2185 HSCK1_B_MARK,
2186 };
2187 static const unsigned int hscif1_ctrl_b_pins[] = {
2188 /* RTS, CTS */
2189 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2190 };
2191 static const unsigned int hscif1_ctrl_b_mux[] = {
2192 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2193 };
2194 /* - HSCIF2 ----------------------------------------------------------------- */
2195 static const unsigned int hscif2_data_a_pins[] = {
2196 /* RX, TX */
2197 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2198 };
2199 static const unsigned int hscif2_data_a_mux[] = {
2200 HRX2_A_MARK, HTX2_A_MARK,
2201 };
2202 static const unsigned int hscif2_clk_a_pins[] = {
2203 /* SCK */
2204 RCAR_GP_PIN(6, 10),
2205 };
2206 static const unsigned int hscif2_clk_a_mux[] = {
2207 HSCK2_A_MARK,
2208 };
2209 static const unsigned int hscif2_ctrl_a_pins[] = {
2210 /* RTS, CTS */
2211 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2212 };
2213 static const unsigned int hscif2_ctrl_a_mux[] = {
2214 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2215 };
2216
2217 static const unsigned int hscif2_data_b_pins[] = {
2218 /* RX, TX */
2219 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2220 };
2221 static const unsigned int hscif2_data_b_mux[] = {
2222 HRX2_B_MARK, HTX2_B_MARK,
2223 };
2224 static const unsigned int hscif2_clk_b_pins[] = {
2225 /* SCK */
2226 RCAR_GP_PIN(6, 21),
2227 };
2228 static const unsigned int hscif2_clk_b_mux[] = {
2229 HSCK2_B_MARK,
2230 };
2231 static const unsigned int hscif2_ctrl_b_pins[] = {
2232 /* RTS, CTS */
2233 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2234 };
2235 static const unsigned int hscif2_ctrl_b_mux[] = {
2236 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2237 };
2238
2239 static const unsigned int hscif2_data_c_pins[] = {
2240 /* RX, TX */
2241 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2242 };
2243 static const unsigned int hscif2_data_c_mux[] = {
2244 HRX2_C_MARK, HTX2_C_MARK,
2245 };
2246 static const unsigned int hscif2_clk_c_pins[] = {
2247 /* SCK */
2248 RCAR_GP_PIN(6, 24),
2249 };
2250 static const unsigned int hscif2_clk_c_mux[] = {
2251 HSCK2_C_MARK,
2252 };
2253 static const unsigned int hscif2_ctrl_c_pins[] = {
2254 /* RTS, CTS */
2255 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2256 };
2257 static const unsigned int hscif2_ctrl_c_mux[] = {
2258 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2259 };
2260 /* - HSCIF3 ----------------------------------------------------------------- */
2261 static const unsigned int hscif3_data_a_pins[] = {
2262 /* RX, TX */
2263 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2264 };
2265 static const unsigned int hscif3_data_a_mux[] = {
2266 HRX3_A_MARK, HTX3_A_MARK,
2267 };
2268 static const unsigned int hscif3_clk_pins[] = {
2269 /* SCK */
2270 RCAR_GP_PIN(1, 22),
2271 };
2272 static const unsigned int hscif3_clk_mux[] = {
2273 HSCK3_MARK,
2274 };
2275 static const unsigned int hscif3_ctrl_pins[] = {
2276 /* RTS, CTS */
2277 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2278 };
2279 static const unsigned int hscif3_ctrl_mux[] = {
2280 HRTS3_N_MARK, HCTS3_N_MARK,
2281 };
2282
2283 static const unsigned int hscif3_data_b_pins[] = {
2284 /* RX, TX */
2285 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2286 };
2287 static const unsigned int hscif3_data_b_mux[] = {
2288 HRX3_B_MARK, HTX3_B_MARK,
2289 };
2290 static const unsigned int hscif3_data_c_pins[] = {
2291 /* RX, TX */
2292 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2293 };
2294 static const unsigned int hscif3_data_c_mux[] = {
2295 HRX3_C_MARK, HTX3_C_MARK,
2296 };
2297 static const unsigned int hscif3_data_d_pins[] = {
2298 /* RX, TX */
2299 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2300 };
2301 static const unsigned int hscif3_data_d_mux[] = {
2302 HRX3_D_MARK, HTX3_D_MARK,
2303 };
2304 /* - HSCIF4 ----------------------------------------------------------------- */
2305 static const unsigned int hscif4_data_a_pins[] = {
2306 /* RX, TX */
2307 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2308 };
2309 static const unsigned int hscif4_data_a_mux[] = {
2310 HRX4_A_MARK, HTX4_A_MARK,
2311 };
2312 static const unsigned int hscif4_clk_pins[] = {
2313 /* SCK */
2314 RCAR_GP_PIN(1, 11),
2315 };
2316 static const unsigned int hscif4_clk_mux[] = {
2317 HSCK4_MARK,
2318 };
2319 static const unsigned int hscif4_ctrl_pins[] = {
2320 /* RTS, CTS */
2321 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2322 };
2323 static const unsigned int hscif4_ctrl_mux[] = {
2324 HRTS4_N_MARK, HCTS4_N_MARK,
2325 };
2326
2327 static const unsigned int hscif4_data_b_pins[] = {
2328 /* RX, TX */
2329 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2330 };
2331 static const unsigned int hscif4_data_b_mux[] = {
2332 HRX4_B_MARK, HTX4_B_MARK,
2333 };
2334
2335 /* - I2C -------------------------------------------------------------------- */
2336 static const unsigned int i2c0_pins[] = {
2337 /* SCL, SDA */
2338 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2339 };
2340
2341 static const unsigned int i2c0_mux[] = {
2342 SCL0_MARK, SDA0_MARK,
2343 };
2344
2345 static const unsigned int i2c1_a_pins[] = {
2346 /* SDA, SCL */
2347 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2348 };
2349 static const unsigned int i2c1_a_mux[] = {
2350 SDA1_A_MARK, SCL1_A_MARK,
2351 };
2352 static const unsigned int i2c1_b_pins[] = {
2353 /* SDA, SCL */
2354 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2355 };
2356 static const unsigned int i2c1_b_mux[] = {
2357 SDA1_B_MARK, SCL1_B_MARK,
2358 };
2359 static const unsigned int i2c2_a_pins[] = {
2360 /* SDA, SCL */
2361 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2362 };
2363 static const unsigned int i2c2_a_mux[] = {
2364 SDA2_A_MARK, SCL2_A_MARK,
2365 };
2366 static const unsigned int i2c2_b_pins[] = {
2367 /* SDA, SCL */
2368 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2369 };
2370 static const unsigned int i2c2_b_mux[] = {
2371 SDA2_B_MARK, SCL2_B_MARK,
2372 };
2373
2374 static const unsigned int i2c3_pins[] = {
2375 /* SCL, SDA */
2376 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2377 };
2378
2379 static const unsigned int i2c3_mux[] = {
2380 SCL3_MARK, SDA3_MARK,
2381 };
2382
2383 static const unsigned int i2c5_pins[] = {
2384 /* SCL, SDA */
2385 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2386 };
2387
2388 static const unsigned int i2c5_mux[] = {
2389 SCL5_MARK, SDA5_MARK,
2390 };
2391
2392 static const unsigned int i2c6_a_pins[] = {
2393 /* SDA, SCL */
2394 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2395 };
2396 static const unsigned int i2c6_a_mux[] = {
2397 SDA6_A_MARK, SCL6_A_MARK,
2398 };
2399 static const unsigned int i2c6_b_pins[] = {
2400 /* SDA, SCL */
2401 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2402 };
2403 static const unsigned int i2c6_b_mux[] = {
2404 SDA6_B_MARK, SCL6_B_MARK,
2405 };
2406 static const unsigned int i2c6_c_pins[] = {
2407 /* SDA, SCL */
2408 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2409 };
2410 static const unsigned int i2c6_c_mux[] = {
2411 SDA6_C_MARK, SCL6_C_MARK,
2412 };
2413
2414 /* - INTC-EX ---------------------------------------------------------------- */
2415 static const unsigned int intc_ex_irq0_pins[] = {
2416 /* IRQ0 */
2417 RCAR_GP_PIN(2, 0),
2418 };
2419 static const unsigned int intc_ex_irq0_mux[] = {
2420 IRQ0_MARK,
2421 };
2422 static const unsigned int intc_ex_irq1_pins[] = {
2423 /* IRQ1 */
2424 RCAR_GP_PIN(2, 1),
2425 };
2426 static const unsigned int intc_ex_irq1_mux[] = {
2427 IRQ1_MARK,
2428 };
2429 static const unsigned int intc_ex_irq2_pins[] = {
2430 /* IRQ2 */
2431 RCAR_GP_PIN(2, 2),
2432 };
2433 static const unsigned int intc_ex_irq2_mux[] = {
2434 IRQ2_MARK,
2435 };
2436 static const unsigned int intc_ex_irq3_pins[] = {
2437 /* IRQ3 */
2438 RCAR_GP_PIN(2, 3),
2439 };
2440 static const unsigned int intc_ex_irq3_mux[] = {
2441 IRQ3_MARK,
2442 };
2443 static const unsigned int intc_ex_irq4_pins[] = {
2444 /* IRQ4 */
2445 RCAR_GP_PIN(2, 4),
2446 };
2447 static const unsigned int intc_ex_irq4_mux[] = {
2448 IRQ4_MARK,
2449 };
2450 static const unsigned int intc_ex_irq5_pins[] = {
2451 /* IRQ5 */
2452 RCAR_GP_PIN(2, 5),
2453 };
2454 static const unsigned int intc_ex_irq5_mux[] = {
2455 IRQ5_MARK,
2456 };
2457
2458 /* - MSIOF0 ----------------------------------------------------------------- */
2459 static const unsigned int msiof0_clk_pins[] = {
2460 /* SCK */
2461 RCAR_GP_PIN(5, 17),
2462 };
2463 static const unsigned int msiof0_clk_mux[] = {
2464 MSIOF0_SCK_MARK,
2465 };
2466 static const unsigned int msiof0_sync_pins[] = {
2467 /* SYNC */
2468 RCAR_GP_PIN(5, 18),
2469 };
2470 static const unsigned int msiof0_sync_mux[] = {
2471 MSIOF0_SYNC_MARK,
2472 };
2473 static const unsigned int msiof0_ss1_pins[] = {
2474 /* SS1 */
2475 RCAR_GP_PIN(5, 19),
2476 };
2477 static const unsigned int msiof0_ss1_mux[] = {
2478 MSIOF0_SS1_MARK,
2479 };
2480 static const unsigned int msiof0_ss2_pins[] = {
2481 /* SS2 */
2482 RCAR_GP_PIN(5, 21),
2483 };
2484 static const unsigned int msiof0_ss2_mux[] = {
2485 MSIOF0_SS2_MARK,
2486 };
2487 static const unsigned int msiof0_txd_pins[] = {
2488 /* TXD */
2489 RCAR_GP_PIN(5, 20),
2490 };
2491 static const unsigned int msiof0_txd_mux[] = {
2492 MSIOF0_TXD_MARK,
2493 };
2494 static const unsigned int msiof0_rxd_pins[] = {
2495 /* RXD */
2496 RCAR_GP_PIN(5, 22),
2497 };
2498 static const unsigned int msiof0_rxd_mux[] = {
2499 MSIOF0_RXD_MARK,
2500 };
2501 /* - MSIOF1 ----------------------------------------------------------------- */
2502 static const unsigned int msiof1_clk_a_pins[] = {
2503 /* SCK */
2504 RCAR_GP_PIN(6, 8),
2505 };
2506 static const unsigned int msiof1_clk_a_mux[] = {
2507 MSIOF1_SCK_A_MARK,
2508 };
2509 static const unsigned int msiof1_sync_a_pins[] = {
2510 /* SYNC */
2511 RCAR_GP_PIN(6, 9),
2512 };
2513 static const unsigned int msiof1_sync_a_mux[] = {
2514 MSIOF1_SYNC_A_MARK,
2515 };
2516 static const unsigned int msiof1_ss1_a_pins[] = {
2517 /* SS1 */
2518 RCAR_GP_PIN(6, 5),
2519 };
2520 static const unsigned int msiof1_ss1_a_mux[] = {
2521 MSIOF1_SS1_A_MARK,
2522 };
2523 static const unsigned int msiof1_ss2_a_pins[] = {
2524 /* SS2 */
2525 RCAR_GP_PIN(6, 6),
2526 };
2527 static const unsigned int msiof1_ss2_a_mux[] = {
2528 MSIOF1_SS2_A_MARK,
2529 };
2530 static const unsigned int msiof1_txd_a_pins[] = {
2531 /* TXD */
2532 RCAR_GP_PIN(6, 7),
2533 };
2534 static const unsigned int msiof1_txd_a_mux[] = {
2535 MSIOF1_TXD_A_MARK,
2536 };
2537 static const unsigned int msiof1_rxd_a_pins[] = {
2538 /* RXD */
2539 RCAR_GP_PIN(6, 10),
2540 };
2541 static const unsigned int msiof1_rxd_a_mux[] = {
2542 MSIOF1_RXD_A_MARK,
2543 };
2544 static const unsigned int msiof1_clk_b_pins[] = {
2545 /* SCK */
2546 RCAR_GP_PIN(5, 9),
2547 };
2548 static const unsigned int msiof1_clk_b_mux[] = {
2549 MSIOF1_SCK_B_MARK,
2550 };
2551 static const unsigned int msiof1_sync_b_pins[] = {
2552 /* SYNC */
2553 RCAR_GP_PIN(5, 3),
2554 };
2555 static const unsigned int msiof1_sync_b_mux[] = {
2556 MSIOF1_SYNC_B_MARK,
2557 };
2558 static const unsigned int msiof1_ss1_b_pins[] = {
2559 /* SS1 */
2560 RCAR_GP_PIN(5, 4),
2561 };
2562 static const unsigned int msiof1_ss1_b_mux[] = {
2563 MSIOF1_SS1_B_MARK,
2564 };
2565 static const unsigned int msiof1_ss2_b_pins[] = {
2566 /* SS2 */
2567 RCAR_GP_PIN(5, 0),
2568 };
2569 static const unsigned int msiof1_ss2_b_mux[] = {
2570 MSIOF1_SS2_B_MARK,
2571 };
2572 static const unsigned int msiof1_txd_b_pins[] = {
2573 /* TXD */
2574 RCAR_GP_PIN(5, 8),
2575 };
2576 static const unsigned int msiof1_txd_b_mux[] = {
2577 MSIOF1_TXD_B_MARK,
2578 };
2579 static const unsigned int msiof1_rxd_b_pins[] = {
2580 /* RXD */
2581 RCAR_GP_PIN(5, 7),
2582 };
2583 static const unsigned int msiof1_rxd_b_mux[] = {
2584 MSIOF1_RXD_B_MARK,
2585 };
2586 static const unsigned int msiof1_clk_c_pins[] = {
2587 /* SCK */
2588 RCAR_GP_PIN(6, 17),
2589 };
2590 static const unsigned int msiof1_clk_c_mux[] = {
2591 MSIOF1_SCK_C_MARK,
2592 };
2593 static const unsigned int msiof1_sync_c_pins[] = {
2594 /* SYNC */
2595 RCAR_GP_PIN(6, 18),
2596 };
2597 static const unsigned int msiof1_sync_c_mux[] = {
2598 MSIOF1_SYNC_C_MARK,
2599 };
2600 static const unsigned int msiof1_ss1_c_pins[] = {
2601 /* SS1 */
2602 RCAR_GP_PIN(6, 21),
2603 };
2604 static const unsigned int msiof1_ss1_c_mux[] = {
2605 MSIOF1_SS1_C_MARK,
2606 };
2607 static const unsigned int msiof1_ss2_c_pins[] = {
2608 /* SS2 */
2609 RCAR_GP_PIN(6, 27),
2610 };
2611 static const unsigned int msiof1_ss2_c_mux[] = {
2612 MSIOF1_SS2_C_MARK,
2613 };
2614 static const unsigned int msiof1_txd_c_pins[] = {
2615 /* TXD */
2616 RCAR_GP_PIN(6, 20),
2617 };
2618 static const unsigned int msiof1_txd_c_mux[] = {
2619 MSIOF1_TXD_C_MARK,
2620 };
2621 static const unsigned int msiof1_rxd_c_pins[] = {
2622 /* RXD */
2623 RCAR_GP_PIN(6, 19),
2624 };
2625 static const unsigned int msiof1_rxd_c_mux[] = {
2626 MSIOF1_RXD_C_MARK,
2627 };
2628 static const unsigned int msiof1_clk_d_pins[] = {
2629 /* SCK */
2630 RCAR_GP_PIN(5, 12),
2631 };
2632 static const unsigned int msiof1_clk_d_mux[] = {
2633 MSIOF1_SCK_D_MARK,
2634 };
2635 static const unsigned int msiof1_sync_d_pins[] = {
2636 /* SYNC */
2637 RCAR_GP_PIN(5, 15),
2638 };
2639 static const unsigned int msiof1_sync_d_mux[] = {
2640 MSIOF1_SYNC_D_MARK,
2641 };
2642 static const unsigned int msiof1_ss1_d_pins[] = {
2643 /* SS1 */
2644 RCAR_GP_PIN(5, 16),
2645 };
2646 static const unsigned int msiof1_ss1_d_mux[] = {
2647 MSIOF1_SS1_D_MARK,
2648 };
2649 static const unsigned int msiof1_ss2_d_pins[] = {
2650 /* SS2 */
2651 RCAR_GP_PIN(5, 21),
2652 };
2653 static const unsigned int msiof1_ss2_d_mux[] = {
2654 MSIOF1_SS2_D_MARK,
2655 };
2656 static const unsigned int msiof1_txd_d_pins[] = {
2657 /* TXD */
2658 RCAR_GP_PIN(5, 14),
2659 };
2660 static const unsigned int msiof1_txd_d_mux[] = {
2661 MSIOF1_TXD_D_MARK,
2662 };
2663 static const unsigned int msiof1_rxd_d_pins[] = {
2664 /* RXD */
2665 RCAR_GP_PIN(5, 13),
2666 };
2667 static const unsigned int msiof1_rxd_d_mux[] = {
2668 MSIOF1_RXD_D_MARK,
2669 };
2670 static const unsigned int msiof1_clk_e_pins[] = {
2671 /* SCK */
2672 RCAR_GP_PIN(3, 0),
2673 };
2674 static const unsigned int msiof1_clk_e_mux[] = {
2675 MSIOF1_SCK_E_MARK,
2676 };
2677 static const unsigned int msiof1_sync_e_pins[] = {
2678 /* SYNC */
2679 RCAR_GP_PIN(3, 1),
2680 };
2681 static const unsigned int msiof1_sync_e_mux[] = {
2682 MSIOF1_SYNC_E_MARK,
2683 };
2684 static const unsigned int msiof1_ss1_e_pins[] = {
2685 /* SS1 */
2686 RCAR_GP_PIN(3, 4),
2687 };
2688 static const unsigned int msiof1_ss1_e_mux[] = {
2689 MSIOF1_SS1_E_MARK,
2690 };
2691 static const unsigned int msiof1_ss2_e_pins[] = {
2692 /* SS2 */
2693 RCAR_GP_PIN(3, 5),
2694 };
2695 static const unsigned int msiof1_ss2_e_mux[] = {
2696 MSIOF1_SS2_E_MARK,
2697 };
2698 static const unsigned int msiof1_txd_e_pins[] = {
2699 /* TXD */
2700 RCAR_GP_PIN(3, 3),
2701 };
2702 static const unsigned int msiof1_txd_e_mux[] = {
2703 MSIOF1_TXD_E_MARK,
2704 };
2705 static const unsigned int msiof1_rxd_e_pins[] = {
2706 /* RXD */
2707 RCAR_GP_PIN(3, 2),
2708 };
2709 static const unsigned int msiof1_rxd_e_mux[] = {
2710 MSIOF1_RXD_E_MARK,
2711 };
2712 static const unsigned int msiof1_clk_f_pins[] = {
2713 /* SCK */
2714 RCAR_GP_PIN(5, 23),
2715 };
2716 static const unsigned int msiof1_clk_f_mux[] = {
2717 MSIOF1_SCK_F_MARK,
2718 };
2719 static const unsigned int msiof1_sync_f_pins[] = {
2720 /* SYNC */
2721 RCAR_GP_PIN(5, 24),
2722 };
2723 static const unsigned int msiof1_sync_f_mux[] = {
2724 MSIOF1_SYNC_F_MARK,
2725 };
2726 static const unsigned int msiof1_ss1_f_pins[] = {
2727 /* SS1 */
2728 RCAR_GP_PIN(6, 1),
2729 };
2730 static const unsigned int msiof1_ss1_f_mux[] = {
2731 MSIOF1_SS1_F_MARK,
2732 };
2733 static const unsigned int msiof1_ss2_f_pins[] = {
2734 /* SS2 */
2735 RCAR_GP_PIN(6, 2),
2736 };
2737 static const unsigned int msiof1_ss2_f_mux[] = {
2738 MSIOF1_SS2_F_MARK,
2739 };
2740 static const unsigned int msiof1_txd_f_pins[] = {
2741 /* TXD */
2742 RCAR_GP_PIN(6, 0),
2743 };
2744 static const unsigned int msiof1_txd_f_mux[] = {
2745 MSIOF1_TXD_F_MARK,
2746 };
2747 static const unsigned int msiof1_rxd_f_pins[] = {
2748 /* RXD */
2749 RCAR_GP_PIN(5, 25),
2750 };
2751 static const unsigned int msiof1_rxd_f_mux[] = {
2752 MSIOF1_RXD_F_MARK,
2753 };
2754 static const unsigned int msiof1_clk_g_pins[] = {
2755 /* SCK */
2756 RCAR_GP_PIN(3, 6),
2757 };
2758 static const unsigned int msiof1_clk_g_mux[] = {
2759 MSIOF1_SCK_G_MARK,
2760 };
2761 static const unsigned int msiof1_sync_g_pins[] = {
2762 /* SYNC */
2763 RCAR_GP_PIN(3, 7),
2764 };
2765 static const unsigned int msiof1_sync_g_mux[] = {
2766 MSIOF1_SYNC_G_MARK,
2767 };
2768 static const unsigned int msiof1_ss1_g_pins[] = {
2769 /* SS1 */
2770 RCAR_GP_PIN(3, 10),
2771 };
2772 static const unsigned int msiof1_ss1_g_mux[] = {
2773 MSIOF1_SS1_G_MARK,
2774 };
2775 static const unsigned int msiof1_ss2_g_pins[] = {
2776 /* SS2 */
2777 RCAR_GP_PIN(3, 11),
2778 };
2779 static const unsigned int msiof1_ss2_g_mux[] = {
2780 MSIOF1_SS2_G_MARK,
2781 };
2782 static const unsigned int msiof1_txd_g_pins[] = {
2783 /* TXD */
2784 RCAR_GP_PIN(3, 9),
2785 };
2786 static const unsigned int msiof1_txd_g_mux[] = {
2787 MSIOF1_TXD_G_MARK,
2788 };
2789 static const unsigned int msiof1_rxd_g_pins[] = {
2790 /* RXD */
2791 RCAR_GP_PIN(3, 8),
2792 };
2793 static const unsigned int msiof1_rxd_g_mux[] = {
2794 MSIOF1_RXD_G_MARK,
2795 };
2796 /* - MSIOF2 ----------------------------------------------------------------- */
2797 static const unsigned int msiof2_clk_a_pins[] = {
2798 /* SCK */
2799 RCAR_GP_PIN(1, 9),
2800 };
2801 static const unsigned int msiof2_clk_a_mux[] = {
2802 MSIOF2_SCK_A_MARK,
2803 };
2804 static const unsigned int msiof2_sync_a_pins[] = {
2805 /* SYNC */
2806 RCAR_GP_PIN(1, 8),
2807 };
2808 static const unsigned int msiof2_sync_a_mux[] = {
2809 MSIOF2_SYNC_A_MARK,
2810 };
2811 static const unsigned int msiof2_ss1_a_pins[] = {
2812 /* SS1 */
2813 RCAR_GP_PIN(1, 6),
2814 };
2815 static const unsigned int msiof2_ss1_a_mux[] = {
2816 MSIOF2_SS1_A_MARK,
2817 };
2818 static const unsigned int msiof2_ss2_a_pins[] = {
2819 /* SS2 */
2820 RCAR_GP_PIN(1, 7),
2821 };
2822 static const unsigned int msiof2_ss2_a_mux[] = {
2823 MSIOF2_SS2_A_MARK,
2824 };
2825 static const unsigned int msiof2_txd_a_pins[] = {
2826 /* TXD */
2827 RCAR_GP_PIN(1, 11),
2828 };
2829 static const unsigned int msiof2_txd_a_mux[] = {
2830 MSIOF2_TXD_A_MARK,
2831 };
2832 static const unsigned int msiof2_rxd_a_pins[] = {
2833 /* RXD */
2834 RCAR_GP_PIN(1, 10),
2835 };
2836 static const unsigned int msiof2_rxd_a_mux[] = {
2837 MSIOF2_RXD_A_MARK,
2838 };
2839 static const unsigned int msiof2_clk_b_pins[] = {
2840 /* SCK */
2841 RCAR_GP_PIN(0, 4),
2842 };
2843 static const unsigned int msiof2_clk_b_mux[] = {
2844 MSIOF2_SCK_B_MARK,
2845 };
2846 static const unsigned int msiof2_sync_b_pins[] = {
2847 /* SYNC */
2848 RCAR_GP_PIN(0, 5),
2849 };
2850 static const unsigned int msiof2_sync_b_mux[] = {
2851 MSIOF2_SYNC_B_MARK,
2852 };
2853 static const unsigned int msiof2_ss1_b_pins[] = {
2854 /* SS1 */
2855 RCAR_GP_PIN(0, 0),
2856 };
2857 static const unsigned int msiof2_ss1_b_mux[] = {
2858 MSIOF2_SS1_B_MARK,
2859 };
2860 static const unsigned int msiof2_ss2_b_pins[] = {
2861 /* SS2 */
2862 RCAR_GP_PIN(0, 1),
2863 };
2864 static const unsigned int msiof2_ss2_b_mux[] = {
2865 MSIOF2_SS2_B_MARK,
2866 };
2867 static const unsigned int msiof2_txd_b_pins[] = {
2868 /* TXD */
2869 RCAR_GP_PIN(0, 7),
2870 };
2871 static const unsigned int msiof2_txd_b_mux[] = {
2872 MSIOF2_TXD_B_MARK,
2873 };
2874 static const unsigned int msiof2_rxd_b_pins[] = {
2875 /* RXD */
2876 RCAR_GP_PIN(0, 6),
2877 };
2878 static const unsigned int msiof2_rxd_b_mux[] = {
2879 MSIOF2_RXD_B_MARK,
2880 };
2881 static const unsigned int msiof2_clk_c_pins[] = {
2882 /* SCK */
2883 RCAR_GP_PIN(2, 12),
2884 };
2885 static const unsigned int msiof2_clk_c_mux[] = {
2886 MSIOF2_SCK_C_MARK,
2887 };
2888 static const unsigned int msiof2_sync_c_pins[] = {
2889 /* SYNC */
2890 RCAR_GP_PIN(2, 11),
2891 };
2892 static const unsigned int msiof2_sync_c_mux[] = {
2893 MSIOF2_SYNC_C_MARK,
2894 };
2895 static const unsigned int msiof2_ss1_c_pins[] = {
2896 /* SS1 */
2897 RCAR_GP_PIN(2, 10),
2898 };
2899 static const unsigned int msiof2_ss1_c_mux[] = {
2900 MSIOF2_SS1_C_MARK,
2901 };
2902 static const unsigned int msiof2_ss2_c_pins[] = {
2903 /* SS2 */
2904 RCAR_GP_PIN(2, 9),
2905 };
2906 static const unsigned int msiof2_ss2_c_mux[] = {
2907 MSIOF2_SS2_C_MARK,
2908 };
2909 static const unsigned int msiof2_txd_c_pins[] = {
2910 /* TXD */
2911 RCAR_GP_PIN(2, 14),
2912 };
2913 static const unsigned int msiof2_txd_c_mux[] = {
2914 MSIOF2_TXD_C_MARK,
2915 };
2916 static const unsigned int msiof2_rxd_c_pins[] = {
2917 /* RXD */
2918 RCAR_GP_PIN(2, 13),
2919 };
2920 static const unsigned int msiof2_rxd_c_mux[] = {
2921 MSIOF2_RXD_C_MARK,
2922 };
2923 static const unsigned int msiof2_clk_d_pins[] = {
2924 /* SCK */
2925 RCAR_GP_PIN(0, 8),
2926 };
2927 static const unsigned int msiof2_clk_d_mux[] = {
2928 MSIOF2_SCK_D_MARK,
2929 };
2930 static const unsigned int msiof2_sync_d_pins[] = {
2931 /* SYNC */
2932 RCAR_GP_PIN(0, 9),
2933 };
2934 static const unsigned int msiof2_sync_d_mux[] = {
2935 MSIOF2_SYNC_D_MARK,
2936 };
2937 static const unsigned int msiof2_ss1_d_pins[] = {
2938 /* SS1 */
2939 RCAR_GP_PIN(0, 12),
2940 };
2941 static const unsigned int msiof2_ss1_d_mux[] = {
2942 MSIOF2_SS1_D_MARK,
2943 };
2944 static const unsigned int msiof2_ss2_d_pins[] = {
2945 /* SS2 */
2946 RCAR_GP_PIN(0, 13),
2947 };
2948 static const unsigned int msiof2_ss2_d_mux[] = {
2949 MSIOF2_SS2_D_MARK,
2950 };
2951 static const unsigned int msiof2_txd_d_pins[] = {
2952 /* TXD */
2953 RCAR_GP_PIN(0, 11),
2954 };
2955 static const unsigned int msiof2_txd_d_mux[] = {
2956 MSIOF2_TXD_D_MARK,
2957 };
2958 static const unsigned int msiof2_rxd_d_pins[] = {
2959 /* RXD */
2960 RCAR_GP_PIN(0, 10),
2961 };
2962 static const unsigned int msiof2_rxd_d_mux[] = {
2963 MSIOF2_RXD_D_MARK,
2964 };
2965 /* - MSIOF3 ----------------------------------------------------------------- */
2966 static const unsigned int msiof3_clk_a_pins[] = {
2967 /* SCK */
2968 RCAR_GP_PIN(0, 0),
2969 };
2970 static const unsigned int msiof3_clk_a_mux[] = {
2971 MSIOF3_SCK_A_MARK,
2972 };
2973 static const unsigned int msiof3_sync_a_pins[] = {
2974 /* SYNC */
2975 RCAR_GP_PIN(0, 1),
2976 };
2977 static const unsigned int msiof3_sync_a_mux[] = {
2978 MSIOF3_SYNC_A_MARK,
2979 };
2980 static const unsigned int msiof3_ss1_a_pins[] = {
2981 /* SS1 */
2982 RCAR_GP_PIN(0, 14),
2983 };
2984 static const unsigned int msiof3_ss1_a_mux[] = {
2985 MSIOF3_SS1_A_MARK,
2986 };
2987 static const unsigned int msiof3_ss2_a_pins[] = {
2988 /* SS2 */
2989 RCAR_GP_PIN(0, 15),
2990 };
2991 static const unsigned int msiof3_ss2_a_mux[] = {
2992 MSIOF3_SS2_A_MARK,
2993 };
2994 static const unsigned int msiof3_txd_a_pins[] = {
2995 /* TXD */
2996 RCAR_GP_PIN(0, 3),
2997 };
2998 static const unsigned int msiof3_txd_a_mux[] = {
2999 MSIOF3_TXD_A_MARK,
3000 };
3001 static const unsigned int msiof3_rxd_a_pins[] = {
3002 /* RXD */
3003 RCAR_GP_PIN(0, 2),
3004 };
3005 static const unsigned int msiof3_rxd_a_mux[] = {
3006 MSIOF3_RXD_A_MARK,
3007 };
3008 static const unsigned int msiof3_clk_b_pins[] = {
3009 /* SCK */
3010 RCAR_GP_PIN(1, 2),
3011 };
3012 static const unsigned int msiof3_clk_b_mux[] = {
3013 MSIOF3_SCK_B_MARK,
3014 };
3015 static const unsigned int msiof3_sync_b_pins[] = {
3016 /* SYNC */
3017 RCAR_GP_PIN(1, 0),
3018 };
3019 static const unsigned int msiof3_sync_b_mux[] = {
3020 MSIOF3_SYNC_B_MARK,
3021 };
3022 static const unsigned int msiof3_ss1_b_pins[] = {
3023 /* SS1 */
3024 RCAR_GP_PIN(1, 4),
3025 };
3026 static const unsigned int msiof3_ss1_b_mux[] = {
3027 MSIOF3_SS1_B_MARK,
3028 };
3029 static const unsigned int msiof3_ss2_b_pins[] = {
3030 /* SS2 */
3031 RCAR_GP_PIN(1, 5),
3032 };
3033 static const unsigned int msiof3_ss2_b_mux[] = {
3034 MSIOF3_SS2_B_MARK,
3035 };
3036 static const unsigned int msiof3_txd_b_pins[] = {
3037 /* TXD */
3038 RCAR_GP_PIN(1, 1),
3039 };
3040 static const unsigned int msiof3_txd_b_mux[] = {
3041 MSIOF3_TXD_B_MARK,
3042 };
3043 static const unsigned int msiof3_rxd_b_pins[] = {
3044 /* RXD */
3045 RCAR_GP_PIN(1, 3),
3046 };
3047 static const unsigned int msiof3_rxd_b_mux[] = {
3048 MSIOF3_RXD_B_MARK,
3049 };
3050 static const unsigned int msiof3_clk_c_pins[] = {
3051 /* SCK */
3052 RCAR_GP_PIN(1, 12),
3053 };
3054 static const unsigned int msiof3_clk_c_mux[] = {
3055 MSIOF3_SCK_C_MARK,
3056 };
3057 static const unsigned int msiof3_sync_c_pins[] = {
3058 /* SYNC */
3059 RCAR_GP_PIN(1, 13),
3060 };
3061 static const unsigned int msiof3_sync_c_mux[] = {
3062 MSIOF3_SYNC_C_MARK,
3063 };
3064 static const unsigned int msiof3_txd_c_pins[] = {
3065 /* TXD */
3066 RCAR_GP_PIN(1, 15),
3067 };
3068 static const unsigned int msiof3_txd_c_mux[] = {
3069 MSIOF3_TXD_C_MARK,
3070 };
3071 static const unsigned int msiof3_rxd_c_pins[] = {
3072 /* RXD */
3073 RCAR_GP_PIN(1, 14),
3074 };
3075 static const unsigned int msiof3_rxd_c_mux[] = {
3076 MSIOF3_RXD_C_MARK,
3077 };
3078 static const unsigned int msiof3_clk_d_pins[] = {
3079 /* SCK */
3080 RCAR_GP_PIN(1, 22),
3081 };
3082 static const unsigned int msiof3_clk_d_mux[] = {
3083 MSIOF3_SCK_D_MARK,
3084 };
3085 static const unsigned int msiof3_sync_d_pins[] = {
3086 /* SYNC */
3087 RCAR_GP_PIN(1, 23),
3088 };
3089 static const unsigned int msiof3_sync_d_mux[] = {
3090 MSIOF3_SYNC_D_MARK,
3091 };
3092 static const unsigned int msiof3_ss1_d_pins[] = {
3093 /* SS1 */
3094 RCAR_GP_PIN(1, 26),
3095 };
3096 static const unsigned int msiof3_ss1_d_mux[] = {
3097 MSIOF3_SS1_D_MARK,
3098 };
3099 static const unsigned int msiof3_txd_d_pins[] = {
3100 /* TXD */
3101 RCAR_GP_PIN(1, 25),
3102 };
3103 static const unsigned int msiof3_txd_d_mux[] = {
3104 MSIOF3_TXD_D_MARK,
3105 };
3106 static const unsigned int msiof3_rxd_d_pins[] = {
3107 /* RXD */
3108 RCAR_GP_PIN(1, 24),
3109 };
3110 static const unsigned int msiof3_rxd_d_mux[] = {
3111 MSIOF3_RXD_D_MARK,
3112 };
3113 static const unsigned int msiof3_clk_e_pins[] = {
3114 /* SCK */
3115 RCAR_GP_PIN(2, 3),
3116 };
3117 static const unsigned int msiof3_clk_e_mux[] = {
3118 MSIOF3_SCK_E_MARK,
3119 };
3120 static const unsigned int msiof3_sync_e_pins[] = {
3121 /* SYNC */
3122 RCAR_GP_PIN(2, 2),
3123 };
3124 static const unsigned int msiof3_sync_e_mux[] = {
3125 MSIOF3_SYNC_E_MARK,
3126 };
3127 static const unsigned int msiof3_ss1_e_pins[] = {
3128 /* SS1 */
3129 RCAR_GP_PIN(2, 1),
3130 };
3131 static const unsigned int msiof3_ss1_e_mux[] = {
3132 MSIOF3_SS1_E_MARK,
3133 };
3134 static const unsigned int msiof3_ss2_e_pins[] = {
3135 /* SS2 */
3136 RCAR_GP_PIN(2, 0),
3137 };
3138 static const unsigned int msiof3_ss2_e_mux[] = {
3139 MSIOF3_SS2_E_MARK,
3140 };
3141 static const unsigned int msiof3_txd_e_pins[] = {
3142 /* TXD */
3143 RCAR_GP_PIN(2, 5),
3144 };
3145 static const unsigned int msiof3_txd_e_mux[] = {
3146 MSIOF3_TXD_E_MARK,
3147 };
3148 static const unsigned int msiof3_rxd_e_pins[] = {
3149 /* RXD */
3150 RCAR_GP_PIN(2, 4),
3151 };
3152 static const unsigned int msiof3_rxd_e_mux[] = {
3153 MSIOF3_RXD_E_MARK,
3154 };
3155
3156 /* - PWM0 --------------------------------------------------------------------*/
3157 static const unsigned int pwm0_pins[] = {
3158 /* PWM */
3159 RCAR_GP_PIN(2, 6),
3160 };
3161 static const unsigned int pwm0_mux[] = {
3162 PWM0_MARK,
3163 };
3164 /* - PWM1 --------------------------------------------------------------------*/
3165 static const unsigned int pwm1_a_pins[] = {
3166 /* PWM */
3167 RCAR_GP_PIN(2, 7),
3168 };
3169 static const unsigned int pwm1_a_mux[] = {
3170 PWM1_A_MARK,
3171 };
3172 static const unsigned int pwm1_b_pins[] = {
3173 /* PWM */
3174 RCAR_GP_PIN(1, 8),
3175 };
3176 static const unsigned int pwm1_b_mux[] = {
3177 PWM1_B_MARK,
3178 };
3179 /* - PWM2 --------------------------------------------------------------------*/
3180 static const unsigned int pwm2_a_pins[] = {
3181 /* PWM */
3182 RCAR_GP_PIN(2, 8),
3183 };
3184 static const unsigned int pwm2_a_mux[] = {
3185 PWM2_A_MARK,
3186 };
3187 static const unsigned int pwm2_b_pins[] = {
3188 /* PWM */
3189 RCAR_GP_PIN(1, 11),
3190 };
3191 static const unsigned int pwm2_b_mux[] = {
3192 PWM2_B_MARK,
3193 };
3194 /* - PWM3 --------------------------------------------------------------------*/
3195 static const unsigned int pwm3_a_pins[] = {
3196 /* PWM */
3197 RCAR_GP_PIN(1, 0),
3198 };
3199 static const unsigned int pwm3_a_mux[] = {
3200 PWM3_A_MARK,
3201 };
3202 static const unsigned int pwm3_b_pins[] = {
3203 /* PWM */
3204 RCAR_GP_PIN(2, 2),
3205 };
3206 static const unsigned int pwm3_b_mux[] = {
3207 PWM3_B_MARK,
3208 };
3209 /* - PWM4 --------------------------------------------------------------------*/
3210 static const unsigned int pwm4_a_pins[] = {
3211 /* PWM */
3212 RCAR_GP_PIN(1, 1),
3213 };
3214 static const unsigned int pwm4_a_mux[] = {
3215 PWM4_A_MARK,
3216 };
3217 static const unsigned int pwm4_b_pins[] = {
3218 /* PWM */
3219 RCAR_GP_PIN(2, 3),
3220 };
3221 static const unsigned int pwm4_b_mux[] = {
3222 PWM4_B_MARK,
3223 };
3224 /* - PWM5 --------------------------------------------------------------------*/
3225 static const unsigned int pwm5_a_pins[] = {
3226 /* PWM */
3227 RCAR_GP_PIN(1, 2),
3228 };
3229 static const unsigned int pwm5_a_mux[] = {
3230 PWM5_A_MARK,
3231 };
3232 static const unsigned int pwm5_b_pins[] = {
3233 /* PWM */
3234 RCAR_GP_PIN(2, 4),
3235 };
3236 static const unsigned int pwm5_b_mux[] = {
3237 PWM5_B_MARK,
3238 };
3239 /* - PWM6 --------------------------------------------------------------------*/
3240 static const unsigned int pwm6_a_pins[] = {
3241 /* PWM */
3242 RCAR_GP_PIN(1, 3),
3243 };
3244 static const unsigned int pwm6_a_mux[] = {
3245 PWM6_A_MARK,
3246 };
3247 static const unsigned int pwm6_b_pins[] = {
3248 /* PWM */
3249 RCAR_GP_PIN(2, 5),
3250 };
3251 static const unsigned int pwm6_b_mux[] = {
3252 PWM6_B_MARK,
3253 };
3254
3255 /* - QSPI0 ------------------------------------------------------------------ */
3256 static const unsigned int qspi0_ctrl_pins[] = {
3257 /* QSPI0_SPCLK, QSPI0_SSL */
3258 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3259 };
3260 static const unsigned int qspi0_ctrl_mux[] = {
3261 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3262 };
3263 static const unsigned int qspi0_data2_pins[] = {
3264 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3265 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3266 };
3267 static const unsigned int qspi0_data2_mux[] = {
3268 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3269 };
3270 static const unsigned int qspi0_data4_pins[] = {
3271 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3272 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3273 /* QSPI0_IO2, QSPI0_IO3 */
3274 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3275 };
3276 static const unsigned int qspi0_data4_mux[] = {
3277 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3278 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3279 };
3280 /* - QSPI1 ------------------------------------------------------------------ */
3281 static const unsigned int qspi1_ctrl_pins[] = {
3282 /* QSPI1_SPCLK, QSPI1_SSL */
3283 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3284 };
3285 static const unsigned int qspi1_ctrl_mux[] = {
3286 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3287 };
3288 static const unsigned int qspi1_data2_pins[] = {
3289 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3290 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3291 };
3292 static const unsigned int qspi1_data2_mux[] = {
3293 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3294 };
3295 static const unsigned int qspi1_data4_pins[] = {
3296 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3297 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3298 /* QSPI1_IO2, QSPI1_IO3 */
3299 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3300 };
3301 static const unsigned int qspi1_data4_mux[] = {
3302 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3303 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3304 };
3305
3306 /* - SATA --------------------------------------------------------------------*/
3307 static const unsigned int sata0_devslp_a_pins[] = {
3308 /* DEVSLP */
3309 RCAR_GP_PIN(6, 16),
3310 };
3311 static const unsigned int sata0_devslp_a_mux[] = {
3312 SATA_DEVSLP_A_MARK,
3313 };
3314 static const unsigned int sata0_devslp_b_pins[] = {
3315 /* DEVSLP */
3316 RCAR_GP_PIN(4, 6),
3317 };
3318 static const unsigned int sata0_devslp_b_mux[] = {
3319 SATA_DEVSLP_B_MARK,
3320 };
3321
3322 /* - SCIF0 ------------------------------------------------------------------ */
3323 static const unsigned int scif0_data_pins[] = {
3324 /* RX, TX */
3325 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3326 };
3327 static const unsigned int scif0_data_mux[] = {
3328 RX0_MARK, TX0_MARK,
3329 };
3330 static const unsigned int scif0_clk_pins[] = {
3331 /* SCK */
3332 RCAR_GP_PIN(5, 0),
3333 };
3334 static const unsigned int scif0_clk_mux[] = {
3335 SCK0_MARK,
3336 };
3337 static const unsigned int scif0_ctrl_pins[] = {
3338 /* RTS, CTS */
3339 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3340 };
3341 static const unsigned int scif0_ctrl_mux[] = {
3342 RTS0_N_MARK, CTS0_N_MARK,
3343 };
3344 /* - SCIF1 ------------------------------------------------------------------ */
3345 static const unsigned int scif1_data_a_pins[] = {
3346 /* RX, TX */
3347 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3348 };
3349 static const unsigned int scif1_data_a_mux[] = {
3350 RX1_A_MARK, TX1_A_MARK,
3351 };
3352 static const unsigned int scif1_clk_pins[] = {
3353 /* SCK */
3354 RCAR_GP_PIN(6, 21),
3355 };
3356 static const unsigned int scif1_clk_mux[] = {
3357 SCK1_MARK,
3358 };
3359 static const unsigned int scif1_ctrl_pins[] = {
3360 /* RTS, CTS */
3361 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3362 };
3363 static const unsigned int scif1_ctrl_mux[] = {
3364 RTS1_N_MARK, CTS1_N_MARK,
3365 };
3366
3367 static const unsigned int scif1_data_b_pins[] = {
3368 /* RX, TX */
3369 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3370 };
3371 static const unsigned int scif1_data_b_mux[] = {
3372 RX1_B_MARK, TX1_B_MARK,
3373 };
3374 /* - SCIF2 ------------------------------------------------------------------ */
3375 static const unsigned int scif2_data_a_pins[] = {
3376 /* RX, TX */
3377 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3378 };
3379 static const unsigned int scif2_data_a_mux[] = {
3380 RX2_A_MARK, TX2_A_MARK,
3381 };
3382 static const unsigned int scif2_clk_pins[] = {
3383 /* SCK */
3384 RCAR_GP_PIN(5, 9),
3385 };
3386 static const unsigned int scif2_clk_mux[] = {
3387 SCK2_MARK,
3388 };
3389 static const unsigned int scif2_data_b_pins[] = {
3390 /* RX, TX */
3391 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3392 };
3393 static const unsigned int scif2_data_b_mux[] = {
3394 RX2_B_MARK, TX2_B_MARK,
3395 };
3396 /* - SCIF3 ------------------------------------------------------------------ */
3397 static const unsigned int scif3_data_a_pins[] = {
3398 /* RX, TX */
3399 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3400 };
3401 static const unsigned int scif3_data_a_mux[] = {
3402 RX3_A_MARK, TX3_A_MARK,
3403 };
3404 static const unsigned int scif3_clk_pins[] = {
3405 /* SCK */
3406 RCAR_GP_PIN(1, 22),
3407 };
3408 static const unsigned int scif3_clk_mux[] = {
3409 SCK3_MARK,
3410 };
3411 static const unsigned int scif3_ctrl_pins[] = {
3412 /* RTS, CTS */
3413 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3414 };
3415 static const unsigned int scif3_ctrl_mux[] = {
3416 RTS3_N_MARK, CTS3_N_MARK,
3417 };
3418 static const unsigned int scif3_data_b_pins[] = {
3419 /* RX, TX */
3420 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3421 };
3422 static const unsigned int scif3_data_b_mux[] = {
3423 RX3_B_MARK, TX3_B_MARK,
3424 };
3425 /* - SCIF4 ------------------------------------------------------------------ */
3426 static const unsigned int scif4_data_a_pins[] = {
3427 /* RX, TX */
3428 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3429 };
3430 static const unsigned int scif4_data_a_mux[] = {
3431 RX4_A_MARK, TX4_A_MARK,
3432 };
3433 static const unsigned int scif4_clk_a_pins[] = {
3434 /* SCK */
3435 RCAR_GP_PIN(2, 10),
3436 };
3437 static const unsigned int scif4_clk_a_mux[] = {
3438 SCK4_A_MARK,
3439 };
3440 static const unsigned int scif4_ctrl_a_pins[] = {
3441 /* RTS, CTS */
3442 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3443 };
3444 static const unsigned int scif4_ctrl_a_mux[] = {
3445 RTS4_N_A_MARK, CTS4_N_A_MARK,
3446 };
3447 static const unsigned int scif4_data_b_pins[] = {
3448 /* RX, TX */
3449 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3450 };
3451 static const unsigned int scif4_data_b_mux[] = {
3452 RX4_B_MARK, TX4_B_MARK,
3453 };
3454 static const unsigned int scif4_clk_b_pins[] = {
3455 /* SCK */
3456 RCAR_GP_PIN(1, 5),
3457 };
3458 static const unsigned int scif4_clk_b_mux[] = {
3459 SCK4_B_MARK,
3460 };
3461 static const unsigned int scif4_ctrl_b_pins[] = {
3462 /* RTS, CTS */
3463 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3464 };
3465 static const unsigned int scif4_ctrl_b_mux[] = {
3466 RTS4_N_B_MARK, CTS4_N_B_MARK,
3467 };
3468 static const unsigned int scif4_data_c_pins[] = {
3469 /* RX, TX */
3470 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3471 };
3472 static const unsigned int scif4_data_c_mux[] = {
3473 RX4_C_MARK, TX4_C_MARK,
3474 };
3475 static const unsigned int scif4_clk_c_pins[] = {
3476 /* SCK */
3477 RCAR_GP_PIN(0, 8),
3478 };
3479 static const unsigned int scif4_clk_c_mux[] = {
3480 SCK4_C_MARK,
3481 };
3482 static const unsigned int scif4_ctrl_c_pins[] = {
3483 /* RTS, CTS */
3484 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3485 };
3486 static const unsigned int scif4_ctrl_c_mux[] = {
3487 RTS4_N_C_MARK, CTS4_N_C_MARK,
3488 };
3489 /* - SCIF5 ------------------------------------------------------------------ */
3490 static const unsigned int scif5_data_a_pins[] = {
3491 /* RX, TX */
3492 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3493 };
3494 static const unsigned int scif5_data_a_mux[] = {
3495 RX5_A_MARK, TX5_A_MARK,
3496 };
3497 static const unsigned int scif5_clk_a_pins[] = {
3498 /* SCK */
3499 RCAR_GP_PIN(6, 21),
3500 };
3501 static const unsigned int scif5_clk_a_mux[] = {
3502 SCK5_A_MARK,
3503 };
3504 static const unsigned int scif5_data_b_pins[] = {
3505 /* RX, TX */
3506 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3507 };
3508 static const unsigned int scif5_data_b_mux[] = {
3509 RX5_B_MARK, TX5_B_MARK,
3510 };
3511 static const unsigned int scif5_clk_b_pins[] = {
3512 /* SCK */
3513 RCAR_GP_PIN(5, 0),
3514 };
3515 static const unsigned int scif5_clk_b_mux[] = {
3516 SCK5_B_MARK,
3517 };
3518
3519 /* - SCIF Clock ------------------------------------------------------------- */
3520 static const unsigned int scif_clk_a_pins[] = {
3521 /* SCIF_CLK */
3522 RCAR_GP_PIN(6, 23),
3523 };
3524 static const unsigned int scif_clk_a_mux[] = {
3525 SCIF_CLK_A_MARK,
3526 };
3527 static const unsigned int scif_clk_b_pins[] = {
3528 /* SCIF_CLK */
3529 RCAR_GP_PIN(5, 9),
3530 };
3531 static const unsigned int scif_clk_b_mux[] = {
3532 SCIF_CLK_B_MARK,
3533 };
3534
3535 /* - SDHI0 ------------------------------------------------------------------ */
3536 static const unsigned int sdhi0_data1_pins[] = {
3537 /* D0 */
3538 RCAR_GP_PIN(3, 2),
3539 };
3540 static const unsigned int sdhi0_data1_mux[] = {
3541 SD0_DAT0_MARK,
3542 };
3543 static const unsigned int sdhi0_data4_pins[] = {
3544 /* D[0:3] */
3545 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3546 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3547 };
3548 static const unsigned int sdhi0_data4_mux[] = {
3549 SD0_DAT0_MARK, SD0_DAT1_MARK,
3550 SD0_DAT2_MARK, SD0_DAT3_MARK,
3551 };
3552 static const unsigned int sdhi0_ctrl_pins[] = {
3553 /* CLK, CMD */
3554 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3555 };
3556 static const unsigned int sdhi0_ctrl_mux[] = {
3557 SD0_CLK_MARK, SD0_CMD_MARK,
3558 };
3559 static const unsigned int sdhi0_cd_pins[] = {
3560 /* CD */
3561 RCAR_GP_PIN(3, 12),
3562 };
3563 static const unsigned int sdhi0_cd_mux[] = {
3564 SD0_CD_MARK,
3565 };
3566 static const unsigned int sdhi0_wp_pins[] = {
3567 /* WP */
3568 RCAR_GP_PIN(3, 13),
3569 };
3570 static const unsigned int sdhi0_wp_mux[] = {
3571 SD0_WP_MARK,
3572 };
3573 /* - SDHI1 ------------------------------------------------------------------ */
3574 static const unsigned int sdhi1_data1_pins[] = {
3575 /* D0 */
3576 RCAR_GP_PIN(3, 8),
3577 };
3578 static const unsigned int sdhi1_data1_mux[] = {
3579 SD1_DAT0_MARK,
3580 };
3581 static const unsigned int sdhi1_data4_pins[] = {
3582 /* D[0:3] */
3583 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3584 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3585 };
3586 static const unsigned int sdhi1_data4_mux[] = {
3587 SD1_DAT0_MARK, SD1_DAT1_MARK,
3588 SD1_DAT2_MARK, SD1_DAT3_MARK,
3589 };
3590 static const unsigned int sdhi1_ctrl_pins[] = {
3591 /* CLK, CMD */
3592 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3593 };
3594 static const unsigned int sdhi1_ctrl_mux[] = {
3595 SD1_CLK_MARK, SD1_CMD_MARK,
3596 };
3597 static const unsigned int sdhi1_cd_pins[] = {
3598 /* CD */
3599 RCAR_GP_PIN(3, 14),
3600 };
3601 static const unsigned int sdhi1_cd_mux[] = {
3602 SD1_CD_MARK,
3603 };
3604 static const unsigned int sdhi1_wp_pins[] = {
3605 /* WP */
3606 RCAR_GP_PIN(3, 15),
3607 };
3608 static const unsigned int sdhi1_wp_mux[] = {
3609 SD1_WP_MARK,
3610 };
3611 /* - SDHI2 ------------------------------------------------------------------ */
3612 static const unsigned int sdhi2_data1_pins[] = {
3613 /* D0 */
3614 RCAR_GP_PIN(4, 2),
3615 };
3616 static const unsigned int sdhi2_data1_mux[] = {
3617 SD2_DAT0_MARK,
3618 };
3619 static const unsigned int sdhi2_data4_pins[] = {
3620 /* D[0:3] */
3621 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3622 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3623 };
3624 static const unsigned int sdhi2_data4_mux[] = {
3625 SD2_DAT0_MARK, SD2_DAT1_MARK,
3626 SD2_DAT2_MARK, SD2_DAT3_MARK,
3627 };
3628 static const unsigned int sdhi2_data8_pins[] = {
3629 /* D[0:7] */
3630 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3631 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3632 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3633 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3634 };
3635 static const unsigned int sdhi2_data8_mux[] = {
3636 SD2_DAT0_MARK, SD2_DAT1_MARK,
3637 SD2_DAT2_MARK, SD2_DAT3_MARK,
3638 SD2_DAT4_MARK, SD2_DAT5_MARK,
3639 SD2_DAT6_MARK, SD2_DAT7_MARK,
3640 };
3641 static const unsigned int sdhi2_ctrl_pins[] = {
3642 /* CLK, CMD */
3643 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3644 };
3645 static const unsigned int sdhi2_ctrl_mux[] = {
3646 SD2_CLK_MARK, SD2_CMD_MARK,
3647 };
3648 static const unsigned int sdhi2_cd_a_pins[] = {
3649 /* CD */
3650 RCAR_GP_PIN(4, 13),
3651 };
3652 static const unsigned int sdhi2_cd_a_mux[] = {
3653 SD2_CD_A_MARK,
3654 };
3655 static const unsigned int sdhi2_cd_b_pins[] = {
3656 /* CD */
3657 RCAR_GP_PIN(5, 10),
3658 };
3659 static const unsigned int sdhi2_cd_b_mux[] = {
3660 SD2_CD_B_MARK,
3661 };
3662 static const unsigned int sdhi2_wp_a_pins[] = {
3663 /* WP */
3664 RCAR_GP_PIN(4, 14),
3665 };
3666 static const unsigned int sdhi2_wp_a_mux[] = {
3667 SD2_WP_A_MARK,
3668 };
3669 static const unsigned int sdhi2_wp_b_pins[] = {
3670 /* WP */
3671 RCAR_GP_PIN(5, 11),
3672 };
3673 static const unsigned int sdhi2_wp_b_mux[] = {
3674 SD2_WP_B_MARK,
3675 };
3676 static const unsigned int sdhi2_ds_pins[] = {
3677 /* DS */
3678 RCAR_GP_PIN(4, 6),
3679 };
3680 static const unsigned int sdhi2_ds_mux[] = {
3681 SD2_DS_MARK,
3682 };
3683 /* - SDHI3 ------------------------------------------------------------------ */
3684 static const unsigned int sdhi3_data1_pins[] = {
3685 /* D0 */
3686 RCAR_GP_PIN(4, 9),
3687 };
3688 static const unsigned int sdhi3_data1_mux[] = {
3689 SD3_DAT0_MARK,
3690 };
3691 static const unsigned int sdhi3_data4_pins[] = {
3692 /* D[0:3] */
3693 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3694 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3695 };
3696 static const unsigned int sdhi3_data4_mux[] = {
3697 SD3_DAT0_MARK, SD3_DAT1_MARK,
3698 SD3_DAT2_MARK, SD3_DAT3_MARK,
3699 };
3700 static const unsigned int sdhi3_data8_pins[] = {
3701 /* D[0:7] */
3702 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3703 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3704 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3705 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3706 };
3707 static const unsigned int sdhi3_data8_mux[] = {
3708 SD3_DAT0_MARK, SD3_DAT1_MARK,
3709 SD3_DAT2_MARK, SD3_DAT3_MARK,
3710 SD3_DAT4_MARK, SD3_DAT5_MARK,
3711 SD3_DAT6_MARK, SD3_DAT7_MARK,
3712 };
3713 static const unsigned int sdhi3_ctrl_pins[] = {
3714 /* CLK, CMD */
3715 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3716 };
3717 static const unsigned int sdhi3_ctrl_mux[] = {
3718 SD3_CLK_MARK, SD3_CMD_MARK,
3719 };
3720 static const unsigned int sdhi3_cd_pins[] = {
3721 /* CD */
3722 RCAR_GP_PIN(4, 15),
3723 };
3724 static const unsigned int sdhi3_cd_mux[] = {
3725 SD3_CD_MARK,
3726 };
3727 static const unsigned int sdhi3_wp_pins[] = {
3728 /* WP */
3729 RCAR_GP_PIN(4, 16),
3730 };
3731 static const unsigned int sdhi3_wp_mux[] = {
3732 SD3_WP_MARK,
3733 };
3734 static const unsigned int sdhi3_ds_pins[] = {
3735 /* DS */
3736 RCAR_GP_PIN(4, 17),
3737 };
3738 static const unsigned int sdhi3_ds_mux[] = {
3739 SD3_DS_MARK,
3740 };
3741
3742 /* - SSI -------------------------------------------------------------------- */
3743 static const unsigned int ssi0_data_pins[] = {
3744 /* SDATA */
3745 RCAR_GP_PIN(6, 2),
3746 };
3747 static const unsigned int ssi0_data_mux[] = {
3748 SSI_SDATA0_MARK,
3749 };
3750 static const unsigned int ssi01239_ctrl_pins[] = {
3751 /* SCK, WS */
3752 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3753 };
3754 static const unsigned int ssi01239_ctrl_mux[] = {
3755 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3756 };
3757 static const unsigned int ssi1_data_a_pins[] = {
3758 /* SDATA */
3759 RCAR_GP_PIN(6, 3),
3760 };
3761 static const unsigned int ssi1_data_a_mux[] = {
3762 SSI_SDATA1_A_MARK,
3763 };
3764 static const unsigned int ssi1_data_b_pins[] = {
3765 /* SDATA */
3766 RCAR_GP_PIN(5, 12),
3767 };
3768 static const unsigned int ssi1_data_b_mux[] = {
3769 SSI_SDATA1_B_MARK,
3770 };
3771 static const unsigned int ssi1_ctrl_a_pins[] = {
3772 /* SCK, WS */
3773 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3774 };
3775 static const unsigned int ssi1_ctrl_a_mux[] = {
3776 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3777 };
3778 static const unsigned int ssi1_ctrl_b_pins[] = {
3779 /* SCK, WS */
3780 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3781 };
3782 static const unsigned int ssi1_ctrl_b_mux[] = {
3783 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3784 };
3785 static const unsigned int ssi2_data_a_pins[] = {
3786 /* SDATA */
3787 RCAR_GP_PIN(6, 4),
3788 };
3789 static const unsigned int ssi2_data_a_mux[] = {
3790 SSI_SDATA2_A_MARK,
3791 };
3792 static const unsigned int ssi2_data_b_pins[] = {
3793 /* SDATA */
3794 RCAR_GP_PIN(5, 13),
3795 };
3796 static const unsigned int ssi2_data_b_mux[] = {
3797 SSI_SDATA2_B_MARK,
3798 };
3799 static const unsigned int ssi2_ctrl_a_pins[] = {
3800 /* SCK, WS */
3801 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3802 };
3803 static const unsigned int ssi2_ctrl_a_mux[] = {
3804 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3805 };
3806 static const unsigned int ssi2_ctrl_b_pins[] = {
3807 /* SCK, WS */
3808 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3809 };
3810 static const unsigned int ssi2_ctrl_b_mux[] = {
3811 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3812 };
3813 static const unsigned int ssi3_data_pins[] = {
3814 /* SDATA */
3815 RCAR_GP_PIN(6, 7),
3816 };
3817 static const unsigned int ssi3_data_mux[] = {
3818 SSI_SDATA3_MARK,
3819 };
3820 static const unsigned int ssi349_ctrl_pins[] = {
3821 /* SCK, WS */
3822 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3823 };
3824 static const unsigned int ssi349_ctrl_mux[] = {
3825 SSI_SCK349_MARK, SSI_WS349_MARK,
3826 };
3827 static const unsigned int ssi4_data_pins[] = {
3828 /* SDATA */
3829 RCAR_GP_PIN(6, 10),
3830 };
3831 static const unsigned int ssi4_data_mux[] = {
3832 SSI_SDATA4_MARK,
3833 };
3834 static const unsigned int ssi4_ctrl_pins[] = {
3835 /* SCK, WS */
3836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3837 };
3838 static const unsigned int ssi4_ctrl_mux[] = {
3839 SSI_SCK4_MARK, SSI_WS4_MARK,
3840 };
3841 static const unsigned int ssi5_data_pins[] = {
3842 /* SDATA */
3843 RCAR_GP_PIN(6, 13),
3844 };
3845 static const unsigned int ssi5_data_mux[] = {
3846 SSI_SDATA5_MARK,
3847 };
3848 static const unsigned int ssi5_ctrl_pins[] = {
3849 /* SCK, WS */
3850 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3851 };
3852 static const unsigned int ssi5_ctrl_mux[] = {
3853 SSI_SCK5_MARK, SSI_WS5_MARK,
3854 };
3855 static const unsigned int ssi6_data_pins[] = {
3856 /* SDATA */
3857 RCAR_GP_PIN(6, 16),
3858 };
3859 static const unsigned int ssi6_data_mux[] = {
3860 SSI_SDATA6_MARK,
3861 };
3862 static const unsigned int ssi6_ctrl_pins[] = {
3863 /* SCK, WS */
3864 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3865 };
3866 static const unsigned int ssi6_ctrl_mux[] = {
3867 SSI_SCK6_MARK, SSI_WS6_MARK,
3868 };
3869 static const unsigned int ssi7_data_pins[] = {
3870 /* SDATA */
3871 RCAR_GP_PIN(6, 19),
3872 };
3873 static const unsigned int ssi7_data_mux[] = {
3874 SSI_SDATA7_MARK,
3875 };
3876 static const unsigned int ssi78_ctrl_pins[] = {
3877 /* SCK, WS */
3878 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3879 };
3880 static const unsigned int ssi78_ctrl_mux[] = {
3881 SSI_SCK78_MARK, SSI_WS78_MARK,
3882 };
3883 static const unsigned int ssi8_data_pins[] = {
3884 /* SDATA */
3885 RCAR_GP_PIN(6, 20),
3886 };
3887 static const unsigned int ssi8_data_mux[] = {
3888 SSI_SDATA8_MARK,
3889 };
3890 static const unsigned int ssi9_data_a_pins[] = {
3891 /* SDATA */
3892 RCAR_GP_PIN(6, 21),
3893 };
3894 static const unsigned int ssi9_data_a_mux[] = {
3895 SSI_SDATA9_A_MARK,
3896 };
3897 static const unsigned int ssi9_data_b_pins[] = {
3898 /* SDATA */
3899 RCAR_GP_PIN(5, 14),
3900 };
3901 static const unsigned int ssi9_data_b_mux[] = {
3902 SSI_SDATA9_B_MARK,
3903 };
3904 static const unsigned int ssi9_ctrl_a_pins[] = {
3905 /* SCK, WS */
3906 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3907 };
3908 static const unsigned int ssi9_ctrl_a_mux[] = {
3909 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3910 };
3911 static const unsigned int ssi9_ctrl_b_pins[] = {
3912 /* SCK, WS */
3913 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3914 };
3915 static const unsigned int ssi9_ctrl_b_mux[] = {
3916 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3917 };
3918
3919 /* - TMU -------------------------------------------------------------------- */
3920 static const unsigned int tmu_tclk1_a_pins[] = {
3921 /* TCLK */
3922 RCAR_GP_PIN(6, 23),
3923 };
3924 static const unsigned int tmu_tclk1_a_mux[] = {
3925 TCLK1_A_MARK,
3926 };
3927 static const unsigned int tmu_tclk1_b_pins[] = {
3928 /* TCLK */
3929 RCAR_GP_PIN(5, 19),
3930 };
3931 static const unsigned int tmu_tclk1_b_mux[] = {
3932 TCLK1_B_MARK,
3933 };
3934 static const unsigned int tmu_tclk2_a_pins[] = {
3935 /* TCLK */
3936 RCAR_GP_PIN(6, 19),
3937 };
3938 static const unsigned int tmu_tclk2_a_mux[] = {
3939 TCLK2_A_MARK,
3940 };
3941 static const unsigned int tmu_tclk2_b_pins[] = {
3942 /* TCLK */
3943 RCAR_GP_PIN(6, 28),
3944 };
3945 static const unsigned int tmu_tclk2_b_mux[] = {
3946 TCLK2_B_MARK,
3947 };
3948
3949 /* - TPU ------------------------------------------------------------------- */
3950 static const unsigned int tpu_to0_pins[] = {
3951 /* TPU0TO0 */
3952 RCAR_GP_PIN(6, 28),
3953 };
3954 static const unsigned int tpu_to0_mux[] = {
3955 TPU0TO0_MARK,
3956 };
3957 static const unsigned int tpu_to1_pins[] = {
3958 /* TPU0TO1 */
3959 RCAR_GP_PIN(6, 29),
3960 };
3961 static const unsigned int tpu_to1_mux[] = {
3962 TPU0TO1_MARK,
3963 };
3964 static const unsigned int tpu_to2_pins[] = {
3965 /* TPU0TO2 */
3966 RCAR_GP_PIN(6, 30),
3967 };
3968 static const unsigned int tpu_to2_mux[] = {
3969 TPU0TO2_MARK,
3970 };
3971 static const unsigned int tpu_to3_pins[] = {
3972 /* TPU0TO3 */
3973 RCAR_GP_PIN(6, 31),
3974 };
3975 static const unsigned int tpu_to3_mux[] = {
3976 TPU0TO3_MARK,
3977 };
3978
3979 /* - USB0 ------------------------------------------------------------------- */
3980 static const unsigned int usb0_pins[] = {
3981 /* PWEN, OVC */
3982 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3983 };
3984 static const unsigned int usb0_mux[] = {
3985 USB0_PWEN_MARK, USB0_OVC_MARK,
3986 };
3987 /* - USB1 ------------------------------------------------------------------- */
3988 static const unsigned int usb1_pins[] = {
3989 /* PWEN, OVC */
3990 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3991 };
3992 static const unsigned int usb1_mux[] = {
3993 USB1_PWEN_MARK, USB1_OVC_MARK,
3994 };
3995 /* - USB2 ------------------------------------------------------------------- */
3996 static const unsigned int usb2_pins[] = {
3997 /* PWEN, OVC */
3998 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3999 };
4000 static const unsigned int usb2_mux[] = {
4001 USB2_PWEN_MARK, USB2_OVC_MARK,
4002 };
4003 /* - USB2_CH3 --------------------------------------------------------------- */
4004 static const unsigned int usb2_ch3_pins[] = {
4005 /* PWEN, OVC */
4006 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4007 };
4008 static const unsigned int usb2_ch3_mux[] = {
4009 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
4010 };
4011
4012 /* - USB30 ------------------------------------------------------------------ */
4013 static const unsigned int usb30_pins[] = {
4014 /* PWEN, OVC */
4015 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4016 };
4017 static const unsigned int usb30_mux[] = {
4018 USB30_PWEN_MARK, USB30_OVC_MARK,
4019 };
4020
4021 /* - VIN4 ------------------------------------------------------------------- */
4022 static const unsigned int vin4_data18_a_pins[] = {
4023 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4024 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4025 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4026 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4027 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4028 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4029 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4030 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4031 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4032 };
4033 static const unsigned int vin4_data18_a_mux[] = {
4034 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4035 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4036 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4037 VI4_DATA10_MARK, VI4_DATA11_MARK,
4038 VI4_DATA12_MARK, VI4_DATA13_MARK,
4039 VI4_DATA14_MARK, VI4_DATA15_MARK,
4040 VI4_DATA18_MARK, VI4_DATA19_MARK,
4041 VI4_DATA20_MARK, VI4_DATA21_MARK,
4042 VI4_DATA22_MARK, VI4_DATA23_MARK,
4043 };
4044 static const unsigned int vin4_data18_b_pins[] = {
4045 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4046 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4047 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4048 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4049 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4050 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4051 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4052 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4053 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4054 };
4055 static const unsigned int vin4_data18_b_mux[] = {
4056 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4057 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4058 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4059 VI4_DATA10_MARK, VI4_DATA11_MARK,
4060 VI4_DATA12_MARK, VI4_DATA13_MARK,
4061 VI4_DATA14_MARK, VI4_DATA15_MARK,
4062 VI4_DATA18_MARK, VI4_DATA19_MARK,
4063 VI4_DATA20_MARK, VI4_DATA21_MARK,
4064 VI4_DATA22_MARK, VI4_DATA23_MARK,
4065 };
4066 static const union vin_data vin4_data_a_pins = {
4067 .data24 = {
4068 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4069 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4070 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4071 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4072 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4073 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4074 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4075 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4076 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4077 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4078 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4079 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4080 },
4081 };
4082 static const union vin_data vin4_data_a_mux = {
4083 .data24 = {
4084 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4085 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4086 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4087 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4088 VI4_DATA8_MARK, VI4_DATA9_MARK,
4089 VI4_DATA10_MARK, VI4_DATA11_MARK,
4090 VI4_DATA12_MARK, VI4_DATA13_MARK,
4091 VI4_DATA14_MARK, VI4_DATA15_MARK,
4092 VI4_DATA16_MARK, VI4_DATA17_MARK,
4093 VI4_DATA18_MARK, VI4_DATA19_MARK,
4094 VI4_DATA20_MARK, VI4_DATA21_MARK,
4095 VI4_DATA22_MARK, VI4_DATA23_MARK,
4096 },
4097 };
4098 static const union vin_data vin4_data_b_pins = {
4099 .data24 = {
4100 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4101 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4102 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4103 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4104 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4105 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4106 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4107 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4108 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4109 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4110 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4111 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4112 },
4113 };
4114 static const union vin_data vin4_data_b_mux = {
4115 .data24 = {
4116 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4117 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4118 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4119 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4120 VI4_DATA8_MARK, VI4_DATA9_MARK,
4121 VI4_DATA10_MARK, VI4_DATA11_MARK,
4122 VI4_DATA12_MARK, VI4_DATA13_MARK,
4123 VI4_DATA14_MARK, VI4_DATA15_MARK,
4124 VI4_DATA16_MARK, VI4_DATA17_MARK,
4125 VI4_DATA18_MARK, VI4_DATA19_MARK,
4126 VI4_DATA20_MARK, VI4_DATA21_MARK,
4127 VI4_DATA22_MARK, VI4_DATA23_MARK,
4128 },
4129 };
4130 static const unsigned int vin4_sync_pins[] = {
4131 /* HSYNC#, VSYNC# */
4132 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4133 };
4134 static const unsigned int vin4_sync_mux[] = {
4135 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4136 };
4137 static const unsigned int vin4_field_pins[] = {
4138 /* FIELD */
4139 RCAR_GP_PIN(1, 16),
4140 };
4141 static const unsigned int vin4_field_mux[] = {
4142 VI4_FIELD_MARK,
4143 };
4144 static const unsigned int vin4_clkenb_pins[] = {
4145 /* CLKENB */
4146 RCAR_GP_PIN(1, 19),
4147 };
4148 static const unsigned int vin4_clkenb_mux[] = {
4149 VI4_CLKENB_MARK,
4150 };
4151 static const unsigned int vin4_clk_pins[] = {
4152 /* CLK */
4153 RCAR_GP_PIN(1, 27),
4154 };
4155 static const unsigned int vin4_clk_mux[] = {
4156 VI4_CLK_MARK,
4157 };
4158
4159 /* - VIN5 ------------------------------------------------------------------- */
4160 static const union vin_data16 vin5_data_pins = {
4161 .data16 = {
4162 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4163 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4164 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4165 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4166 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4167 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4168 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4169 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4170 },
4171 };
4172 static const union vin_data16 vin5_data_mux = {
4173 .data16 = {
4174 VI5_DATA0_MARK, VI5_DATA1_MARK,
4175 VI5_DATA2_MARK, VI5_DATA3_MARK,
4176 VI5_DATA4_MARK, VI5_DATA5_MARK,
4177 VI5_DATA6_MARK, VI5_DATA7_MARK,
4178 VI5_DATA8_MARK, VI5_DATA9_MARK,
4179 VI5_DATA10_MARK, VI5_DATA11_MARK,
4180 VI5_DATA12_MARK, VI5_DATA13_MARK,
4181 VI5_DATA14_MARK, VI5_DATA15_MARK,
4182 },
4183 };
4184 static const unsigned int vin5_sync_pins[] = {
4185 /* HSYNC#, VSYNC# */
4186 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4187 };
4188 static const unsigned int vin5_sync_mux[] = {
4189 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4190 };
4191 static const unsigned int vin5_field_pins[] = {
4192 RCAR_GP_PIN(1, 11),
4193 };
4194 static const unsigned int vin5_field_mux[] = {
4195 /* FIELD */
4196 VI5_FIELD_MARK,
4197 };
4198 static const unsigned int vin5_clkenb_pins[] = {
4199 RCAR_GP_PIN(1, 20),
4200 };
4201 static const unsigned int vin5_clkenb_mux[] = {
4202 /* CLKENB */
4203 VI5_CLKENB_MARK,
4204 };
4205 static const unsigned int vin5_clk_pins[] = {
4206 RCAR_GP_PIN(1, 21),
4207 };
4208 static const unsigned int vin5_clk_mux[] = {
4209 /* CLK */
4210 VI5_CLK_MARK,
4211 };
4212
4213 static const struct {
4214 struct sh_pfc_pin_group common[326];
4215 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4216 struct sh_pfc_pin_group automotive[30];
4217 #endif
4218 } pinmux_groups = {
4219 .common = {
4220 SH_PFC_PIN_GROUP(audio_clk_a_a),
4221 SH_PFC_PIN_GROUP(audio_clk_a_b),
4222 SH_PFC_PIN_GROUP(audio_clk_a_c),
4223 SH_PFC_PIN_GROUP(audio_clk_b_a),
4224 SH_PFC_PIN_GROUP(audio_clk_b_b),
4225 SH_PFC_PIN_GROUP(audio_clk_c_a),
4226 SH_PFC_PIN_GROUP(audio_clk_c_b),
4227 SH_PFC_PIN_GROUP(audio_clkout_a),
4228 SH_PFC_PIN_GROUP(audio_clkout_b),
4229 SH_PFC_PIN_GROUP(audio_clkout_c),
4230 SH_PFC_PIN_GROUP(audio_clkout_d),
4231 SH_PFC_PIN_GROUP(audio_clkout1_a),
4232 SH_PFC_PIN_GROUP(audio_clkout1_b),
4233 SH_PFC_PIN_GROUP(audio_clkout2_a),
4234 SH_PFC_PIN_GROUP(audio_clkout2_b),
4235 SH_PFC_PIN_GROUP(audio_clkout3_a),
4236 SH_PFC_PIN_GROUP(audio_clkout3_b),
4237 SH_PFC_PIN_GROUP(avb_link),
4238 SH_PFC_PIN_GROUP(avb_magic),
4239 SH_PFC_PIN_GROUP(avb_phy_int),
4240 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4241 SH_PFC_PIN_GROUP(avb_mdio),
4242 SH_PFC_PIN_GROUP(avb_mii),
4243 SH_PFC_PIN_GROUP(avb_avtp_pps),
4244 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4245 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4246 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4247 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4248 SH_PFC_PIN_GROUP(can0_data_a),
4249 SH_PFC_PIN_GROUP(can0_data_b),
4250 SH_PFC_PIN_GROUP(can1_data),
4251 SH_PFC_PIN_GROUP(can_clk),
4252 SH_PFC_PIN_GROUP(canfd0_data_a),
4253 SH_PFC_PIN_GROUP(canfd0_data_b),
4254 SH_PFC_PIN_GROUP(canfd1_data),
4255 SH_PFC_PIN_GROUP(du_rgb666),
4256 SH_PFC_PIN_GROUP(du_rgb888),
4257 SH_PFC_PIN_GROUP(du_clk_out_0),
4258 SH_PFC_PIN_GROUP(du_clk_out_1),
4259 SH_PFC_PIN_GROUP(du_sync),
4260 SH_PFC_PIN_GROUP(du_oddf),
4261 SH_PFC_PIN_GROUP(du_cde),
4262 SH_PFC_PIN_GROUP(du_disp),
4263 SH_PFC_PIN_GROUP(hscif0_data),
4264 SH_PFC_PIN_GROUP(hscif0_clk),
4265 SH_PFC_PIN_GROUP(hscif0_ctrl),
4266 SH_PFC_PIN_GROUP(hscif1_data_a),
4267 SH_PFC_PIN_GROUP(hscif1_clk_a),
4268 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4269 SH_PFC_PIN_GROUP(hscif1_data_b),
4270 SH_PFC_PIN_GROUP(hscif1_clk_b),
4271 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4272 SH_PFC_PIN_GROUP(hscif2_data_a),
4273 SH_PFC_PIN_GROUP(hscif2_clk_a),
4274 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4275 SH_PFC_PIN_GROUP(hscif2_data_b),
4276 SH_PFC_PIN_GROUP(hscif2_clk_b),
4277 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4278 SH_PFC_PIN_GROUP(hscif2_data_c),
4279 SH_PFC_PIN_GROUP(hscif2_clk_c),
4280 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4281 SH_PFC_PIN_GROUP(hscif3_data_a),
4282 SH_PFC_PIN_GROUP(hscif3_clk),
4283 SH_PFC_PIN_GROUP(hscif3_ctrl),
4284 SH_PFC_PIN_GROUP(hscif3_data_b),
4285 SH_PFC_PIN_GROUP(hscif3_data_c),
4286 SH_PFC_PIN_GROUP(hscif3_data_d),
4287 SH_PFC_PIN_GROUP(hscif4_data_a),
4288 SH_PFC_PIN_GROUP(hscif4_clk),
4289 SH_PFC_PIN_GROUP(hscif4_ctrl),
4290 SH_PFC_PIN_GROUP(hscif4_data_b),
4291 SH_PFC_PIN_GROUP(i2c0),
4292 SH_PFC_PIN_GROUP(i2c1_a),
4293 SH_PFC_PIN_GROUP(i2c1_b),
4294 SH_PFC_PIN_GROUP(i2c2_a),
4295 SH_PFC_PIN_GROUP(i2c2_b),
4296 SH_PFC_PIN_GROUP(i2c3),
4297 SH_PFC_PIN_GROUP(i2c5),
4298 SH_PFC_PIN_GROUP(i2c6_a),
4299 SH_PFC_PIN_GROUP(i2c6_b),
4300 SH_PFC_PIN_GROUP(i2c6_c),
4301 SH_PFC_PIN_GROUP(intc_ex_irq0),
4302 SH_PFC_PIN_GROUP(intc_ex_irq1),
4303 SH_PFC_PIN_GROUP(intc_ex_irq2),
4304 SH_PFC_PIN_GROUP(intc_ex_irq3),
4305 SH_PFC_PIN_GROUP(intc_ex_irq4),
4306 SH_PFC_PIN_GROUP(intc_ex_irq5),
4307 SH_PFC_PIN_GROUP(msiof0_clk),
4308 SH_PFC_PIN_GROUP(msiof0_sync),
4309 SH_PFC_PIN_GROUP(msiof0_ss1),
4310 SH_PFC_PIN_GROUP(msiof0_ss2),
4311 SH_PFC_PIN_GROUP(msiof0_txd),
4312 SH_PFC_PIN_GROUP(msiof0_rxd),
4313 SH_PFC_PIN_GROUP(msiof1_clk_a),
4314 SH_PFC_PIN_GROUP(msiof1_sync_a),
4315 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4316 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4317 SH_PFC_PIN_GROUP(msiof1_txd_a),
4318 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4319 SH_PFC_PIN_GROUP(msiof1_clk_b),
4320 SH_PFC_PIN_GROUP(msiof1_sync_b),
4321 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4322 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4323 SH_PFC_PIN_GROUP(msiof1_txd_b),
4324 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4325 SH_PFC_PIN_GROUP(msiof1_clk_c),
4326 SH_PFC_PIN_GROUP(msiof1_sync_c),
4327 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4328 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4329 SH_PFC_PIN_GROUP(msiof1_txd_c),
4330 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4331 SH_PFC_PIN_GROUP(msiof1_clk_d),
4332 SH_PFC_PIN_GROUP(msiof1_sync_d),
4333 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4334 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4335 SH_PFC_PIN_GROUP(msiof1_txd_d),
4336 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4337 SH_PFC_PIN_GROUP(msiof1_clk_e),
4338 SH_PFC_PIN_GROUP(msiof1_sync_e),
4339 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4340 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4341 SH_PFC_PIN_GROUP(msiof1_txd_e),
4342 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4343 SH_PFC_PIN_GROUP(msiof1_clk_f),
4344 SH_PFC_PIN_GROUP(msiof1_sync_f),
4345 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4346 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4347 SH_PFC_PIN_GROUP(msiof1_txd_f),
4348 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4349 SH_PFC_PIN_GROUP(msiof1_clk_g),
4350 SH_PFC_PIN_GROUP(msiof1_sync_g),
4351 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4352 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4353 SH_PFC_PIN_GROUP(msiof1_txd_g),
4354 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4355 SH_PFC_PIN_GROUP(msiof2_clk_a),
4356 SH_PFC_PIN_GROUP(msiof2_sync_a),
4357 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4358 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4359 SH_PFC_PIN_GROUP(msiof2_txd_a),
4360 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4361 SH_PFC_PIN_GROUP(msiof2_clk_b),
4362 SH_PFC_PIN_GROUP(msiof2_sync_b),
4363 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4364 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4365 SH_PFC_PIN_GROUP(msiof2_txd_b),
4366 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4367 SH_PFC_PIN_GROUP(msiof2_clk_c),
4368 SH_PFC_PIN_GROUP(msiof2_sync_c),
4369 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4370 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4371 SH_PFC_PIN_GROUP(msiof2_txd_c),
4372 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4373 SH_PFC_PIN_GROUP(msiof2_clk_d),
4374 SH_PFC_PIN_GROUP(msiof2_sync_d),
4375 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4376 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4377 SH_PFC_PIN_GROUP(msiof2_txd_d),
4378 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4379 SH_PFC_PIN_GROUP(msiof3_clk_a),
4380 SH_PFC_PIN_GROUP(msiof3_sync_a),
4381 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4382 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4383 SH_PFC_PIN_GROUP(msiof3_txd_a),
4384 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4385 SH_PFC_PIN_GROUP(msiof3_clk_b),
4386 SH_PFC_PIN_GROUP(msiof3_sync_b),
4387 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4388 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4389 SH_PFC_PIN_GROUP(msiof3_txd_b),
4390 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4391 SH_PFC_PIN_GROUP(msiof3_clk_c),
4392 SH_PFC_PIN_GROUP(msiof3_sync_c),
4393 SH_PFC_PIN_GROUP(msiof3_txd_c),
4394 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4395 SH_PFC_PIN_GROUP(msiof3_clk_d),
4396 SH_PFC_PIN_GROUP(msiof3_sync_d),
4397 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4398 SH_PFC_PIN_GROUP(msiof3_txd_d),
4399 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4400 SH_PFC_PIN_GROUP(msiof3_clk_e),
4401 SH_PFC_PIN_GROUP(msiof3_sync_e),
4402 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4403 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4404 SH_PFC_PIN_GROUP(msiof3_txd_e),
4405 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4406 SH_PFC_PIN_GROUP(pwm0),
4407 SH_PFC_PIN_GROUP(pwm1_a),
4408 SH_PFC_PIN_GROUP(pwm1_b),
4409 SH_PFC_PIN_GROUP(pwm2_a),
4410 SH_PFC_PIN_GROUP(pwm2_b),
4411 SH_PFC_PIN_GROUP(pwm3_a),
4412 SH_PFC_PIN_GROUP(pwm3_b),
4413 SH_PFC_PIN_GROUP(pwm4_a),
4414 SH_PFC_PIN_GROUP(pwm4_b),
4415 SH_PFC_PIN_GROUP(pwm5_a),
4416 SH_PFC_PIN_GROUP(pwm5_b),
4417 SH_PFC_PIN_GROUP(pwm6_a),
4418 SH_PFC_PIN_GROUP(pwm6_b),
4419 SH_PFC_PIN_GROUP(qspi0_ctrl),
4420 SH_PFC_PIN_GROUP(qspi0_data2),
4421 SH_PFC_PIN_GROUP(qspi0_data4),
4422 SH_PFC_PIN_GROUP(qspi1_ctrl),
4423 SH_PFC_PIN_GROUP(qspi1_data2),
4424 SH_PFC_PIN_GROUP(qspi1_data4),
4425 SH_PFC_PIN_GROUP(sata0_devslp_a),
4426 SH_PFC_PIN_GROUP(sata0_devslp_b),
4427 SH_PFC_PIN_GROUP(scif0_data),
4428 SH_PFC_PIN_GROUP(scif0_clk),
4429 SH_PFC_PIN_GROUP(scif0_ctrl),
4430 SH_PFC_PIN_GROUP(scif1_data_a),
4431 SH_PFC_PIN_GROUP(scif1_clk),
4432 SH_PFC_PIN_GROUP(scif1_ctrl),
4433 SH_PFC_PIN_GROUP(scif1_data_b),
4434 SH_PFC_PIN_GROUP(scif2_data_a),
4435 SH_PFC_PIN_GROUP(scif2_clk),
4436 SH_PFC_PIN_GROUP(scif2_data_b),
4437 SH_PFC_PIN_GROUP(scif3_data_a),
4438 SH_PFC_PIN_GROUP(scif3_clk),
4439 SH_PFC_PIN_GROUP(scif3_ctrl),
4440 SH_PFC_PIN_GROUP(scif3_data_b),
4441 SH_PFC_PIN_GROUP(scif4_data_a),
4442 SH_PFC_PIN_GROUP(scif4_clk_a),
4443 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4444 SH_PFC_PIN_GROUP(scif4_data_b),
4445 SH_PFC_PIN_GROUP(scif4_clk_b),
4446 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4447 SH_PFC_PIN_GROUP(scif4_data_c),
4448 SH_PFC_PIN_GROUP(scif4_clk_c),
4449 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4450 SH_PFC_PIN_GROUP(scif5_data_a),
4451 SH_PFC_PIN_GROUP(scif5_clk_a),
4452 SH_PFC_PIN_GROUP(scif5_data_b),
4453 SH_PFC_PIN_GROUP(scif5_clk_b),
4454 SH_PFC_PIN_GROUP(scif_clk_a),
4455 SH_PFC_PIN_GROUP(scif_clk_b),
4456 SH_PFC_PIN_GROUP(sdhi0_data1),
4457 SH_PFC_PIN_GROUP(sdhi0_data4),
4458 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4459 SH_PFC_PIN_GROUP(sdhi0_cd),
4460 SH_PFC_PIN_GROUP(sdhi0_wp),
4461 SH_PFC_PIN_GROUP(sdhi1_data1),
4462 SH_PFC_PIN_GROUP(sdhi1_data4),
4463 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4464 SH_PFC_PIN_GROUP(sdhi1_cd),
4465 SH_PFC_PIN_GROUP(sdhi1_wp),
4466 SH_PFC_PIN_GROUP(sdhi2_data1),
4467 SH_PFC_PIN_GROUP(sdhi2_data4),
4468 SH_PFC_PIN_GROUP(sdhi2_data8),
4469 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4470 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4471 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4472 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4473 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4474 SH_PFC_PIN_GROUP(sdhi2_ds),
4475 SH_PFC_PIN_GROUP(sdhi3_data1),
4476 SH_PFC_PIN_GROUP(sdhi3_data4),
4477 SH_PFC_PIN_GROUP(sdhi3_data8),
4478 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4479 SH_PFC_PIN_GROUP(sdhi3_cd),
4480 SH_PFC_PIN_GROUP(sdhi3_wp),
4481 SH_PFC_PIN_GROUP(sdhi3_ds),
4482 SH_PFC_PIN_GROUP(ssi0_data),
4483 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4484 SH_PFC_PIN_GROUP(ssi1_data_a),
4485 SH_PFC_PIN_GROUP(ssi1_data_b),
4486 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4487 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4488 SH_PFC_PIN_GROUP(ssi2_data_a),
4489 SH_PFC_PIN_GROUP(ssi2_data_b),
4490 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4491 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4492 SH_PFC_PIN_GROUP(ssi3_data),
4493 SH_PFC_PIN_GROUP(ssi349_ctrl),
4494 SH_PFC_PIN_GROUP(ssi4_data),
4495 SH_PFC_PIN_GROUP(ssi4_ctrl),
4496 SH_PFC_PIN_GROUP(ssi5_data),
4497 SH_PFC_PIN_GROUP(ssi5_ctrl),
4498 SH_PFC_PIN_GROUP(ssi6_data),
4499 SH_PFC_PIN_GROUP(ssi6_ctrl),
4500 SH_PFC_PIN_GROUP(ssi7_data),
4501 SH_PFC_PIN_GROUP(ssi78_ctrl),
4502 SH_PFC_PIN_GROUP(ssi8_data),
4503 SH_PFC_PIN_GROUP(ssi9_data_a),
4504 SH_PFC_PIN_GROUP(ssi9_data_b),
4505 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4506 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4507 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4508 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4509 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4510 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4511 SH_PFC_PIN_GROUP(tpu_to0),
4512 SH_PFC_PIN_GROUP(tpu_to1),
4513 SH_PFC_PIN_GROUP(tpu_to2),
4514 SH_PFC_PIN_GROUP(tpu_to3),
4515 SH_PFC_PIN_GROUP(usb0),
4516 SH_PFC_PIN_GROUP(usb1),
4517 SH_PFC_PIN_GROUP(usb2),
4518 SH_PFC_PIN_GROUP(usb2_ch3),
4519 SH_PFC_PIN_GROUP(usb30),
4520 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4521 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4522 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4523 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4524 SH_PFC_PIN_GROUP(vin4_data18_a),
4525 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4526 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4527 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4528 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4529 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4530 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4531 SH_PFC_PIN_GROUP(vin4_data18_b),
4532 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4533 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4534 SH_PFC_PIN_GROUP(vin4_sync),
4535 SH_PFC_PIN_GROUP(vin4_field),
4536 SH_PFC_PIN_GROUP(vin4_clkenb),
4537 SH_PFC_PIN_GROUP(vin4_clk),
4538 VIN_DATA_PIN_GROUP(vin5_data, 8),
4539 VIN_DATA_PIN_GROUP(vin5_data, 10),
4540 VIN_DATA_PIN_GROUP(vin5_data, 12),
4541 VIN_DATA_PIN_GROUP(vin5_data, 16),
4542 SH_PFC_PIN_GROUP(vin5_sync),
4543 SH_PFC_PIN_GROUP(vin5_field),
4544 SH_PFC_PIN_GROUP(vin5_clkenb),
4545 SH_PFC_PIN_GROUP(vin5_clk),
4546 },
4547 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4548 .automotive = {
4549 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4550 SH_PFC_PIN_GROUP(drif0_data0_a),
4551 SH_PFC_PIN_GROUP(drif0_data1_a),
4552 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4553 SH_PFC_PIN_GROUP(drif0_data0_b),
4554 SH_PFC_PIN_GROUP(drif0_data1_b),
4555 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4556 SH_PFC_PIN_GROUP(drif0_data0_c),
4557 SH_PFC_PIN_GROUP(drif0_data1_c),
4558 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4559 SH_PFC_PIN_GROUP(drif1_data0_a),
4560 SH_PFC_PIN_GROUP(drif1_data1_a),
4561 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4562 SH_PFC_PIN_GROUP(drif1_data0_b),
4563 SH_PFC_PIN_GROUP(drif1_data1_b),
4564 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4565 SH_PFC_PIN_GROUP(drif1_data0_c),
4566 SH_PFC_PIN_GROUP(drif1_data1_c),
4567 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4568 SH_PFC_PIN_GROUP(drif2_data0_a),
4569 SH_PFC_PIN_GROUP(drif2_data1_a),
4570 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4571 SH_PFC_PIN_GROUP(drif2_data0_b),
4572 SH_PFC_PIN_GROUP(drif2_data1_b),
4573 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4574 SH_PFC_PIN_GROUP(drif3_data0_a),
4575 SH_PFC_PIN_GROUP(drif3_data1_a),
4576 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4577 SH_PFC_PIN_GROUP(drif3_data0_b),
4578 SH_PFC_PIN_GROUP(drif3_data1_b),
4579 }
4580 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4581 };
4582
4583 static const char * const audio_clk_groups[] = {
4584 "audio_clk_a_a",
4585 "audio_clk_a_b",
4586 "audio_clk_a_c",
4587 "audio_clk_b_a",
4588 "audio_clk_b_b",
4589 "audio_clk_c_a",
4590 "audio_clk_c_b",
4591 "audio_clkout_a",
4592 "audio_clkout_b",
4593 "audio_clkout_c",
4594 "audio_clkout_d",
4595 "audio_clkout1_a",
4596 "audio_clkout1_b",
4597 "audio_clkout2_a",
4598 "audio_clkout2_b",
4599 "audio_clkout3_a",
4600 "audio_clkout3_b",
4601 };
4602
4603 static const char * const avb_groups[] = {
4604 "avb_link",
4605 "avb_magic",
4606 "avb_phy_int",
4607 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4608 "avb_mdio",
4609 "avb_mii",
4610 "avb_avtp_pps",
4611 "avb_avtp_match_a",
4612 "avb_avtp_capture_a",
4613 "avb_avtp_match_b",
4614 "avb_avtp_capture_b",
4615 };
4616
4617 static const char * const can0_groups[] = {
4618 "can0_data_a",
4619 "can0_data_b",
4620 };
4621
4622 static const char * const can1_groups[] = {
4623 "can1_data",
4624 };
4625
4626 static const char * const can_clk_groups[] = {
4627 "can_clk",
4628 };
4629
4630 static const char * const canfd0_groups[] = {
4631 "canfd0_data_a",
4632 "canfd0_data_b",
4633 };
4634
4635 static const char * const canfd1_groups[] = {
4636 "canfd1_data",
4637 };
4638
4639 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4640 static const char * const drif0_groups[] = {
4641 "drif0_ctrl_a",
4642 "drif0_data0_a",
4643 "drif0_data1_a",
4644 "drif0_ctrl_b",
4645 "drif0_data0_b",
4646 "drif0_data1_b",
4647 "drif0_ctrl_c",
4648 "drif0_data0_c",
4649 "drif0_data1_c",
4650 };
4651
4652 static const char * const drif1_groups[] = {
4653 "drif1_ctrl_a",
4654 "drif1_data0_a",
4655 "drif1_data1_a",
4656 "drif1_ctrl_b",
4657 "drif1_data0_b",
4658 "drif1_data1_b",
4659 "drif1_ctrl_c",
4660 "drif1_data0_c",
4661 "drif1_data1_c",
4662 };
4663
4664 static const char * const drif2_groups[] = {
4665 "drif2_ctrl_a",
4666 "drif2_data0_a",
4667 "drif2_data1_a",
4668 "drif2_ctrl_b",
4669 "drif2_data0_b",
4670 "drif2_data1_b",
4671 };
4672
4673 static const char * const drif3_groups[] = {
4674 "drif3_ctrl_a",
4675 "drif3_data0_a",
4676 "drif3_data1_a",
4677 "drif3_ctrl_b",
4678 "drif3_data0_b",
4679 "drif3_data1_b",
4680 };
4681 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4682
4683 static const char * const du_groups[] = {
4684 "du_rgb666",
4685 "du_rgb888",
4686 "du_clk_out_0",
4687 "du_clk_out_1",
4688 "du_sync",
4689 "du_oddf",
4690 "du_cde",
4691 "du_disp",
4692 };
4693
4694 static const char * const hscif0_groups[] = {
4695 "hscif0_data",
4696 "hscif0_clk",
4697 "hscif0_ctrl",
4698 };
4699
4700 static const char * const hscif1_groups[] = {
4701 "hscif1_data_a",
4702 "hscif1_clk_a",
4703 "hscif1_ctrl_a",
4704 "hscif1_data_b",
4705 "hscif1_clk_b",
4706 "hscif1_ctrl_b",
4707 };
4708
4709 static const char * const hscif2_groups[] = {
4710 "hscif2_data_a",
4711 "hscif2_clk_a",
4712 "hscif2_ctrl_a",
4713 "hscif2_data_b",
4714 "hscif2_clk_b",
4715 "hscif2_ctrl_b",
4716 "hscif2_data_c",
4717 "hscif2_clk_c",
4718 "hscif2_ctrl_c",
4719 };
4720
4721 static const char * const hscif3_groups[] = {
4722 "hscif3_data_a",
4723 "hscif3_clk",
4724 "hscif3_ctrl",
4725 "hscif3_data_b",
4726 "hscif3_data_c",
4727 "hscif3_data_d",
4728 };
4729
4730 static const char * const hscif4_groups[] = {
4731 "hscif4_data_a",
4732 "hscif4_clk",
4733 "hscif4_ctrl",
4734 "hscif4_data_b",
4735 };
4736
4737 static const char * const i2c0_groups[] = {
4738 "i2c0",
4739 };
4740
4741 static const char * const i2c1_groups[] = {
4742 "i2c1_a",
4743 "i2c1_b",
4744 };
4745
4746 static const char * const i2c2_groups[] = {
4747 "i2c2_a",
4748 "i2c2_b",
4749 };
4750
4751 static const char * const i2c3_groups[] = {
4752 "i2c3",
4753 };
4754
4755 static const char * const i2c5_groups[] = {
4756 "i2c5",
4757 };
4758
4759 static const char * const i2c6_groups[] = {
4760 "i2c6_a",
4761 "i2c6_b",
4762 "i2c6_c",
4763 };
4764
4765 static const char * const intc_ex_groups[] = {
4766 "intc_ex_irq0",
4767 "intc_ex_irq1",
4768 "intc_ex_irq2",
4769 "intc_ex_irq3",
4770 "intc_ex_irq4",
4771 "intc_ex_irq5",
4772 };
4773
4774 static const char * const msiof0_groups[] = {
4775 "msiof0_clk",
4776 "msiof0_sync",
4777 "msiof0_ss1",
4778 "msiof0_ss2",
4779 "msiof0_txd",
4780 "msiof0_rxd",
4781 };
4782
4783 static const char * const msiof1_groups[] = {
4784 "msiof1_clk_a",
4785 "msiof1_sync_a",
4786 "msiof1_ss1_a",
4787 "msiof1_ss2_a",
4788 "msiof1_txd_a",
4789 "msiof1_rxd_a",
4790 "msiof1_clk_b",
4791 "msiof1_sync_b",
4792 "msiof1_ss1_b",
4793 "msiof1_ss2_b",
4794 "msiof1_txd_b",
4795 "msiof1_rxd_b",
4796 "msiof1_clk_c",
4797 "msiof1_sync_c",
4798 "msiof1_ss1_c",
4799 "msiof1_ss2_c",
4800 "msiof1_txd_c",
4801 "msiof1_rxd_c",
4802 "msiof1_clk_d",
4803 "msiof1_sync_d",
4804 "msiof1_ss1_d",
4805 "msiof1_ss2_d",
4806 "msiof1_txd_d",
4807 "msiof1_rxd_d",
4808 "msiof1_clk_e",
4809 "msiof1_sync_e",
4810 "msiof1_ss1_e",
4811 "msiof1_ss2_e",
4812 "msiof1_txd_e",
4813 "msiof1_rxd_e",
4814 "msiof1_clk_f",
4815 "msiof1_sync_f",
4816 "msiof1_ss1_f",
4817 "msiof1_ss2_f",
4818 "msiof1_txd_f",
4819 "msiof1_rxd_f",
4820 "msiof1_clk_g",
4821 "msiof1_sync_g",
4822 "msiof1_ss1_g",
4823 "msiof1_ss2_g",
4824 "msiof1_txd_g",
4825 "msiof1_rxd_g",
4826 };
4827
4828 static const char * const msiof2_groups[] = {
4829 "msiof2_clk_a",
4830 "msiof2_sync_a",
4831 "msiof2_ss1_a",
4832 "msiof2_ss2_a",
4833 "msiof2_txd_a",
4834 "msiof2_rxd_a",
4835 "msiof2_clk_b",
4836 "msiof2_sync_b",
4837 "msiof2_ss1_b",
4838 "msiof2_ss2_b",
4839 "msiof2_txd_b",
4840 "msiof2_rxd_b",
4841 "msiof2_clk_c",
4842 "msiof2_sync_c",
4843 "msiof2_ss1_c",
4844 "msiof2_ss2_c",
4845 "msiof2_txd_c",
4846 "msiof2_rxd_c",
4847 "msiof2_clk_d",
4848 "msiof2_sync_d",
4849 "msiof2_ss1_d",
4850 "msiof2_ss2_d",
4851 "msiof2_txd_d",
4852 "msiof2_rxd_d",
4853 };
4854
4855 static const char * const msiof3_groups[] = {
4856 "msiof3_clk_a",
4857 "msiof3_sync_a",
4858 "msiof3_ss1_a",
4859 "msiof3_ss2_a",
4860 "msiof3_txd_a",
4861 "msiof3_rxd_a",
4862 "msiof3_clk_b",
4863 "msiof3_sync_b",
4864 "msiof3_ss1_b",
4865 "msiof3_ss2_b",
4866 "msiof3_txd_b",
4867 "msiof3_rxd_b",
4868 "msiof3_clk_c",
4869 "msiof3_sync_c",
4870 "msiof3_txd_c",
4871 "msiof3_rxd_c",
4872 "msiof3_clk_d",
4873 "msiof3_sync_d",
4874 "msiof3_ss1_d",
4875 "msiof3_txd_d",
4876 "msiof3_rxd_d",
4877 "msiof3_clk_e",
4878 "msiof3_sync_e",
4879 "msiof3_ss1_e",
4880 "msiof3_ss2_e",
4881 "msiof3_txd_e",
4882 "msiof3_rxd_e",
4883 };
4884
4885 static const char * const pwm0_groups[] = {
4886 "pwm0",
4887 };
4888
4889 static const char * const pwm1_groups[] = {
4890 "pwm1_a",
4891 "pwm1_b",
4892 };
4893
4894 static const char * const pwm2_groups[] = {
4895 "pwm2_a",
4896 "pwm2_b",
4897 };
4898
4899 static const char * const pwm3_groups[] = {
4900 "pwm3_a",
4901 "pwm3_b",
4902 };
4903
4904 static const char * const pwm4_groups[] = {
4905 "pwm4_a",
4906 "pwm4_b",
4907 };
4908
4909 static const char * const pwm5_groups[] = {
4910 "pwm5_a",
4911 "pwm5_b",
4912 };
4913
4914 static const char * const pwm6_groups[] = {
4915 "pwm6_a",
4916 "pwm6_b",
4917 };
4918
4919 static const char * const qspi0_groups[] = {
4920 "qspi0_ctrl",
4921 "qspi0_data2",
4922 "qspi0_data4",
4923 };
4924
4925 static const char * const qspi1_groups[] = {
4926 "qspi1_ctrl",
4927 "qspi1_data2",
4928 "qspi1_data4",
4929 };
4930
4931 static const char * const sata0_groups[] = {
4932 "sata0_devslp_a",
4933 "sata0_devslp_b",
4934 };
4935
4936 static const char * const scif0_groups[] = {
4937 "scif0_data",
4938 "scif0_clk",
4939 "scif0_ctrl",
4940 };
4941
4942 static const char * const scif1_groups[] = {
4943 "scif1_data_a",
4944 "scif1_clk",
4945 "scif1_ctrl",
4946 "scif1_data_b",
4947 };
4948
4949 static const char * const scif2_groups[] = {
4950 "scif2_data_a",
4951 "scif2_clk",
4952 "scif2_data_b",
4953 };
4954
4955 static const char * const scif3_groups[] = {
4956 "scif3_data_a",
4957 "scif3_clk",
4958 "scif3_ctrl",
4959 "scif3_data_b",
4960 };
4961
4962 static const char * const scif4_groups[] = {
4963 "scif4_data_a",
4964 "scif4_clk_a",
4965 "scif4_ctrl_a",
4966 "scif4_data_b",
4967 "scif4_clk_b",
4968 "scif4_ctrl_b",
4969 "scif4_data_c",
4970 "scif4_clk_c",
4971 "scif4_ctrl_c",
4972 };
4973
4974 static const char * const scif5_groups[] = {
4975 "scif5_data_a",
4976 "scif5_clk_a",
4977 "scif5_data_b",
4978 "scif5_clk_b",
4979 };
4980
4981 static const char * const scif_clk_groups[] = {
4982 "scif_clk_a",
4983 "scif_clk_b",
4984 };
4985
4986 static const char * const sdhi0_groups[] = {
4987 "sdhi0_data1",
4988 "sdhi0_data4",
4989 "sdhi0_ctrl",
4990 "sdhi0_cd",
4991 "sdhi0_wp",
4992 };
4993
4994 static const char * const sdhi1_groups[] = {
4995 "sdhi1_data1",
4996 "sdhi1_data4",
4997 "sdhi1_ctrl",
4998 "sdhi1_cd",
4999 "sdhi1_wp",
5000 };
5001
5002 static const char * const sdhi2_groups[] = {
5003 "sdhi2_data1",
5004 "sdhi2_data4",
5005 "sdhi2_data8",
5006 "sdhi2_ctrl",
5007 "sdhi2_cd_a",
5008 "sdhi2_wp_a",
5009 "sdhi2_cd_b",
5010 "sdhi2_wp_b",
5011 "sdhi2_ds",
5012 };
5013
5014 static const char * const sdhi3_groups[] = {
5015 "sdhi3_data1",
5016 "sdhi3_data4",
5017 "sdhi3_data8",
5018 "sdhi3_ctrl",
5019 "sdhi3_cd",
5020 "sdhi3_wp",
5021 "sdhi3_ds",
5022 };
5023
5024 static const char * const ssi_groups[] = {
5025 "ssi0_data",
5026 "ssi01239_ctrl",
5027 "ssi1_data_a",
5028 "ssi1_data_b",
5029 "ssi1_ctrl_a",
5030 "ssi1_ctrl_b",
5031 "ssi2_data_a",
5032 "ssi2_data_b",
5033 "ssi2_ctrl_a",
5034 "ssi2_ctrl_b",
5035 "ssi3_data",
5036 "ssi349_ctrl",
5037 "ssi4_data",
5038 "ssi4_ctrl",
5039 "ssi5_data",
5040 "ssi5_ctrl",
5041 "ssi6_data",
5042 "ssi6_ctrl",
5043 "ssi7_data",
5044 "ssi78_ctrl",
5045 "ssi8_data",
5046 "ssi9_data_a",
5047 "ssi9_data_b",
5048 "ssi9_ctrl_a",
5049 "ssi9_ctrl_b",
5050 };
5051
5052 static const char * const tmu_groups[] = {
5053 "tmu_tclk1_a",
5054 "tmu_tclk1_b",
5055 "tmu_tclk2_a",
5056 "tmu_tclk2_b",
5057 };
5058
5059 static const char * const tpu_groups[] = {
5060 "tpu_to0",
5061 "tpu_to1",
5062 "tpu_to2",
5063 "tpu_to3",
5064 };
5065
5066 static const char * const usb0_groups[] = {
5067 "usb0",
5068 };
5069
5070 static const char * const usb1_groups[] = {
5071 "usb1",
5072 };
5073
5074 static const char * const usb2_groups[] = {
5075 "usb2",
5076 };
5077
5078 static const char * const usb2_ch3_groups[] = {
5079 "usb2_ch3",
5080 };
5081
5082 static const char * const usb30_groups[] = {
5083 "usb30",
5084 };
5085
5086 static const char * const vin4_groups[] = {
5087 "vin4_data8_a",
5088 "vin4_data10_a",
5089 "vin4_data12_a",
5090 "vin4_data16_a",
5091 "vin4_data18_a",
5092 "vin4_data20_a",
5093 "vin4_data24_a",
5094 "vin4_data8_b",
5095 "vin4_data10_b",
5096 "vin4_data12_b",
5097 "vin4_data16_b",
5098 "vin4_data18_b",
5099 "vin4_data20_b",
5100 "vin4_data24_b",
5101 "vin4_sync",
5102 "vin4_field",
5103 "vin4_clkenb",
5104 "vin4_clk",
5105 };
5106
5107 static const char * const vin5_groups[] = {
5108 "vin5_data8",
5109 "vin5_data10",
5110 "vin5_data12",
5111 "vin5_data16",
5112 "vin5_sync",
5113 "vin5_field",
5114 "vin5_clkenb",
5115 "vin5_clk",
5116 };
5117
5118 static const struct {
5119 struct sh_pfc_function common[55];
5120 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5121 struct sh_pfc_function automotive[4];
5122 #endif
5123 } pinmux_functions = {
5124 .common = {
5125 SH_PFC_FUNCTION(audio_clk),
5126 SH_PFC_FUNCTION(avb),
5127 SH_PFC_FUNCTION(can0),
5128 SH_PFC_FUNCTION(can1),
5129 SH_PFC_FUNCTION(can_clk),
5130 SH_PFC_FUNCTION(canfd0),
5131 SH_PFC_FUNCTION(canfd1),
5132 SH_PFC_FUNCTION(du),
5133 SH_PFC_FUNCTION(hscif0),
5134 SH_PFC_FUNCTION(hscif1),
5135 SH_PFC_FUNCTION(hscif2),
5136 SH_PFC_FUNCTION(hscif3),
5137 SH_PFC_FUNCTION(hscif4),
5138 SH_PFC_FUNCTION(i2c0),
5139 SH_PFC_FUNCTION(i2c1),
5140 SH_PFC_FUNCTION(i2c2),
5141 SH_PFC_FUNCTION(i2c3),
5142 SH_PFC_FUNCTION(i2c5),
5143 SH_PFC_FUNCTION(i2c6),
5144 SH_PFC_FUNCTION(intc_ex),
5145 SH_PFC_FUNCTION(msiof0),
5146 SH_PFC_FUNCTION(msiof1),
5147 SH_PFC_FUNCTION(msiof2),
5148 SH_PFC_FUNCTION(msiof3),
5149 SH_PFC_FUNCTION(pwm0),
5150 SH_PFC_FUNCTION(pwm1),
5151 SH_PFC_FUNCTION(pwm2),
5152 SH_PFC_FUNCTION(pwm3),
5153 SH_PFC_FUNCTION(pwm4),
5154 SH_PFC_FUNCTION(pwm5),
5155 SH_PFC_FUNCTION(pwm6),
5156 SH_PFC_FUNCTION(qspi0),
5157 SH_PFC_FUNCTION(qspi1),
5158 SH_PFC_FUNCTION(sata0),
5159 SH_PFC_FUNCTION(scif0),
5160 SH_PFC_FUNCTION(scif1),
5161 SH_PFC_FUNCTION(scif2),
5162 SH_PFC_FUNCTION(scif3),
5163 SH_PFC_FUNCTION(scif4),
5164 SH_PFC_FUNCTION(scif5),
5165 SH_PFC_FUNCTION(scif_clk),
5166 SH_PFC_FUNCTION(sdhi0),
5167 SH_PFC_FUNCTION(sdhi1),
5168 SH_PFC_FUNCTION(sdhi2),
5169 SH_PFC_FUNCTION(sdhi3),
5170 SH_PFC_FUNCTION(ssi),
5171 SH_PFC_FUNCTION(tmu),
5172 SH_PFC_FUNCTION(tpu),
5173 SH_PFC_FUNCTION(usb0),
5174 SH_PFC_FUNCTION(usb1),
5175 SH_PFC_FUNCTION(usb2),
5176 SH_PFC_FUNCTION(usb2_ch3),
5177 SH_PFC_FUNCTION(usb30),
5178 SH_PFC_FUNCTION(vin4),
5179 SH_PFC_FUNCTION(vin5),
5180 },
5181 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5182 .automotive = {
5183 SH_PFC_FUNCTION(drif0),
5184 SH_PFC_FUNCTION(drif1),
5185 SH_PFC_FUNCTION(drif2),
5186 SH_PFC_FUNCTION(drif3),
5187 }
5188 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
5189 };
5190
5191 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5192 #define F_(x, y) FN_##y
5193 #define FM(x) FN_##x
5194 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5195 0, 0,
5196 0, 0,
5197 0, 0,
5198 0, 0,
5199 0, 0,
5200 0, 0,
5201 0, 0,
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 0, 0,
5209 0, 0,
5210 0, 0,
5211 GP_0_15_FN, GPSR0_15,
5212 GP_0_14_FN, GPSR0_14,
5213 GP_0_13_FN, GPSR0_13,
5214 GP_0_12_FN, GPSR0_12,
5215 GP_0_11_FN, GPSR0_11,
5216 GP_0_10_FN, GPSR0_10,
5217 GP_0_9_FN, GPSR0_9,
5218 GP_0_8_FN, GPSR0_8,
5219 GP_0_7_FN, GPSR0_7,
5220 GP_0_6_FN, GPSR0_6,
5221 GP_0_5_FN, GPSR0_5,
5222 GP_0_4_FN, GPSR0_4,
5223 GP_0_3_FN, GPSR0_3,
5224 GP_0_2_FN, GPSR0_2,
5225 GP_0_1_FN, GPSR0_1,
5226 GP_0_0_FN, GPSR0_0, ))
5227 },
5228 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5229 0, 0,
5230 0, 0,
5231 0, 0,
5232 GP_1_28_FN, GPSR1_28,
5233 GP_1_27_FN, GPSR1_27,
5234 GP_1_26_FN, GPSR1_26,
5235 GP_1_25_FN, GPSR1_25,
5236 GP_1_24_FN, GPSR1_24,
5237 GP_1_23_FN, GPSR1_23,
5238 GP_1_22_FN, GPSR1_22,
5239 GP_1_21_FN, GPSR1_21,
5240 GP_1_20_FN, GPSR1_20,
5241 GP_1_19_FN, GPSR1_19,
5242 GP_1_18_FN, GPSR1_18,
5243 GP_1_17_FN, GPSR1_17,
5244 GP_1_16_FN, GPSR1_16,
5245 GP_1_15_FN, GPSR1_15,
5246 GP_1_14_FN, GPSR1_14,
5247 GP_1_13_FN, GPSR1_13,
5248 GP_1_12_FN, GPSR1_12,
5249 GP_1_11_FN, GPSR1_11,
5250 GP_1_10_FN, GPSR1_10,
5251 GP_1_9_FN, GPSR1_9,
5252 GP_1_8_FN, GPSR1_8,
5253 GP_1_7_FN, GPSR1_7,
5254 GP_1_6_FN, GPSR1_6,
5255 GP_1_5_FN, GPSR1_5,
5256 GP_1_4_FN, GPSR1_4,
5257 GP_1_3_FN, GPSR1_3,
5258 GP_1_2_FN, GPSR1_2,
5259 GP_1_1_FN, GPSR1_1,
5260 GP_1_0_FN, GPSR1_0, ))
5261 },
5262 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5263 0, 0,
5264 0, 0,
5265 0, 0,
5266 0, 0,
5267 0, 0,
5268 0, 0,
5269 0, 0,
5270 0, 0,
5271 0, 0,
5272 0, 0,
5273 0, 0,
5274 0, 0,
5275 0, 0,
5276 0, 0,
5277 0, 0,
5278 0, 0,
5279 0, 0,
5280 GP_2_14_FN, GPSR2_14,
5281 GP_2_13_FN, GPSR2_13,
5282 GP_2_12_FN, GPSR2_12,
5283 GP_2_11_FN, GPSR2_11,
5284 GP_2_10_FN, GPSR2_10,
5285 GP_2_9_FN, GPSR2_9,
5286 GP_2_8_FN, GPSR2_8,
5287 GP_2_7_FN, GPSR2_7,
5288 GP_2_6_FN, GPSR2_6,
5289 GP_2_5_FN, GPSR2_5,
5290 GP_2_4_FN, GPSR2_4,
5291 GP_2_3_FN, GPSR2_3,
5292 GP_2_2_FN, GPSR2_2,
5293 GP_2_1_FN, GPSR2_1,
5294 GP_2_0_FN, GPSR2_0, ))
5295 },
5296 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5297 0, 0,
5298 0, 0,
5299 0, 0,
5300 0, 0,
5301 0, 0,
5302 0, 0,
5303 0, 0,
5304 0, 0,
5305 0, 0,
5306 0, 0,
5307 0, 0,
5308 0, 0,
5309 0, 0,
5310 0, 0,
5311 0, 0,
5312 0, 0,
5313 GP_3_15_FN, GPSR3_15,
5314 GP_3_14_FN, GPSR3_14,
5315 GP_3_13_FN, GPSR3_13,
5316 GP_3_12_FN, GPSR3_12,
5317 GP_3_11_FN, GPSR3_11,
5318 GP_3_10_FN, GPSR3_10,
5319 GP_3_9_FN, GPSR3_9,
5320 GP_3_8_FN, GPSR3_8,
5321 GP_3_7_FN, GPSR3_7,
5322 GP_3_6_FN, GPSR3_6,
5323 GP_3_5_FN, GPSR3_5,
5324 GP_3_4_FN, GPSR3_4,
5325 GP_3_3_FN, GPSR3_3,
5326 GP_3_2_FN, GPSR3_2,
5327 GP_3_1_FN, GPSR3_1,
5328 GP_3_0_FN, GPSR3_0, ))
5329 },
5330 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5331 0, 0,
5332 0, 0,
5333 0, 0,
5334 0, 0,
5335 0, 0,
5336 0, 0,
5337 0, 0,
5338 0, 0,
5339 0, 0,
5340 0, 0,
5341 0, 0,
5342 0, 0,
5343 0, 0,
5344 0, 0,
5345 GP_4_17_FN, GPSR4_17,
5346 GP_4_16_FN, GPSR4_16,
5347 GP_4_15_FN, GPSR4_15,
5348 GP_4_14_FN, GPSR4_14,
5349 GP_4_13_FN, GPSR4_13,
5350 GP_4_12_FN, GPSR4_12,
5351 GP_4_11_FN, GPSR4_11,
5352 GP_4_10_FN, GPSR4_10,
5353 GP_4_9_FN, GPSR4_9,
5354 GP_4_8_FN, GPSR4_8,
5355 GP_4_7_FN, GPSR4_7,
5356 GP_4_6_FN, GPSR4_6,
5357 GP_4_5_FN, GPSR4_5,
5358 GP_4_4_FN, GPSR4_4,
5359 GP_4_3_FN, GPSR4_3,
5360 GP_4_2_FN, GPSR4_2,
5361 GP_4_1_FN, GPSR4_1,
5362 GP_4_0_FN, GPSR4_0, ))
5363 },
5364 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5365 0, 0,
5366 0, 0,
5367 0, 0,
5368 0, 0,
5369 0, 0,
5370 0, 0,
5371 GP_5_25_FN, GPSR5_25,
5372 GP_5_24_FN, GPSR5_24,
5373 GP_5_23_FN, GPSR5_23,
5374 GP_5_22_FN, GPSR5_22,
5375 GP_5_21_FN, GPSR5_21,
5376 GP_5_20_FN, GPSR5_20,
5377 GP_5_19_FN, GPSR5_19,
5378 GP_5_18_FN, GPSR5_18,
5379 GP_5_17_FN, GPSR5_17,
5380 GP_5_16_FN, GPSR5_16,
5381 GP_5_15_FN, GPSR5_15,
5382 GP_5_14_FN, GPSR5_14,
5383 GP_5_13_FN, GPSR5_13,
5384 GP_5_12_FN, GPSR5_12,
5385 GP_5_11_FN, GPSR5_11,
5386 GP_5_10_FN, GPSR5_10,
5387 GP_5_9_FN, GPSR5_9,
5388 GP_5_8_FN, GPSR5_8,
5389 GP_5_7_FN, GPSR5_7,
5390 GP_5_6_FN, GPSR5_6,
5391 GP_5_5_FN, GPSR5_5,
5392 GP_5_4_FN, GPSR5_4,
5393 GP_5_3_FN, GPSR5_3,
5394 GP_5_2_FN, GPSR5_2,
5395 GP_5_1_FN, GPSR5_1,
5396 GP_5_0_FN, GPSR5_0, ))
5397 },
5398 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5399 GP_6_31_FN, GPSR6_31,
5400 GP_6_30_FN, GPSR6_30,
5401 GP_6_29_FN, GPSR6_29,
5402 GP_6_28_FN, GPSR6_28,
5403 GP_6_27_FN, GPSR6_27,
5404 GP_6_26_FN, GPSR6_26,
5405 GP_6_25_FN, GPSR6_25,
5406 GP_6_24_FN, GPSR6_24,
5407 GP_6_23_FN, GPSR6_23,
5408 GP_6_22_FN, GPSR6_22,
5409 GP_6_21_FN, GPSR6_21,
5410 GP_6_20_FN, GPSR6_20,
5411 GP_6_19_FN, GPSR6_19,
5412 GP_6_18_FN, GPSR6_18,
5413 GP_6_17_FN, GPSR6_17,
5414 GP_6_16_FN, GPSR6_16,
5415 GP_6_15_FN, GPSR6_15,
5416 GP_6_14_FN, GPSR6_14,
5417 GP_6_13_FN, GPSR6_13,
5418 GP_6_12_FN, GPSR6_12,
5419 GP_6_11_FN, GPSR6_11,
5420 GP_6_10_FN, GPSR6_10,
5421 GP_6_9_FN, GPSR6_9,
5422 GP_6_8_FN, GPSR6_8,
5423 GP_6_7_FN, GPSR6_7,
5424 GP_6_6_FN, GPSR6_6,
5425 GP_6_5_FN, GPSR6_5,
5426 GP_6_4_FN, GPSR6_4,
5427 GP_6_3_FN, GPSR6_3,
5428 GP_6_2_FN, GPSR6_2,
5429 GP_6_1_FN, GPSR6_1,
5430 GP_6_0_FN, GPSR6_0, ))
5431 },
5432 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5433 0, 0,
5434 0, 0,
5435 0, 0,
5436 0, 0,
5437 0, 0,
5438 0, 0,
5439 0, 0,
5440 0, 0,
5441 0, 0,
5442 0, 0,
5443 0, 0,
5444 0, 0,
5445 0, 0,
5446 0, 0,
5447 0, 0,
5448 0, 0,
5449 0, 0,
5450 0, 0,
5451 0, 0,
5452 0, 0,
5453 0, 0,
5454 0, 0,
5455 0, 0,
5456 0, 0,
5457 0, 0,
5458 0, 0,
5459 0, 0,
5460 0, 0,
5461 GP_7_3_FN, GPSR7_3,
5462 GP_7_2_FN, GPSR7_2,
5463 GP_7_1_FN, GPSR7_1,
5464 GP_7_0_FN, GPSR7_0, ))
5465 },
5466 #undef F_
5467 #undef FM
5468
5469 #define F_(x, y) x,
5470 #define FM(x) FN_##x,
5471 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5472 IP0_31_28
5473 IP0_27_24
5474 IP0_23_20
5475 IP0_19_16
5476 IP0_15_12
5477 IP0_11_8
5478 IP0_7_4
5479 IP0_3_0 ))
5480 },
5481 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5482 IP1_31_28
5483 IP1_27_24
5484 IP1_23_20
5485 IP1_19_16
5486 IP1_15_12
5487 IP1_11_8
5488 IP1_7_4
5489 IP1_3_0 ))
5490 },
5491 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5492 IP2_31_28
5493 IP2_27_24
5494 IP2_23_20
5495 IP2_19_16
5496 IP2_15_12
5497 IP2_11_8
5498 IP2_7_4
5499 IP2_3_0 ))
5500 },
5501 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5502 IP3_31_28
5503 IP3_27_24
5504 IP3_23_20
5505 IP3_19_16
5506 IP3_15_12
5507 IP3_11_8
5508 IP3_7_4
5509 IP3_3_0 ))
5510 },
5511 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5512 IP4_31_28
5513 IP4_27_24
5514 IP4_23_20
5515 IP4_19_16
5516 IP4_15_12
5517 IP4_11_8
5518 IP4_7_4
5519 IP4_3_0 ))
5520 },
5521 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5522 IP5_31_28
5523 IP5_27_24
5524 IP5_23_20
5525 IP5_19_16
5526 IP5_15_12
5527 IP5_11_8
5528 IP5_7_4
5529 IP5_3_0 ))
5530 },
5531 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5532 IP6_31_28
5533 IP6_27_24
5534 IP6_23_20
5535 IP6_19_16
5536 IP6_15_12
5537 IP6_11_8
5538 IP6_7_4
5539 IP6_3_0 ))
5540 },
5541 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5542 IP7_31_28
5543 IP7_27_24
5544 IP7_23_20
5545 IP7_19_16
5546 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5547 IP7_11_8
5548 IP7_7_4
5549 IP7_3_0 ))
5550 },
5551 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5552 IP8_31_28
5553 IP8_27_24
5554 IP8_23_20
5555 IP8_19_16
5556 IP8_15_12
5557 IP8_11_8
5558 IP8_7_4
5559 IP8_3_0 ))
5560 },
5561 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5562 IP9_31_28
5563 IP9_27_24
5564 IP9_23_20
5565 IP9_19_16
5566 IP9_15_12
5567 IP9_11_8
5568 IP9_7_4
5569 IP9_3_0 ))
5570 },
5571 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5572 IP10_31_28
5573 IP10_27_24
5574 IP10_23_20
5575 IP10_19_16
5576 IP10_15_12
5577 IP10_11_8
5578 IP10_7_4
5579 IP10_3_0 ))
5580 },
5581 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5582 IP11_31_28
5583 IP11_27_24
5584 IP11_23_20
5585 IP11_19_16
5586 IP11_15_12
5587 IP11_11_8
5588 IP11_7_4
5589 IP11_3_0 ))
5590 },
5591 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5592 IP12_31_28
5593 IP12_27_24
5594 IP12_23_20
5595 IP12_19_16
5596 IP12_15_12
5597 IP12_11_8
5598 IP12_7_4
5599 IP12_3_0 ))
5600 },
5601 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5602 IP13_31_28
5603 IP13_27_24
5604 IP13_23_20
5605 IP13_19_16
5606 IP13_15_12
5607 IP13_11_8
5608 IP13_7_4
5609 IP13_3_0 ))
5610 },
5611 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5612 IP14_31_28
5613 IP14_27_24
5614 IP14_23_20
5615 IP14_19_16
5616 IP14_15_12
5617 IP14_11_8
5618 IP14_7_4
5619 IP14_3_0 ))
5620 },
5621 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5622 IP15_31_28
5623 IP15_27_24
5624 IP15_23_20
5625 IP15_19_16
5626 IP15_15_12
5627 IP15_11_8
5628 IP15_7_4
5629 IP15_3_0 ))
5630 },
5631 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5632 IP16_31_28
5633 IP16_27_24
5634 IP16_23_20
5635 IP16_19_16
5636 IP16_15_12
5637 IP16_11_8
5638 IP16_7_4
5639 IP16_3_0 ))
5640 },
5641 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5642 IP17_31_28
5643 IP17_27_24
5644 IP17_23_20
5645 IP17_19_16
5646 IP17_15_12
5647 IP17_11_8
5648 IP17_7_4
5649 IP17_3_0 ))
5650 },
5651 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5652 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5653 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5654 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5655 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5656 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5657 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5658 IP18_7_4
5659 IP18_3_0 ))
5660 },
5661 #undef F_
5662 #undef FM
5663
5664 #define F_(x, y) x,
5665 #define FM(x) FN_##x,
5666 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5667 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5668 1, 1, 1, 2, 2, 1, 2, 3),
5669 GROUP(
5670 MOD_SEL0_31_30_29
5671 MOD_SEL0_28_27
5672 MOD_SEL0_26_25_24
5673 MOD_SEL0_23
5674 MOD_SEL0_22
5675 MOD_SEL0_21
5676 MOD_SEL0_20
5677 MOD_SEL0_19
5678 MOD_SEL0_18_17
5679 MOD_SEL0_16
5680 0, 0, /* RESERVED 15 */
5681 MOD_SEL0_14_13
5682 MOD_SEL0_12
5683 MOD_SEL0_11
5684 MOD_SEL0_10
5685 MOD_SEL0_9_8
5686 MOD_SEL0_7_6
5687 MOD_SEL0_5
5688 MOD_SEL0_4_3
5689 /* RESERVED 2, 1, 0 */
5690 0, 0, 0, 0, 0, 0, 0, 0 ))
5691 },
5692 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5693 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5694 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5695 GROUP(
5696 MOD_SEL1_31_30
5697 MOD_SEL1_29_28_27
5698 MOD_SEL1_26
5699 MOD_SEL1_25_24
5700 MOD_SEL1_23_22_21
5701 MOD_SEL1_20
5702 MOD_SEL1_19
5703 MOD_SEL1_18_17
5704 MOD_SEL1_16
5705 MOD_SEL1_15_14
5706 MOD_SEL1_13
5707 MOD_SEL1_12
5708 MOD_SEL1_11
5709 MOD_SEL1_10
5710 MOD_SEL1_9
5711 0, 0, 0, 0, /* RESERVED 8, 7 */
5712 MOD_SEL1_6
5713 MOD_SEL1_5
5714 MOD_SEL1_4
5715 MOD_SEL1_3
5716 MOD_SEL1_2
5717 MOD_SEL1_1
5718 MOD_SEL1_0 ))
5719 },
5720 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5721 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5722 1, 4, 4, 4, 3, 1),
5723 GROUP(
5724 MOD_SEL2_31
5725 MOD_SEL2_30
5726 MOD_SEL2_29
5727 MOD_SEL2_28_27
5728 MOD_SEL2_26
5729 MOD_SEL2_25_24_23
5730 /* RESERVED 22 */
5731 0, 0,
5732 MOD_SEL2_21
5733 MOD_SEL2_20
5734 MOD_SEL2_19
5735 MOD_SEL2_18
5736 MOD_SEL2_17
5737 /* RESERVED 16 */
5738 0, 0,
5739 /* RESERVED 15, 14, 13, 12 */
5740 0, 0, 0, 0, 0, 0, 0, 0,
5741 0, 0, 0, 0, 0, 0, 0, 0,
5742 /* RESERVED 11, 10, 9, 8 */
5743 0, 0, 0, 0, 0, 0, 0, 0,
5744 0, 0, 0, 0, 0, 0, 0, 0,
5745 /* RESERVED 7, 6, 5, 4 */
5746 0, 0, 0, 0, 0, 0, 0, 0,
5747 0, 0, 0, 0, 0, 0, 0, 0,
5748 /* RESERVED 3, 2, 1 */
5749 0, 0, 0, 0, 0, 0, 0, 0,
5750 MOD_SEL2_0 ))
5751 },
5752 { },
5753 };
5754
5755 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5756 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5757 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5758 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5759 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5760 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5761 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5762 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5763 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5764 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5765 } },
5766 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5767 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5768 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5769 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5770 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5771 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5772 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5773 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5774 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5775 } },
5776 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5777 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5778 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5779 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5780 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5781 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5782 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5783 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5784 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5785 } },
5786 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5787 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5788 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5789 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5790 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5791 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5792 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5793 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5794 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5795 } },
5796 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5797 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5798 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5799 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5800 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5801 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5802 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5803 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5804 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5805 } },
5806 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5807 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5808 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5809 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5810 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5811 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5812 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5813 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5814 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5815 } },
5816 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5817 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5818 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5819 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5820 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5821 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5822 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5823 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5824 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5827 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5828 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5829 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5830 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5831 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5832 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5833 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5834 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5835 } },
5836 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5837 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5838 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5839 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5840 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5841 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5842 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5843 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5844 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5845 } },
5846 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5847 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5848 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5849 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5850 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5851 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5852 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5853 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5854 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5855 } },
5856 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5857 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5858 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5859 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5860 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5861 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5862 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5863 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5864 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5865 } },
5866 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5867 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5868 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5869 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5870 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5871 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5872 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5873 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5874 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5875 } },
5876 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5877 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5878 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5879 #endif
5880 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5881 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5882 { PIN_TMS, 4, 2 }, /* TMS */
5883 } },
5884 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5885 { PIN_TDO, 28, 2 }, /* TDO */
5886 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5887 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5888 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5889 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5890 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5891 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5892 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5893 } },
5894 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5895 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5896 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5897 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5898 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5899 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5900 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5901 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5902 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5903 } },
5904 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5905 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5906 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5907 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5908 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5909 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5910 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5911 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5912 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5913 } },
5914 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5915 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5916 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5917 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5918 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5919 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5920 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5921 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5922 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5923 } },
5924 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5925 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5926 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5927 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5928 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5929 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5930 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5931 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5932 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5933 } },
5934 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5935 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5936 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5937 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5938 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5939 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5940 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5941 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5942 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5943 } },
5944 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5945 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5946 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5947 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5948 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5949 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5950 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5951 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5952 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5953 } },
5954 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5955 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5956 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5957 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5958 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5959 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5960 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5961 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
5962 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5963 } },
5964 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5965 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5966 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5967 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5968 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5969 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5970 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5971 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5972 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5973 } },
5974 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5975 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5976 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5977 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5978 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5979 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5980 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5981 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5982 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5983 } },
5984 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5985 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5986 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5987 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5988 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5989 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5990 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5991 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5992 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5993 } },
5994 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5995 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5996 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5997 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5998 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5999 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6000 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
6001 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
6002 } },
6003 { },
6004 };
6005
6006 enum ioctrl_regs {
6007 POCCTRL,
6008 TDSELCTRL,
6009 };
6010
6011 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6012 [POCCTRL] = { 0xe6060380, },
6013 [TDSELCTRL] = { 0xe60603c0, },
6014 { /* sentinel */ },
6015 };
6016
6017 static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
6018 unsigned int pin, u32 *pocctrl)
6019 {
6020 int bit = -EINVAL;
6021
6022 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6023
6024 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6025 bit = pin & 0x1f;
6026
6027 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6028 bit = (pin & 0x1f) + 12;
6029
6030 return bit;
6031 }
6032
6033 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6034 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6035 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6036 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6037 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6038 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6039 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6040 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6041 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6042 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6043 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6044 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6045 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6046 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6047 [12] = PIN_RPC_INT_N, /* RPC_INT# */
6048 [13] = PIN_RPC_WP_N, /* RPC_WP# */
6049 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6050 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6051 [16] = PIN_AVB_RXC, /* AVB_RXC */
6052 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6053 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6054 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6055 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6056 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6057 [22] = PIN_AVB_TXC, /* AVB_TXC */
6058 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6059 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6060 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6061 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6062 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6063 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
6064 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6065 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6066 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6067 } },
6068 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6069 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6070 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6071 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6072 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6073 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6074 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6075 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6076 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6077 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6078 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6079 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6080 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6081 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6082 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6083 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6084 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6085 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6086 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6087 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6088 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6089 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6090 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6091 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6092 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6093 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6094 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6095 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6096 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6097 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6098 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6099 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6100 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6101 } },
6102 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6103 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6104 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6105 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6106 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6107 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6108 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6109 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6110 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6111 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6112 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
6113 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6114 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6115 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6116 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6117 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6118 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6119 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6120 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6121 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6122 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6123 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6124 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6125 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6126 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6127 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6128 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6129 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6130 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6131 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6132 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6133 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6134 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
6135 } },
6136 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6137 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6138 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6139 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
6140 [ 3] = PIN_EXTALR, /* EXTALR*/
6141 [ 4] = PIN_TRST_N, /* TRST# */
6142 [ 5] = PIN_TCK, /* TCK */
6143 [ 6] = PIN_TMS, /* TMS */
6144 [ 7] = PIN_TDI, /* TDI */
6145 [ 8] = SH_PFC_PIN_NONE,
6146 [ 9] = PIN_ASEBRK, /* ASEBRK */
6147 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6148 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6149 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6150 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6151 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6152 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6153 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6154 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6155 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6156 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6157 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6158 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6159 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6160 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6161 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6162 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6163 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6164 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6165 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6166 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6167 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6168 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6169 } },
6170 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6171 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6172 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6173 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6174 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6175 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6176 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6177 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6178 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6179 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6180 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6181 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6182 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6183 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6184 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6185 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6186 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6187 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6188 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6189 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6190 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6191 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6192 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6193 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6194 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6195 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6196 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6197 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6198 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6199 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6200 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6201 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6202 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6203 } },
6204 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6205 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6206 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6207 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6208 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6209 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6210 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6211 [ 6] = PIN_MLB_REF, /* MLB_REF */
6212 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6213 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6214 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6215 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6216 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6217 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6218 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6219 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6220 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6221 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6222 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6223 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6224 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6225 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6226 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6227 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6228 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6229 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6230 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6231 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6232 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6233 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6234 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6235 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6236 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6237 } },
6238 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6239 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6240 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6241 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6242 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6243 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6244 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6245 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6246 [ 7] = SH_PFC_PIN_NONE,
6247 [ 8] = SH_PFC_PIN_NONE,
6248 [ 9] = SH_PFC_PIN_NONE,
6249 [10] = SH_PFC_PIN_NONE,
6250 [11] = SH_PFC_PIN_NONE,
6251 [12] = SH_PFC_PIN_NONE,
6252 [13] = SH_PFC_PIN_NONE,
6253 [14] = SH_PFC_PIN_NONE,
6254 [15] = SH_PFC_PIN_NONE,
6255 [16] = SH_PFC_PIN_NONE,
6256 [17] = SH_PFC_PIN_NONE,
6257 [18] = SH_PFC_PIN_NONE,
6258 [19] = SH_PFC_PIN_NONE,
6259 [20] = SH_PFC_PIN_NONE,
6260 [21] = SH_PFC_PIN_NONE,
6261 [22] = SH_PFC_PIN_NONE,
6262 [23] = SH_PFC_PIN_NONE,
6263 [24] = SH_PFC_PIN_NONE,
6264 [25] = SH_PFC_PIN_NONE,
6265 [26] = SH_PFC_PIN_NONE,
6266 [27] = SH_PFC_PIN_NONE,
6267 [28] = SH_PFC_PIN_NONE,
6268 [29] = SH_PFC_PIN_NONE,
6269 [30] = SH_PFC_PIN_NONE,
6270 [31] = SH_PFC_PIN_NONE,
6271 } },
6272 { /* sentinel */ },
6273 };
6274
6275 static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
6276 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
6277 .get_bias = rcar_pinmux_get_bias,
6278 .set_bias = rcar_pinmux_set_bias,
6279 };
6280
6281 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
6282 const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6283 .name = "r8a774e1_pfc",
6284 .ops = &r8a77951_pinmux_ops,
6285 .unlock_reg = 0xe6060000, /* PMMR */
6286
6287 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6288
6289 .pins = pinmux_pins,
6290 .nr_pins = ARRAY_SIZE(pinmux_pins),
6291 .groups = pinmux_groups.common,
6292 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6293 .functions = pinmux_functions.common,
6294 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6295
6296 .cfg_regs = pinmux_config_regs,
6297 .drive_regs = pinmux_drive_regs,
6298 .bias_regs = pinmux_bias_regs,
6299 .ioctrl_regs = pinmux_ioctrl_regs,
6300
6301 .pinmux_data = pinmux_data,
6302 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6303 };
6304 #endif
6305
6306 #ifdef CONFIG_PINCTRL_PFC_R8A77951
6307 const struct sh_pfc_soc_info r8a77951_pinmux_info = {
6308 .name = "r8a77951_pfc",
6309 .ops = &r8a77951_pinmux_ops,
6310 .unlock_reg = 0xe6060000, /* PMMR */
6311
6312 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6313
6314 .pins = pinmux_pins,
6315 .nr_pins = ARRAY_SIZE(pinmux_pins),
6316 .groups = pinmux_groups.common,
6317 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6318 ARRAY_SIZE(pinmux_groups.automotive),
6319 .functions = pinmux_functions.common,
6320 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6321 ARRAY_SIZE(pinmux_functions.automotive),
6322
6323 .cfg_regs = pinmux_config_regs,
6324 .drive_regs = pinmux_drive_regs,
6325 .bias_regs = pinmux_bias_regs,
6326 .ioctrl_regs = pinmux_ioctrl_regs,
6327
6328 .pinmux_data = pinmux_data,
6329 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6330 };
6331 #endif
Linux with added FPC-III support