drivers/pinctrl/renesas/pinctrl-rza2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
   4  *
   5  * Copyright (C) 2018 Chris Brandt
   6  */
   7
   8 /*
   9  * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
  10  * family.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/pinctrl/pinmux.h>
  19
  20 #include "../core.h"
  21 #include "../pinmux.h"
  22
  23 #define DRIVER_NAME             "pinctrl-rza2"
  24
  25 #define RZA2_PINS_PER_PORT      8
  26 #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
  27 #define RZA2_PIN_ID_TO_PIN(id)  ((id) % RZA2_PINS_PER_PORT)
  28
  29 /*
  30  * Use 16 lower bits [15:0] for pin identifier
  31  * Use 16 higher bits [31:16] for pin mux function
  32  */
  33 #define MUX_PIN_ID_MASK         GENMASK(15, 0)
  34 #define MUX_FUNC_MASK           GENMASK(31, 16)
  35 #define MUX_FUNC_OFFS           16
  36 #define MUX_FUNC(pinconf)       ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  37
  38 static const char port_names[] = "0123456789ABCDEFGHJKLM";
  39
  40 struct rza2_pinctrl_priv {
  41         struct device *dev;
  42         void __iomem *base;
  43
  44         struct pinctrl_pin_desc *pins;
  45         struct pinctrl_desc desc;
  46         struct pinctrl_dev *pctl;
  47         struct pinctrl_gpio_range gpio_range;
  48         int npins;
  49 };
  50
  51 #define RZA2_PDR(port)          (0x0000 + (port) * 2)   /* Direction 16-bit */
  52 #define RZA2_PODR(port)         (0x0040 + (port))       /* Output Data 8-bit */
  53 #define RZA2_PIDR(port)         (0x0060 + (port))       /* Input Data 8-bit */
  54 #define RZA2_PMR(port)          (0x0080 + (port))       /* Mode 8-bit */
  55 #define RZA2_DSCR(port)         (0x0140 + (port) * 2)   /* Drive 16-bit */
  56 #define RZA2_PFS(port, pin)     (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
  57
  58 #define RZA2_PWPR               0x02ff  /* Write Protect 8-bit */
  59 #define RZA2_PFENET             0x0820  /* Ethernet Pins 8-bit */
  60 #define RZA2_PPOC               0x0900  /* Dedicated Pins 32-bit */
  61 #define RZA2_PHMOMO             0x0980  /* Peripheral Pins 32-bit */
  62 #define RZA2_PCKIO              0x09d0  /* CKIO Drive 8-bit */
  63
  64 #define RZA2_PDR_INPUT          0x02
  65 #define RZA2_PDR_OUTPUT         0x03
  66 #define RZA2_PDR_MASK           0x03
  67
  68 #define PWPR_B0WI               BIT(7)  /* Bit Write Disable */
  69 #define PWPR_PFSWE              BIT(6)  /* PFS Register Write Enable */
  70 #define PFS_ISEL                BIT(6)  /* Interrupt Select */
  71
  72 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
  73                                   u8 func)
  74 {
  75         u16 mask16;
  76         u16 reg16;
  77         u8 reg8;
  78
  79         /* Set pin to 'Non-use (Hi-z input protection)'  */
  80         reg16 = readw(pfc_base + RZA2_PDR(port));
  81         mask16 = RZA2_PDR_MASK << (pin * 2);
  82         reg16 &= ~mask16;
  83         writew(reg16, pfc_base + RZA2_PDR(port));
  84
  85         /* Temporarily switch to GPIO */
  86         reg8 = readb(pfc_base + RZA2_PMR(port));
  87         reg8 &= ~BIT(pin);
  88         writeb(reg8, pfc_base + RZA2_PMR(port));
  89
  90         /* PFS Register Write Protect : OFF */
  91         writeb(0x00, pfc_base + RZA2_PWPR);             /* B0WI=0, PFSWE=0 */
  92         writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR);       /* B0WI=0, PFSWE=1 */
  93
  94         /* Set Pin function (interrupt disabled, ISEL=0) */
  95         writeb(func, pfc_base + RZA2_PFS(port, pin));
  96
  97         /* PFS Register Write Protect : ON */
  98         writeb(0x00, pfc_base + RZA2_PWPR);     /* B0WI=0, PFSWE=0 */
  99         writeb(0x80, pfc_base + RZA2_PWPR);     /* B0WI=1, PFSWE=0 */
 100
 101         /* Port Mode  : Peripheral module pin functions */
 102         reg8 = readb(pfc_base + RZA2_PMR(port));
 103         reg8 |= BIT(pin);
 104         writeb(reg8, pfc_base + RZA2_PMR(port));
 105 }
 106
 107 static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
 108                              u8 dir)
 109 {
 110         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 111         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 112         u16 mask16;
 113         u16 reg16;
 114
 115         reg16 = readw(pfc_base + RZA2_PDR(port));
 116         mask16 = RZA2_PDR_MASK << (pin * 2);
 117         reg16 &= ~mask16;
 118
 119         if (dir)
 120                 reg16 |= RZA2_PDR_INPUT << (pin * 2);   /* pin as input */
 121         else
 122                 reg16 |= RZA2_PDR_OUTPUT << (pin * 2);  /* pin as output */
 123
 124         writew(reg16, pfc_base + RZA2_PDR(port));
 125 }
 126
 127 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
 128 {
 129         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 130         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 131         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 132         u16 reg16;
 133
 134         reg16 = readw(priv->base + RZA2_PDR(port));
 135         reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
 136
 137         if (reg16 == RZA2_PDR_OUTPUT)
 138                 return GPIO_LINE_DIRECTION_OUT;
 139
 140         if (reg16 == RZA2_PDR_INPUT)
 141                 return GPIO_LINE_DIRECTION_IN;
 142
 143         /*
 144          * This GPIO controller has a default Hi-Z state that is not input or
 145          * output, so force the pin to input now.
 146          */
 147         rza2_pin_to_gpio(priv->base, offset, 1);
 148
 149         return GPIO_LINE_DIRECTION_IN;
 150 }
 151
 152 static int rza2_chip_direction_input(struct gpio_chip *chip,
 153                                      unsigned int offset)
 154 {
 155         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 156
 157         rza2_pin_to_gpio(priv->base, offset, 1);
 158
 159         return 0;
 160 }
 161
 162 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
 163 {
 164         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 165         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 166         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 167
 168         return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
 169 }
 170
 171 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
 172                           int value)
 173 {
 174         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 175         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 176         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 177         u8 new_value;
 178
 179         new_value = readb(priv->base + RZA2_PODR(port));
 180
 181         if (value)
 182                 new_value |= BIT(pin);
 183         else
 184                 new_value &= ~BIT(pin);
 185
 186         writeb(new_value, priv->base + RZA2_PODR(port));
 187 }
 188
 189 static int rza2_chip_direction_output(struct gpio_chip *chip,
 190                                       unsigned int offset, int val)
 191 {
 192         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 193
 194         rza2_chip_set(chip, offset, val);
 195         rza2_pin_to_gpio(priv->base, offset, 0);
 196
 197         return 0;
 198 }
 199
 200 static const char * const rza2_gpio_names[] = {
 201         "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
 202         "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
 203         "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
 204         "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
 205         "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
 206         "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
 207         "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
 208         "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
 209         "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
 210         "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
 211         "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
 212         "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
 213         "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
 214         "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
 215         "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
 216         "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
 217         "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
 218         "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
 219         /* port I does not exist */
 220         "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
 221         "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
 222         "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
 223         "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
 224 };
 225
 226 static struct gpio_chip chip = {
 227         .names = rza2_gpio_names,
 228         .base = -1,
 229         .get_direction = rza2_chip_get_direction,
 230         .direction_input = rza2_chip_direction_input,
 231         .direction_output = rza2_chip_direction_output,
 232         .get = rza2_chip_get,
 233         .set = rza2_chip_set,
 234 };
 235
 236 static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
 237 {
 238         struct device_node *np = priv->dev->of_node;
 239         struct of_phandle_args of_args;
 240         int ret;
 241
 242         chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
 243         chip.of_node = np;
 244         chip.parent = priv->dev;
 245         chip.ngpio = priv->npins;
 246
 247         ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
 248                                                &of_args);
 249         if (ret) {
 250                 dev_err(priv->dev, "Unable to parse gpio-ranges\n");
 251                 return ret;
 252         }
 253
 254         if ((of_args.args[0] != 0) ||
 255             (of_args.args[1] != 0) ||
 256             (of_args.args[2] != priv->npins)) {
 257                 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
 258                 return -EINVAL;
 259         }
 260         priv->gpio_range.id = 0;
 261         priv->gpio_range.pin_base = priv->gpio_range.base = 0;
 262         priv->gpio_range.npins = priv->npins;
 263         priv->gpio_range.name = chip.label;
 264         priv->gpio_range.gc = &chip;
 265
 266         /* Register our gpio chip with gpiolib */
 267         ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
 268         if (ret)
 269                 return ret;
 270
 271         /* Register pin range with pinctrl core */
 272         pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
 273
 274         dev_dbg(priv->dev, "Registered gpio controller\n");
 275
 276         return 0;
 277 }
 278
 279 static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
 280 {
 281         struct pinctrl_pin_desc *pins;
 282         unsigned int i;
 283         int ret;
 284
 285         pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
 286         if (!pins)
 287                 return -ENOMEM;
 288
 289         priv->pins = pins;
 290         priv->desc.pins = pins;
 291         priv->desc.npins = priv->npins;
 292
 293         for (i = 0; i < priv->npins; i++) {
 294                 pins[i].number = i;
 295                 pins[i].name = rza2_gpio_names[i];
 296         }
 297
 298         ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
 299                                              &priv->pctl);
 300         if (ret) {
 301                 dev_err(priv->dev, "pinctrl registration failed\n");
 302                 return ret;
 303         }
 304
 305         ret = pinctrl_enable(priv->pctl);
 306         if (ret) {
 307                 dev_err(priv->dev, "pinctrl enable failed\n");
 308                 return ret;
 309         }
 310
 311         ret = rza2_gpio_register(priv);
 312         if (ret) {
 313                 dev_err(priv->dev, "GPIO registration failed\n");
 314                 return ret;
 315         }
 316
 317         return 0;
 318 }
 319
 320 /*
 321  * For each DT node, create a single pin mapping. That pin mapping will only
 322  * contain a single group of pins, and that group of pins will only have a
 323  * single function that can be selected.
 324  */
 325 static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
 326                                struct device_node *np,
 327                                struct pinctrl_map **map,
 328                                unsigned int *num_maps)
 329 {
 330         struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 331         unsigned int *pins, *psel_val;
 332         int i, ret, npins, gsel, fsel;
 333         struct property *of_pins;
 334         const char **pin_fn;
 335
 336         /* Find out how many pins to map */
 337         of_pins = of_find_property(np, "pinmux", NULL);
 338         if (!of_pins) {
 339                 dev_info(priv->dev, "Missing pinmux property\n");
 340                 return -ENOENT;
 341         }
 342         npins = of_pins->length / sizeof(u32);
 343
 344         pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
 345         psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
 346                                 GFP_KERNEL);
 347         pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
 348         if (!pins || !psel_val || !pin_fn)
 349                 return -ENOMEM;
 350
 351         /* Collect pin locations and mux settings from DT properties */
 352         for (i = 0; i < npins; ++i) {
 353                 u32 value;
 354
 355                 ret = of_property_read_u32_index(np, "pinmux", i, &value);
 356                 if (ret)
 357                         return ret;
 358                 pins[i] = value & MUX_PIN_ID_MASK;
 359                 psel_val[i] = MUX_FUNC(value);
 360         }
 361
 362         /* Register a single pin group listing all the pins we read from DT */
 363         gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
 364         if (gsel < 0)
 365                 return gsel;
 366
 367         /*
 368          * Register a single group function where the 'data' is an array PSEL
 369          * register values read from DT.
 370          */
 371         pin_fn[0] = np->name;
 372         fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
 373                                            psel_val);
 374         if (fsel < 0) {
 375                 ret = fsel;
 376                 goto remove_group;
 377         }
 378
 379         dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
 380
 381         /* Create map where to retrieve function and mux settings from */
 382         *num_maps = 0;
 383         *map = kzalloc(sizeof(**map), GFP_KERNEL);
 384         if (!*map) {
 385                 ret = -ENOMEM;
 386                 goto remove_function;
 387         }
 388
 389         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
 390         (*map)->data.mux.group = np->name;
 391         (*map)->data.mux.function = np->name;
 392         *num_maps = 1;
 393
 394         return 0;
 395
 396 remove_function:
 397         pinmux_generic_remove_function(pctldev, fsel);
 398
 399 remove_group:
 400         pinctrl_generic_remove_group(pctldev, gsel);
 401
 402         dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
 403
 404         return ret;
 405 }
 406
 407 static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
 408                              struct pinctrl_map *map, unsigned int num_maps)
 409 {
 410         kfree(map);
 411 }
 412
 413 static const struct pinctrl_ops rza2_pinctrl_ops = {
 414         .get_groups_count       = pinctrl_generic_get_group_count,
 415         .get_group_name         = pinctrl_generic_get_group_name,
 416         .get_group_pins         = pinctrl_generic_get_group_pins,
 417         .dt_node_to_map         = rza2_dt_node_to_map,
 418         .dt_free_map            = rza2_dt_free_map,
 419 };
 420
 421 static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 422                         unsigned int group)
 423 {
 424         struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 425         struct function_desc *func;
 426         unsigned int i, *psel_val;
 427         struct group_desc *grp;
 428
 429         grp = pinctrl_generic_get_group(pctldev, group);
 430         if (!grp)
 431                 return -EINVAL;
 432
 433         func = pinmux_generic_get_function(pctldev, selector);
 434         if (!func)
 435                 return -EINVAL;
 436
 437         psel_val = func->data;
 438
 439         for (i = 0; i < grp->num_pins; ++i) {
 440                 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
 441                         port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
 442                         RZA2_PIN_ID_TO_PIN(grp->pins[i]),
 443                         psel_val[i]);
 444                 rza2_set_pin_function(
 445                         priv->base,
 446                         RZA2_PIN_ID_TO_PORT(grp->pins[i]),
 447                         RZA2_PIN_ID_TO_PIN(grp->pins[i]),
 448                         psel_val[i]);
 449         }
 450
 451         return 0;
 452 }
 453
 454 static const struct pinmux_ops rza2_pinmux_ops = {
 455         .get_functions_count    = pinmux_generic_get_function_count,
 456         .get_function_name      = pinmux_generic_get_function_name,
 457         .get_function_groups    = pinmux_generic_get_function_groups,
 458         .set_mux                = rza2_set_mux,
 459         .strict                 = true,
 460 };
 461
 462 static int rza2_pinctrl_probe(struct platform_device *pdev)
 463 {
 464         struct rza2_pinctrl_priv *priv;
 465         int ret;
 466
 467         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 468         if (!priv)
 469                 return -ENOMEM;
 470
 471         priv->dev = &pdev->dev;
 472
 473         priv->base = devm_platform_ioremap_resource(pdev, 0);
 474         if (IS_ERR(priv->base))
 475                 return PTR_ERR(priv->base);
 476
 477         platform_set_drvdata(pdev, priv);
 478
 479         priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
 480                       RZA2_PINS_PER_PORT;
 481
 482         priv->desc.name         = DRIVER_NAME;
 483         priv->desc.pctlops      = &rza2_pinctrl_ops;
 484         priv->desc.pmxops       = &rza2_pinmux_ops;
 485         priv->desc.owner        = THIS_MODULE;
 486
 487         ret = rza2_pinctrl_register(priv);
 488         if (ret)
 489                 return ret;
 490
 491         dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
 492                  port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
 493
 494         return 0;
 495 }
 496
 497 static const struct of_device_id rza2_pinctrl_of_match[] = {
 498         { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
 499         { /* sentinel */ }
 500 };
 501
 502 static struct platform_driver rza2_pinctrl_driver = {
 503         .driver = {
 504                 .name = DRIVER_NAME,
 505                 .of_match_table = rza2_pinctrl_of_match,
 506         },
 507         .probe = rza2_pinctrl_probe,
 508 };
 509
 510 static int __init rza2_pinctrl_init(void)
 511 {
 512         return platform_driver_register(&rza2_pinctrl_driver);
 513 }
 514 core_initcall(rza2_pinctrl_init);
 515
 516 MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
 517 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
 518 MODULE_LICENSE("GPL v2");