drivers/scsi/aic7xxx/aic79xx_reg.h_shipped

   1 /*
   2  * DO NOT EDIT - This file is automatically generated
   3  *               from the following source files:
   4  *
   5  * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
   6  * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
   7  */
   8 typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);
   9 typedef struct ahd_reg_parse_entry {
  10         char    *name;
  11         uint8_t  value;
  12         uint8_t  mask;
  13 } ahd_reg_parse_entry_t;
  14
  15 #if AIC_DEBUG_REGISTERS
  16 ahd_reg_print_t ahd_intstat_print;
  17 #else
  18 #define ahd_intstat_print(regvalue, cur_col, wrap) \
  19     ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
  20 #endif
  21
  22 #if AIC_DEBUG_REGISTERS
  23 ahd_reg_print_t ahd_hs_mailbox_print;
  24 #else
  25 #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
  26     ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
  27 #endif
  28
  29 #if AIC_DEBUG_REGISTERS
  30 ahd_reg_print_t ahd_seqintstat_print;
  31 #else
  32 #define ahd_seqintstat_print(regvalue, cur_col, wrap) \
  33     ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
  34 #endif
  35
  36 #if AIC_DEBUG_REGISTERS
  37 ahd_reg_print_t ahd_intctl_print;
  38 #else
  39 #define ahd_intctl_print(regvalue, cur_col, wrap) \
  40     ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
  41 #endif
  42
  43 #if AIC_DEBUG_REGISTERS
  44 ahd_reg_print_t ahd_dfcntrl_print;
  45 #else
  46 #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
  47     ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
  48 #endif
  49
  50 #if AIC_DEBUG_REGISTERS
  51 ahd_reg_print_t ahd_dfstatus_print;
  52 #else
  53 #define ahd_dfstatus_print(regvalue, cur_col, wrap) \
  54     ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
  55 #endif
  56
  57 #if AIC_DEBUG_REGISTERS
  58 ahd_reg_print_t ahd_sg_cache_shadow_print;
  59 #else
  60 #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
  61     ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
  62 #endif
  63
  64 #if AIC_DEBUG_REGISTERS
  65 ahd_reg_print_t ahd_scsiseq0_print;
  66 #else
  67 #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
  68     ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
  69 #endif
  70
  71 #if AIC_DEBUG_REGISTERS
  72 ahd_reg_print_t ahd_scsiseq1_print;
  73 #else
  74 #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \
  75     ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
  76 #endif
  77
  78 #if AIC_DEBUG_REGISTERS
  79 ahd_reg_print_t ahd_dffstat_print;
  80 #else
  81 #define ahd_dffstat_print(regvalue, cur_col, wrap) \
  82     ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
  83 #endif
  84
  85 #if AIC_DEBUG_REGISTERS
  86 ahd_reg_print_t ahd_scsisigi_print;
  87 #else
  88 #define ahd_scsisigi_print(regvalue, cur_col, wrap) \
  89     ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)
  90 #endif
  91
  92 #if AIC_DEBUG_REGISTERS
  93 ahd_reg_print_t ahd_scsiphase_print;
  94 #else
  95 #define ahd_scsiphase_print(regvalue, cur_col, wrap) \
  96     ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)
  97 #endif
  98
  99 #if AIC_DEBUG_REGISTERS
 100 ahd_reg_print_t ahd_scsibus_print;
 101 #else
 102 #define ahd_scsibus_print(regvalue, cur_col, wrap) \
 103     ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)
 104 #endif
 105
 106 #if AIC_DEBUG_REGISTERS
 107 ahd_reg_print_t ahd_selid_print;
 108 #else
 109 #define ahd_selid_print(regvalue, cur_col, wrap) \
 110     ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)
 111 #endif
 112
 113 #if AIC_DEBUG_REGISTERS
 114 ahd_reg_print_t ahd_simode0_print;
 115 #else
 116 #define ahd_simode0_print(regvalue, cur_col, wrap) \
 117     ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)
 118 #endif
 119
 120 #if AIC_DEBUG_REGISTERS
 121 ahd_reg_print_t ahd_sstat0_print;
 122 #else
 123 #define ahd_sstat0_print(regvalue, cur_col, wrap) \
 124     ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)
 125 #endif
 126
 127 #if AIC_DEBUG_REGISTERS
 128 ahd_reg_print_t ahd_sstat1_print;
 129 #else
 130 #define ahd_sstat1_print(regvalue, cur_col, wrap) \
 131     ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)
 132 #endif
 133
 134 #if AIC_DEBUG_REGISTERS
 135 ahd_reg_print_t ahd_sstat2_print;
 136 #else
 137 #define ahd_sstat2_print(regvalue, cur_col, wrap) \
 138     ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
 139 #endif
 140
 141 #if AIC_DEBUG_REGISTERS
 142 ahd_reg_print_t ahd_perrdiag_print;
 143 #else
 144 #define ahd_perrdiag_print(regvalue, cur_col, wrap) \
 145     ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
 146 #endif
 147
 148 #if AIC_DEBUG_REGISTERS
 149 ahd_reg_print_t ahd_soffcnt_print;
 150 #else
 151 #define ahd_soffcnt_print(regvalue, cur_col, wrap) \
 152     ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)
 153 #endif
 154
 155 #if AIC_DEBUG_REGISTERS
 156 ahd_reg_print_t ahd_lqistat0_print;
 157 #else
 158 #define ahd_lqistat0_print(regvalue, cur_col, wrap) \
 159     ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)
 160 #endif
 161
 162 #if AIC_DEBUG_REGISTERS
 163 ahd_reg_print_t ahd_lqistat1_print;
 164 #else
 165 #define ahd_lqistat1_print(regvalue, cur_col, wrap) \
 166     ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)
 167 #endif
 168
 169 #if AIC_DEBUG_REGISTERS
 170 ahd_reg_print_t ahd_lqistat2_print;
 171 #else
 172 #define ahd_lqistat2_print(regvalue, cur_col, wrap) \
 173     ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)
 174 #endif
 175
 176 #if AIC_DEBUG_REGISTERS
 177 ahd_reg_print_t ahd_sstat3_print;
 178 #else
 179 #define ahd_sstat3_print(regvalue, cur_col, wrap) \
 180     ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)
 181 #endif
 182
 183 #if AIC_DEBUG_REGISTERS
 184 ahd_reg_print_t ahd_lqostat0_print;
 185 #else
 186 #define ahd_lqostat0_print(regvalue, cur_col, wrap) \
 187     ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)
 188 #endif
 189
 190 #if AIC_DEBUG_REGISTERS
 191 ahd_reg_print_t ahd_lqostat1_print;
 192 #else
 193 #define ahd_lqostat1_print(regvalue, cur_col, wrap) \
 194     ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)
 195 #endif
 196
 197 #if AIC_DEBUG_REGISTERS
 198 ahd_reg_print_t ahd_lqostat2_print;
 199 #else
 200 #define ahd_lqostat2_print(regvalue, cur_col, wrap) \
 201     ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)
 202 #endif
 203
 204 #if AIC_DEBUG_REGISTERS
 205 ahd_reg_print_t ahd_simode1_print;
 206 #else
 207 #define ahd_simode1_print(regvalue, cur_col, wrap) \
 208     ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)
 209 #endif
 210
 211 #if AIC_DEBUG_REGISTERS
 212 ahd_reg_print_t ahd_dffsxfrctl_print;
 213 #else
 214 #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
 215     ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
 216 #endif
 217
 218 #if AIC_DEBUG_REGISTERS
 219 ahd_reg_print_t ahd_seqintsrc_print;
 220 #else
 221 #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \
 222     ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)
 223 #endif
 224
 225 #if AIC_DEBUG_REGISTERS
 226 ahd_reg_print_t ahd_seqimode_print;
 227 #else
 228 #define ahd_seqimode_print(regvalue, cur_col, wrap) \
 229     ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
 230 #endif
 231
 232 #if AIC_DEBUG_REGISTERS
 233 ahd_reg_print_t ahd_mdffstat_print;
 234 #else
 235 #define ahd_mdffstat_print(regvalue, cur_col, wrap) \
 236     ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
 237 #endif
 238
 239 #if AIC_DEBUG_REGISTERS
 240 ahd_reg_print_t ahd_seloid_print;
 241 #else
 242 #define ahd_seloid_print(regvalue, cur_col, wrap) \
 243     ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)
 244 #endif
 245
 246 #if AIC_DEBUG_REGISTERS
 247 ahd_reg_print_t ahd_sg_state_print;
 248 #else
 249 #define ahd_sg_state_print(regvalue, cur_col, wrap) \
 250     ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)
 251 #endif
 252
 253 #if AIC_DEBUG_REGISTERS
 254 ahd_reg_print_t ahd_ccscbctl_print;
 255 #else
 256 #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
 257     ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)
 258 #endif
 259
 260 #if AIC_DEBUG_REGISTERS
 261 ahd_reg_print_t ahd_ccsgctl_print;
 262 #else
 263 #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \
 264     ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)
 265 #endif
 266
 267 #if AIC_DEBUG_REGISTERS
 268 ahd_reg_print_t ahd_seqctl0_print;
 269 #else
 270 #define ahd_seqctl0_print(regvalue, cur_col, wrap) \
 271     ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)
 272 #endif
 273
 274 #if AIC_DEBUG_REGISTERS
 275 ahd_reg_print_t ahd_seqintctl_print;
 276 #else
 277 #define ahd_seqintctl_print(regvalue, cur_col, wrap) \
 278     ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)
 279 #endif
 280
 281 #if AIC_DEBUG_REGISTERS
 282 ahd_reg_print_t ahd_sram_base_print;
 283 #else
 284 #define ahd_sram_base_print(regvalue, cur_col, wrap) \
 285     ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
 286 #endif
 287
 288 #if AIC_DEBUG_REGISTERS
 289 ahd_reg_print_t ahd_qfreeze_count_print;
 290 #else
 291 #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \
 292     ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap)
 293 #endif
 294
 295 #if AIC_DEBUG_REGISTERS
 296 ahd_reg_print_t ahd_kernel_qfreeze_count_print;
 297 #else
 298 #define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \
 299     ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap)
 300 #endif
 301
 302 #if AIC_DEBUG_REGISTERS
 303 ahd_reg_print_t ahd_saved_mode_print;
 304 #else
 305 #define ahd_saved_mode_print(regvalue, cur_col, wrap) \
 306     ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap)
 307 #endif
 308
 309 #if AIC_DEBUG_REGISTERS
 310 ahd_reg_print_t ahd_seq_flags_print;
 311 #else
 312 #define ahd_seq_flags_print(regvalue, cur_col, wrap) \
 313     ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap)
 314 #endif
 315
 316 #if AIC_DEBUG_REGISTERS
 317 ahd_reg_print_t ahd_lastphase_print;
 318 #else
 319 #define ahd_lastphase_print(regvalue, cur_col, wrap) \
 320     ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap)
 321 #endif
 322
 323 #if AIC_DEBUG_REGISTERS
 324 ahd_reg_print_t ahd_seq_flags2_print;
 325 #else
 326 #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \
 327     ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap)
 328 #endif
 329
 330 #if AIC_DEBUG_REGISTERS
 331 ahd_reg_print_t ahd_mk_message_scb_print;
 332 #else
 333 #define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \
 334     ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap)
 335 #endif
 336
 337 #if AIC_DEBUG_REGISTERS
 338 ahd_reg_print_t ahd_mk_message_scsiid_print;
 339 #else
 340 #define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \
 341     ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap)
 342 #endif
 343
 344 #if AIC_DEBUG_REGISTERS
 345 ahd_reg_print_t ahd_scb_base_print;
 346 #else
 347 #define ahd_scb_base_print(regvalue, cur_col, wrap) \
 348     ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
 349 #endif
 350
 351 #if AIC_DEBUG_REGISTERS
 352 ahd_reg_print_t ahd_scb_control_print;
 353 #else
 354 #define ahd_scb_control_print(regvalue, cur_col, wrap) \
 355     ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)
 356 #endif
 357
 358 #if AIC_DEBUG_REGISTERS
 359 ahd_reg_print_t ahd_scb_scsiid_print;
 360 #else
 361 #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \
 362     ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)
 363 #endif
 364
 365
 366 #define MODE_PTR                        0x00
 367 #define         DST_MODE                0x70
 368 #define         SRC_MODE                0x07
 369
 370 #define INTSTAT                         0x01
 371 #define         INT_PEND                0xff
 372 #define         HWERRINT                0x80
 373 #define         BRKADRINT               0x40
 374 #define         SWTMINT                 0x20
 375 #define         PCIINT                  0x10
 376 #define         SCSIINT                 0x08
 377 #define         SEQINT                  0x04
 378 #define         CMDCMPLT                0x02
 379 #define         SPLTINT                 0x01
 380
 381 #define SEQINTCODE                      0x02
 382 #define         BAD_SCB_STATUS          0x1a
 383 #define         SAW_HWERR               0x19
 384 #define         TRACEPOINT3             0x18
 385 #define         TRACEPOINT2             0x17
 386 #define         TRACEPOINT1             0x16
 387 #define         TRACEPOINT0             0x15
 388 #define         TASKMGMT_CMD_CMPLT_OKAY 0x14
 389 #define         TASKMGMT_FUNC_COMPLETE  0x13
 390 #define         ENTERING_NONPACK        0x12
 391 #define         CFG4OVERRUN             0x11
 392 #define         STATUS_OVERRUN          0x10
 393 #define         CFG4ISTAT_INTR          0x0f
 394 #define         INVALID_SEQINT          0x0e
 395 #define         ILLEGAL_PHASE           0x0d
 396 #define         DUMP_CARD_STATE         0x0c
 397 #define         MISSED_BUSFREE          0x0b
 398 #define         MKMSG_FAILED            0x0a
 399 #define         DATA_OVERRUN            0x09
 400 #define         BAD_STATUS              0x08
 401 #define         HOST_MSG_LOOP           0x07
 402 #define         PDATA_REINIT            0x06
 403 #define         IGN_WIDE_RES            0x05
 404 #define         NO_MATCH                0x04
 405 #define         PROTO_VIOLATION         0x03
 406 #define         SEND_REJECT             0x02
 407 #define         BAD_PHASE               0x01
 408 #define         NO_SEQINT               0x00
 409
 410 #define CLRINT                          0x03
 411 #define         CLRHWERRINT             0x80
 412 #define         CLRBRKADRINT            0x40
 413 #define         CLRSWTMINT              0x20
 414 #define         CLRPCIINT               0x10
 415 #define         CLRSCSIINT              0x08
 416 #define         CLRSEQINT               0x04
 417 #define         CLRCMDINT               0x02
 418 #define         CLRSPLTINT              0x01
 419
 420 #define CLRERR                          0x04
 421 #define         CLRCIOPARERR            0x80
 422 #define         CLRCIOACCESFAIL         0x40
 423 #define         CLRMPARERR              0x20
 424 #define         CLRDPARERR              0x10
 425 #define         CLRSQPARERR             0x08
 426 #define         CLRILLOPCODE            0x04
 427 #define         CLRDSCTMOUT             0x02
 428
 429 #define ERROR                           0x04
 430 #define         CIOPARERR               0x80
 431 #define         CIOACCESFAIL            0x40
 432 #define         MPARERR                 0x20
 433 #define         DPARERR                 0x10
 434 #define         SQPARERR                0x08
 435 #define         ILLOPCODE               0x04
 436 #define         DSCTMOUT                0x02
 437
 438 #define HCNTRL                          0x05
 439 #define         SEQ_RESET               0x80
 440 #define         POWRDN                  0x40
 441 #define         SWINT                   0x10
 442 #define         SWTIMER_START_B         0x08
 443 #define         PAUSE                   0x04
 444 #define         INTEN                   0x02
 445 #define         CHIPRST                 0x01
 446 #define         CHIPRSTACK              0x01
 447
 448 #define HNSCB_QOFF                      0x06
 449
 450 #define HESCB_QOFF                      0x08
 451
 452 #define HS_MAILBOX                      0x0b
 453 #define         HOST_TQINPOS            0x80
 454 #define         ENINT_COALESCE          0x40
 455
 456 #define SEQINTSTAT                      0x0c
 457 #define         SEQ_SWTMRTO             0x10
 458 #define         SEQ_SEQINT              0x08
 459 #define         SEQ_SCSIINT             0x04
 460 #define         SEQ_PCIINT              0x02
 461 #define         SEQ_SPLTINT             0x01
 462
 463 #define CLRSEQINTSTAT                   0x0c
 464 #define         CLRSEQ_SWTMRTO          0x10
 465 #define         CLRSEQ_SEQINT           0x08
 466 #define         CLRSEQ_SCSIINT          0x04
 467 #define         CLRSEQ_PCIINT           0x02
 468 #define         CLRSEQ_SPLTINT          0x01
 469
 470 #define SWTIMER                         0x0e
 471
 472 #define SNSCB_QOFF                      0x10
 473
 474 #define SESCB_QOFF                      0x12
 475
 476 #define SDSCB_QOFF                      0x14
 477
 478 #define QOFF_CTLSTA                     0x16
 479 #define         EMPTY_SCB_AVAIL         0x80
 480 #define         NEW_SCB_AVAIL           0x40
 481 #define         SDSCB_ROLLOVR           0x20
 482 #define         HS_MAILBOX_ACT          0x10
 483 #define         SCB_QSIZE               0x0f
 484 #define         SCB_QSIZE_16384         0x0c
 485 #define         SCB_QSIZE_8192          0x0b
 486 #define         SCB_QSIZE_4096          0x0a
 487 #define         SCB_QSIZE_2048          0x09
 488 #define         SCB_QSIZE_1024          0x08
 489 #define         SCB_QSIZE_512           0x07
 490 #define         SCB_QSIZE_256           0x06
 491 #define         SCB_QSIZE_128           0x05
 492 #define         SCB_QSIZE_64            0x04
 493 #define         SCB_QSIZE_32            0x03
 494 #define         SCB_QSIZE_16            0x02
 495 #define         SCB_QSIZE_8             0x01
 496 #define         SCB_QSIZE_4             0x00
 497
 498 #define INTCTL                          0x18
 499 #define         SWTMINTMASK             0x80
 500 #define         SWTMINTEN               0x40
 501 #define         SWTIMER_START           0x20
 502 #define         AUTOCLRCMDINT           0x10
 503 #define         PCIINTEN                0x08
 504 #define         SCSIINTEN               0x04
 505 #define         SEQINTEN                0x02
 506 #define         SPLTINTEN               0x01
 507
 508 #define DFCNTRL                         0x19
 509 #define         SCSIENWRDIS             0x40
 510 #define         SCSIENACK               0x20
 511 #define         DIRECTIONACK            0x04
 512 #define         FIFOFLUSHACK            0x02
 513 #define         DIRECTIONEN             0x01
 514
 515 #define DSCOMMAND0                      0x19
 516 #define         CACHETHEN               0x80
 517 #define         DPARCKEN                0x40
 518 #define         MPARCKEN                0x20
 519 #define         EXTREQLCK               0x10
 520 #define         DISABLE_TWATE           0x02
 521 #define         CIOPARCKEN              0x01
 522
 523 #define DFSTATUS                        0x1a
 524 #define         PRELOAD_AVAIL           0x80
 525 #define         PKT_PRELOAD_AVAIL       0x40
 526 #define         MREQPEND                0x10
 527 #define         HDONE                   0x08
 528 #define         DFTHRESH                0x04
 529 #define         FIFOFULL                0x02
 530 #define         FIFOEMP                 0x01
 531
 532 #define ARBCTL                          0x1b
 533 #define         RESET_HARB              0x80
 534 #define         RETRY_SWEN              0x08
 535 #define         USE_TIME                0x07
 536
 537 #define SG_CACHE_SHADOW                 0x1b
 538 #define         ODD_SEG                 0x04
 539 #define         LAST_SEG                0x02
 540 #define         LAST_SEG_DONE           0x01
 541
 542 #define SG_CACHE_PRE                    0x1b
 543
 544 #define TYPEPTR                         0x20
 545
 546 #define LQIN                            0x20
 547
 548 #define TAGPTR                          0x21
 549
 550 #define LUNPTR                          0x22
 551
 552 #define DATALENPTR                      0x23
 553
 554 #define STATLENPTR                      0x24
 555
 556 #define CMDLENPTR                       0x25
 557
 558 #define ATTRPTR                         0x26
 559
 560 #define FLAGPTR                         0x27
 561
 562 #define CMDPTR                          0x28
 563
 564 #define QNEXTPTR                        0x29
 565
 566 #define IDPTR                           0x2a
 567
 568 #define ABRTBYTEPTR                     0x2b
 569
 570 #define ABRTBITPTR                      0x2c
 571
 572 #define MAXCMDBYTES                     0x2d
 573
 574 #define MAXCMD2RCV                      0x2e
 575
 576 #define SHORTTHRESH                     0x2f
 577
 578 #define LUNLEN                          0x30
 579 #define         TLUNLEN                 0xf0
 580 #define         ILUNLEN                 0x0f
 581
 582 #define CDBLIMIT                        0x31
 583
 584 #define MAXCMD                          0x32
 585
 586 #define MAXCMDCNT                       0x33
 587
 588 #define LQRSVD01                        0x34
 589
 590 #define LQRSVD16                        0x35
 591
 592 #define LQRSVD17                        0x36
 593
 594 #define CMDRSVD0                        0x37
 595
 596 #define LQCTL0                          0x38
 597 #define         LQITARGCLT              0xc0
 598 #define         LQIINITGCLT             0x30
 599 #define         LQ0TARGCLT              0x0c
 600 #define         LQ0INITGCLT             0x03
 601
 602 #define LQCTL1                          0x38
 603 #define         PCI2PCI                 0x04
 604 #define         SINGLECMD               0x02
 605 #define         ABORTPENDING            0x01
 606
 607 #define LQCTL2                          0x39
 608 #define         LQIRETRY                0x80
 609 #define         LQICONTINUE             0x40
 610 #define         LQITOIDLE               0x20
 611 #define         LQIPAUSE                0x10
 612 #define         LQORETRY                0x08
 613 #define         LQOCONTINUE             0x04
 614 #define         LQOTOIDLE               0x02
 615 #define         LQOPAUSE                0x01
 616
 617 #define SCSBIST0                        0x39
 618 #define         GSBISTERR               0x40
 619 #define         GSBISTDONE              0x20
 620 #define         GSBISTRUN               0x10
 621 #define         OSBISTERR               0x04
 622 #define         OSBISTDONE              0x02
 623 #define         OSBISTRUN               0x01
 624
 625 #define SCSISEQ0                        0x3a
 626 #define         TEMODEO                 0x80
 627 #define         ENSELO                  0x40
 628 #define         ENARBO                  0x20
 629 #define         FORCEBUSFREE            0x10
 630 #define         SCSIRSTO                0x01
 631
 632 #define SCSBIST1                        0x3a
 633 #define         NTBISTERR               0x04
 634 #define         NTBISTDONE              0x02
 635 #define         NTBISTRUN               0x01
 636
 637 #define SCSISEQ1                        0x3b
 638
 639 #define BUSINITID                       0x3c
 640
 641 #define SXFRCTL0                        0x3c
 642 #define         DFON                    0x80
 643 #define         DFPEXP                  0x40
 644 #define         BIOSCANCELEN            0x10
 645 #define         SPIOEN                  0x08
 646
 647 #define DLCOUNT                         0x3c
 648
 649 #define SXFRCTL1                        0x3d
 650 #define         BITBUCKET               0x80
 651 #define         ENSACHK                 0x40
 652 #define         ENSPCHK                 0x20
 653 #define         STIMESEL                0x18
 654 #define         ENSTIMER                0x04
 655 #define         ACTNEGEN                0x02
 656 #define         STPWEN                  0x01
 657
 658 #define BUSTARGID                       0x3e
 659
 660 #define SXFRCTL2                        0x3e
 661 #define         AUTORSTDIS              0x10
 662 #define         CMDDMAEN                0x08
 663 #define         ASU                     0x07
 664
 665 #define DFFSTAT                         0x3f
 666 #define         CURRFIFO                0x03
 667 #define         FIFO1FREE               0x20
 668 #define         FIFO0FREE               0x10
 669 #define         CURRFIFO_NONE           0x03
 670 #define         CURRFIFO_1              0x01
 671 #define         CURRFIFO_0              0x00
 672
 673 #define MULTARGID                       0x40
 674
 675 #define SCSISIGO                        0x40
 676 #define         CDO                     0x80
 677 #define         IOO                     0x40
 678 #define         MSGO                    0x20
 679 #define         ATNO                    0x10
 680 #define         SELO                    0x08
 681 #define         BSYO                    0x04
 682 #define         REQO                    0x02
 683 #define         ACKO                    0x01
 684
 685 #define SCSISIGI                        0x41
 686 #define         ATNI                    0x10
 687 #define         SELI                    0x08
 688 #define         BSYI                    0x04
 689 #define         REQI                    0x02
 690 #define         ACKI                    0x01
 691
 692 #define SCSIPHASE                       0x42
 693 #define         STATUS_PHASE            0x20
 694 #define         COMMAND_PHASE           0x10
 695 #define         MSG_IN_PHASE            0x08
 696 #define         MSG_OUT_PHASE           0x04
 697 #define         DATA_PHASE_MASK         0x03
 698 #define         DATA_IN_PHASE           0x02
 699 #define         DATA_OUT_PHASE          0x01
 700
 701 #define SCSIDAT0_IMG                    0x43
 702
 703 #define SCSIDAT                         0x44
 704
 705 #define SCSIBUS                         0x46
 706
 707 #define TARGIDIN                        0x48
 708 #define         CLKOUT                  0x80
 709 #define         TARGID                  0x0f
 710
 711 #define SELID                           0x49
 712 #define         SELID_MASK              0xf0
 713 #define         ONEBIT                  0x08
 714
 715 #define OPTIONMODE                      0x4a
 716 #define         OPTIONMODE_DEFAULTS     0x02
 717 #define         BIOSCANCTL              0x80
 718 #define         AUTOACKEN               0x40
 719 #define         BIASCANCTL              0x20
 720 #define         BUSFREEREV              0x10
 721 #define         ENDGFORMCHK             0x04
 722 #define         AUTO_MSGOUT_DE          0x02
 723
 724 #define SBLKCTL                         0x4a
 725 #define         DIAGLEDEN               0x80
 726 #define         DIAGLEDON               0x40
 727 #define         ENAB40                  0x08
 728 #define         ENAB20                  0x04
 729 #define         SELWIDE                 0x02
 730
 731 #define SIMODE0                         0x4b
 732 #define         ENSELDO                 0x40
 733 #define         ENSELDI                 0x20
 734 #define         ENSELINGO               0x10
 735 #define         ENIOERR                 0x08
 736 #define         ENOVERRUN               0x04
 737 #define         ENSPIORDY               0x02
 738 #define         ENARBDO                 0x01
 739
 740 #define SSTAT0                          0x4b
 741 #define         TARGET                  0x80
 742 #define         SELDO                   0x40
 743 #define         SELDI                   0x20
 744 #define         SELINGO                 0x10
 745 #define         IOERR                   0x08
 746 #define         OVERRUN                 0x04
 747 #define         SPIORDY                 0x02
 748 #define         ARBDO                   0x01
 749
 750 #define CLRSINT0                        0x4b
 751 #define         CLRSELDO                0x40
 752 #define         CLRSELDI                0x20
 753 #define         CLRSELINGO              0x10
 754 #define         CLRIOERR                0x08
 755 #define         CLROVERRUN              0x04
 756 #define         CLRSPIORDY              0x02
 757 #define         CLRARBDO                0x01
 758
 759 #define SSTAT1                          0x4c
 760 #define         SELTO                   0x80
 761 #define         ATNTARG                 0x40
 762 #define         SCSIRSTI                0x20
 763 #define         PHASEMIS                0x10
 764 #define         BUSFREE                 0x08
 765 #define         SCSIPERR                0x04
 766 #define         STRB2FAST               0x02
 767 #define         REQINIT                 0x01
 768
 769 #define CLRSINT1                        0x4c
 770 #define         CLRSELTIMEO             0x80
 771 #define         CLRATNO                 0x40
 772 #define         CLRSCSIRSTI             0x20
 773 #define         CLRBUSFREE              0x08
 774 #define         CLRSCSIPERR             0x04
 775 #define         CLRSTRB2FAST            0x02
 776 #define         CLRREQINIT              0x01
 777
 778 #define SIMODE2                         0x4d
 779 #define         ENWIDE_RES              0x04
 780 #define         ENSDONE                 0x02
 781 #define         ENDMADONE               0x01
 782
 783 #define SSTAT2                          0x4d
 784 #define         BUSFREETIME             0xc0
 785 #define         NONPACKREQ              0x20
 786 #define         EXP_ACTIVE              0x10
 787 #define         BSYX                    0x08
 788 #define         WIDE_RES                0x04
 789 #define         SDONE                   0x02
 790 #define         DMADONE                 0x01
 791 #define         BUSFREE_DFF1            0xc0
 792 #define         BUSFREE_DFF0            0x80
 793 #define         BUSFREE_LQO             0x40
 794
 795 #define CLRSINT2                        0x4d
 796 #define         CLRNONPACKREQ           0x20
 797 #define         CLRWIDE_RES             0x04
 798 #define         CLRSDONE                0x02
 799 #define         CLRDMADONE              0x01
 800
 801 #define PERRDIAG                        0x4e
 802 #define         HIZERO                  0x80
 803 #define         HIPERR                  0x40
 804 #define         PREVPHASE               0x20
 805 #define         PARITYERR               0x10
 806 #define         AIPERR                  0x08
 807 #define         CRCERR                  0x04
 808 #define         DGFORMERR               0x02
 809 #define         DTERR                   0x01
 810
 811 #define LQISTATE                        0x4e
 812
 813 #define LQOSTATE                        0x4f
 814
 815 #define SOFFCNT                         0x4f
 816
 817 #define LQISTAT0                        0x50
 818 #define         LQIATNQAS               0x20
 819 #define         LQICRCT1                0x10
 820 #define         LQICRCT2                0x08
 821 #define         LQIBADLQT               0x04
 822 #define         LQIATNLQ                0x02
 823 #define         LQIATNCMD               0x01
 824
 825 #define LQIMODE0                        0x50
 826 #define         ENLQIATNQASK            0x20
 827 #define         ENLQICRCT1              0x10
 828 #define         ENLQICRCT2              0x08
 829 #define         ENLQIBADLQT             0x04
 830 #define         ENLQIATNLQ              0x02
 831 #define         ENLQIATNCMD             0x01
 832
 833 #define CLRLQIINT0                      0x50
 834 #define         CLRLQIATNQAS            0x20
 835 #define         CLRLQICRCT1             0x10
 836 #define         CLRLQICRCT2             0x08
 837 #define         CLRLQIBADLQT            0x04
 838 #define         CLRLQIATNLQ             0x02
 839 #define         CLRLQIATNCMD            0x01
 840
 841 #define LQIMODE1                        0x51
 842 #define         ENLQIPHASE_LQ           0x80
 843 #define         ENLQIPHASE_NLQ          0x40
 844 #define         ENLIQABORT              0x20
 845 #define         ENLQICRCI_LQ            0x10
 846 #define         ENLQICRCI_NLQ           0x08
 847 #define         ENLQIBADLQI             0x04
 848 #define         ENLQIOVERI_LQ           0x02
 849 #define         ENLQIOVERI_NLQ          0x01
 850
 851 #define LQISTAT1                        0x51
 852 #define         LQIPHASE_LQ             0x80
 853 #define         LQIPHASE_NLQ            0x40
 854 #define         LQIABORT                0x20
 855 #define         LQICRCI_LQ              0x10
 856 #define         LQICRCI_NLQ             0x08
 857 #define         LQIBADLQI               0x04
 858 #define         LQIOVERI_LQ             0x02
 859 #define         LQIOVERI_NLQ            0x01
 860
 861 #define CLRLQIINT1                      0x51
 862 #define         CLRLQIPHASE_LQ          0x80
 863 #define         CLRLQIPHASE_NLQ         0x40
 864 #define         CLRLIQABORT             0x20
 865 #define         CLRLQICRCI_LQ           0x10
 866 #define         CLRLQICRCI_NLQ          0x08
 867 #define         CLRLQIBADLQI            0x04
 868 #define         CLRLQIOVERI_LQ          0x02
 869 #define         CLRLQIOVERI_NLQ         0x01
 870
 871 #define LQISTAT2                        0x52
 872 #define         PACKETIZED              0x80
 873 #define         LQIPHASE_OUTPKT         0x40
 874 #define         LQIWORKONLQ             0x20
 875 #define         LQIWAITFIFO             0x10
 876 #define         LQISTOPPKT              0x08
 877 #define         LQISTOPLQ               0x04
 878 #define         LQISTOPCMD              0x02
 879 #define         LQIGSAVAIL              0x01
 880
 881 #define SIMODE3                         0x53
 882 #define         ENNTRAMPERR             0x02
 883 #define         ENOSRAMPERR             0x01
 884
 885 #define SSTAT3                          0x53
 886 #define         NTRAMPERR               0x02
 887 #define         OSRAMPERR               0x01
 888
 889 #define CLRSINT3                        0x53
 890 #define         CLRNTRAMPERR            0x02
 891 #define         CLROSRAMPERR            0x01
 892
 893 #define CLRLQOINT0                      0x54
 894 #define         CLRLQOTARGSCBPERR       0x10
 895 #define         CLRLQOSTOPT2            0x08
 896 #define         CLRLQOATNLQ             0x04
 897 #define         CLRLQOATNPKT            0x02
 898 #define         CLRLQOTCRC              0x01
 899
 900 #define LQOSTAT0                        0x54
 901 #define         LQOTARGSCBPERR          0x10
 902 #define         LQOSTOPT2               0x08
 903 #define         LQOATNLQ                0x04
 904 #define         LQOATNPKT               0x02
 905 #define         LQOTCRC                 0x01
 906
 907 #define LQOMODE0                        0x54
 908 #define         ENLQOTARGSCBPERR        0x10
 909 #define         ENLQOSTOPT2             0x08
 910 #define         ENLQOATNLQ              0x04
 911 #define         ENLQOATNPKT             0x02
 912 #define         ENLQOTCRC               0x01
 913
 914 #define LQOMODE1                        0x55
 915 #define         ENLQOINITSCBPERR        0x10
 916 #define         ENLQOSTOPI2             0x08
 917 #define         ENLQOBADQAS             0x04
 918 #define         ENLQOBUSFREE            0x02
 919 #define         ENLQOPHACHGINPKT        0x01
 920
 921 #define CLRLQOINT1                      0x55
 922 #define         CLRLQOINITSCBPERR       0x10
 923 #define         CLRLQOSTOPI2            0x08
 924 #define         CLRLQOBADQAS            0x04
 925 #define         CLRLQOBUSFREE           0x02
 926 #define         CLRLQOPHACHGINPKT       0x01
 927
 928 #define LQOSTAT1                        0x55
 929 #define         LQOINITSCBPERR          0x10
 930 #define         LQOSTOPI2               0x08
 931 #define         LQOBADQAS               0x04
 932 #define         LQOBUSFREE              0x02
 933 #define         LQOPHACHGINPKT          0x01
 934
 935 #define LQOSTAT2                        0x56
 936 #define         LQOPKT                  0xe0
 937 #define         LQOWAITFIFO             0x10
 938 #define         LQOPHACHGOUTPKT         0x02
 939 #define         LQOSTOP0                0x01
 940
 941 #define OS_SPACE_CNT                    0x56
 942
 943 #define SIMODE1                         0x57
 944 #define         ENSELTIMO               0x80
 945 #define         ENATNTARG               0x40
 946 #define         ENSCSIRST               0x20
 947 #define         ENPHASEMIS              0x10
 948 #define         ENBUSFREE               0x08
 949 #define         ENSCSIPERR              0x04
 950 #define         ENSTRB2FAST             0x02
 951 #define         ENREQINIT               0x01
 952
 953 #define GSFIFO                          0x58
 954
 955 #define DFFSXFRCTL                      0x5a
 956 #define         DFFBITBUCKET            0x08
 957 #define         CLRSHCNT                0x04
 958 #define         CLRCHN                  0x02
 959 #define         RSTCHN                  0x01
 960
 961 #define LQOSCSCTL                       0x5a
 962 #define         LQOH2A_VERSION          0x80
 963 #define         LQOBUSETDLY             0x40
 964 #define         LQONOHOLDLACK           0x02
 965 #define         LQONOCHKOVER            0x01
 966
 967 #define NEXTSCB                         0x5a
 968
 969 #define CLRSEQINTSRC                    0x5b
 970 #define         CLRCTXTDONE             0x40
 971 #define         CLRSAVEPTRS             0x20
 972 #define         CLRCFG4DATA             0x10
 973 #define         CLRCFG4ISTAT            0x08
 974 #define         CLRCFG4TSTAT            0x04
 975 #define         CLRCFG4ICMD             0x02
 976 #define         CLRCFG4TCMD             0x01
 977
 978 #define SEQINTSRC                       0x5b
 979 #define         CTXTDONE                0x40
 980 #define         SAVEPTRS                0x20
 981 #define         CFG4DATA                0x10
 982 #define         CFG4ISTAT               0x08
 983 #define         CFG4TSTAT               0x04
 984 #define         CFG4ICMD                0x02
 985 #define         CFG4TCMD                0x01
 986
 987 #define SEQIMODE                        0x5c
 988 #define         ENCTXTDONE              0x40
 989 #define         ENSAVEPTRS              0x20
 990 #define         ENCFG4DATA              0x10
 991 #define         ENCFG4ISTAT             0x08
 992 #define         ENCFG4TSTAT             0x04
 993 #define         ENCFG4ICMD              0x02
 994 #define         ENCFG4TCMD              0x01
 995
 996 #define CURRSCB                         0x5c
 997
 998 #define CRCCONTROL                      0x5d
 999 #define         CRCVALCHKEN             0x40
1000
1001 #define MDFFSTAT                        0x5d
1002 #define         SHCNTNEGATIVE           0x40
1003 #define         SHCNTMINUS1             0x20
1004 #define         LASTSDONE               0x10
1005 #define         SHVALID                 0x08
1006 #define         DLZERO                  0x04
1007 #define         DATAINFIFO              0x02
1008 #define         FIFOFREE                0x01
1009
1010 #define DFFTAG                          0x5e
1011
1012 #define SCSITEST                        0x5e
1013 #define         CNTRTEST                0x08
1014 #define         SEL_TXPLL_DEBUG         0x04
1015
1016 #define LASTSCB                         0x5e
1017
1018 #define IOPDNCTL                        0x5f
1019 #define         DISABLE_OE              0x80
1020 #define         PDN_IDIST               0x04
1021 #define         PDN_DIFFSENSE           0x01
1022
1023 #define DGRPCRCI                        0x60
1024
1025 #define NEGOADDR                        0x60
1026
1027 #define SHADDR                          0x60
1028
1029 #define NEGPERIOD                       0x61
1030
1031 #define NEGOFFSET                       0x62
1032
1033 #define PACKCRCI                        0x62
1034
1035 #define NEGPPROPTS                      0x63
1036 #define         PPROPT_PACE             0x08
1037 #define         PPROPT_QAS              0x04
1038 #define         PPROPT_DT               0x02
1039 #define         PPROPT_IUT              0x01
1040
1041 #define NEGCONOPTS                      0x64
1042 #define         ENSNAPSHOT              0x40
1043 #define         RTI_WRTDIS              0x20
1044 #define         RTI_OVRDTRN             0x10
1045 #define         ENSLOWCRC               0x08
1046 #define         ENAUTOATNI              0x04
1047 #define         ENAUTOATNO              0x02
1048 #define         WIDEXFER                0x01
1049
1050 #define ANNEXCOL                        0x65
1051
1052 #define ANNEXDAT                        0x66
1053
1054 #define SCSCHKN                         0x66
1055 #define         BIDICHKDIS              0x80
1056 #define         STSELSKIDDIS            0x40
1057 #define         CURRFIFODEF             0x20
1058 #define         WIDERESEN               0x10
1059 #define         SDONEMSKDIS             0x08
1060 #define         DFFACTCLR               0x04
1061 #define         SHVALIDSTDIS            0x02
1062 #define         LSTSGCLRDIS             0x01
1063
1064 #define IOWNID                          0x67
1065
1066 #define PLL960CTL0                      0x68
1067
1068 #define SHCNT                           0x68
1069
1070 #define PLL960CTL1                      0x69
1071
1072 #define TOWNID                          0x69
1073
1074 #define PLL960CNT0                      0x6a
1075
1076 #define XSIG                            0x6a
1077
1078 #define SELOID                          0x6b
1079
1080 #define FAIRNESS                        0x6c
1081
1082 #define PLL400CTL0                      0x6c
1083 #define         PLL_VCOSEL              0x80
1084 #define         PLL_PWDN                0x40
1085 #define         PLL_NS                  0x30
1086 #define         PLL_ENLUD               0x08
1087 #define         PLL_ENLPF               0x04
1088 #define         PLL_DLPF                0x02
1089 #define         PLL_ENFBM               0x01
1090
1091 #define PLL400CTL1                      0x6d
1092 #define         PLL_CNTEN               0x80
1093 #define         PLL_CNTCLR              0x40
1094 #define         PLL_RST                 0x01
1095
1096 #define UNFAIRNESS                      0x6e
1097
1098 #define PLL400CNT0                      0x6e
1099
1100 #define HADDR                           0x70
1101
1102 #define HODMAADR                        0x70
1103
1104 #define PLLDELAY                        0x70
1105 #define         SPLIT_DROP_REQ          0x80
1106
1107 #define HCNT                            0x78
1108
1109 #define HODMACNT                        0x78
1110
1111 #define HODMAEN                         0x7a
1112
1113 #define SGHADDR                         0x7c
1114
1115 #define SCBHADDR                        0x7c
1116
1117 #define SGHCNT                          0x84
1118
1119 #define SCBHCNT                         0x84
1120
1121 #define DFF_THRSH                       0x88
1122 #define         WR_DFTHRSH              0x70
1123 #define         RD_DFTHRSH              0x07
1124 #define         WR_DFTHRSH_MAX          0x70
1125 #define         WR_DFTHRSH_90           0x60
1126 #define         WR_DFTHRSH_85           0x50
1127 #define         WR_DFTHRSH_75           0x40
1128 #define         WR_DFTHRSH_63           0x30
1129 #define         WR_DFTHRSH_50           0x20
1130 #define         WR_DFTHRSH_25           0x10
1131 #define         RD_DFTHRSH_MAX          0x07
1132 #define         RD_DFTHRSH_90           0x06
1133 #define         RD_DFTHRSH_85           0x05
1134 #define         RD_DFTHRSH_75           0x04
1135 #define         RD_DFTHRSH_63           0x03
1136 #define         RD_DFTHRSH_50           0x02
1137 #define         RD_DFTHRSH_25           0x01
1138 #define         RD_DFTHRSH_MIN          0x00
1139 #define         WR_DFTHRSH_MIN          0x00
1140
1141 #define ROMADDR                         0x8a
1142
1143 #define ROMCNTRL                        0x8d
1144 #define         ROMOP                   0xe0
1145 #define         ROMSPD                  0x18
1146 #define         REPEAT                  0x02
1147 #define         RDY                     0x01
1148
1149 #define ROMDATA                         0x8e
1150
1151 #define CMCRXMSG0                       0x90
1152
1153 #define OVLYRXMSG0                      0x90
1154
1155 #define DCHRXMSG0                       0x90
1156
1157 #define ROENABLE                        0x90
1158 #define         MSIROEN                 0x20
1159 #define         OVLYROEN                0x10
1160 #define         CMCROEN                 0x08
1161 #define         SGROEN                  0x04
1162 #define         DCH1ROEN                0x02
1163 #define         DCH0ROEN                0x01
1164
1165 #define OVLYRXMSG1                      0x91
1166
1167 #define CMCRXMSG1                       0x91
1168
1169 #define DCHRXMSG1                       0x91
1170
1171 #define NSENABLE                        0x91
1172 #define         MSINSEN                 0x20
1173 #define         OVLYNSEN                0x10
1174 #define         CMCNSEN                 0x08
1175 #define         SGNSEN                  0x04
1176 #define         DCH1NSEN                0x02
1177 #define         DCH0NSEN                0x01
1178
1179 #define DCHRXMSG2                       0x92
1180
1181 #define CMCRXMSG2                       0x92
1182
1183 #define OST                             0x92
1184
1185 #define OVLYRXMSG2                      0x92
1186
1187 #define DCHRXMSG3                       0x93
1188
1189 #define OVLYRXMSG3                      0x93
1190
1191 #define CMCRXMSG3                       0x93
1192
1193 #define PCIXCTL                         0x93
1194 #define         SERRPULSE               0x80
1195 #define         UNEXPSCIEN              0x20
1196 #define         SPLTSMADIS              0x10
1197 #define         SPLTSTADIS              0x08
1198 #define         SRSPDPEEN               0x04
1199 #define         TSCSERREN               0x02
1200 #define         CMPABCDIS               0x01
1201
1202 #define CMCSEQBCNT                      0x94
1203
1204 #define OVLYSEQBCNT                     0x94
1205
1206 #define DCHSEQBCNT                      0x94
1207
1208 #define DCHSPLTSTAT0                    0x96
1209
1210 #define OVLYSPLTSTAT0                   0x96
1211
1212 #define CMCSPLTSTAT0                    0x96
1213
1214 #define OVLYSPLTSTAT1                   0x97
1215
1216 #define DCHSPLTSTAT1                    0x97
1217
1218 #define CMCSPLTSTAT1                    0x97
1219
1220 #define SGRXMSG0                        0x98
1221 #define         CDNUM                   0xf8
1222 #define         CFNUM                   0x07
1223
1224 #define SLVSPLTOUTADR0                  0x98
1225 #define         LOWER_ADDR              0x7f
1226
1227 #define SGRXMSG1                        0x99
1228 #define         CBNUM                   0xff
1229
1230 #define SLVSPLTOUTADR1                  0x99
1231 #define         REQ_DNUM                0xf8
1232 #define         REQ_FNUM                0x07
1233
1234 #define SGRXMSG2                        0x9a
1235 #define         MINDEX                  0xff
1236
1237 #define SLVSPLTOUTADR2                  0x9a
1238 #define         REQ_BNUM                0xff
1239
1240 #define SGRXMSG3                        0x9b
1241 #define         MCLASS                  0x0f
1242
1243 #define SLVSPLTOUTADR3                  0x9b
1244 #define         TAG_NUM                 0x1f
1245 #define         RLXORD                  0x10
1246
1247 #define SLVSPLTOUTATTR0                 0x9c
1248 #define         LOWER_BCNT              0xff
1249
1250 #define SGSEQBCNT                       0x9c
1251
1252 #define SLVSPLTOUTATTR1                 0x9d
1253 #define         CMPLT_DNUM              0xf8
1254 #define         CMPLT_FNUM              0x07
1255
1256 #define SGSPLTSTAT0                     0x9e
1257 #define         STAETERM                0x80
1258 #define         SCBCERR                 0x40
1259 #define         SCADERR                 0x20
1260 #define         SCDATBUCKET             0x10
1261 #define         CNTNOTCMPLT             0x08
1262 #define         RXOVRUN                 0x04
1263 #define         RXSCEMSG                0x02
1264 #define         RXSPLTRSP               0x01
1265
1266 #define SLVSPLTOUTATTR2                 0x9e
1267 #define         CMPLT_BNUM              0xff
1268
1269 #define SGSPLTSTAT1                     0x9f
1270 #define         RXDATABUCKET            0x01
1271
1272 #define SFUNCT                          0x9f
1273 #define         TEST_GROUP              0xf0
1274 #define         TEST_NUM                0x0f
1275
1276 #define DF0PCISTAT                      0xa0
1277
1278 #define REG0                            0xa0
1279
1280 #define DF1PCISTAT                      0xa1
1281
1282 #define SGPCISTAT                       0xa2
1283
1284 #define REG1                            0xa2
1285
1286 #define CMCPCISTAT                      0xa3
1287
1288 #define OVLYPCISTAT                     0xa4
1289 #define         SCAAPERR                0x08
1290 #define         RDPERR                  0x04
1291
1292 #define REG_ISR                         0xa4
1293
1294 #define SG_STATE                        0xa6
1295 #define         FETCH_INPROG            0x04
1296 #define         LOADING_NEEDED          0x02
1297 #define         SEGS_AVAIL              0x01
1298
1299 #define MSIPCISTAT                      0xa6
1300 #define         RMA                     0x20
1301 #define         RTA                     0x10
1302 #define         CLRPENDMSI              0x08
1303 #define         DPR                     0x01
1304
1305 #define DATA_COUNT_ODD                  0xa7
1306
1307 #define TARGPCISTAT                     0xa7
1308 #define         DPE                     0x80
1309 #define         SSE                     0x40
1310 #define         STA                     0x08
1311 #define         TWATERR                 0x02
1312
1313 #define SCBPTR                          0xa8
1314
1315 #define CCSCBACNT                       0xab
1316
1317 #define SCBAUTOPTR                      0xab
1318 #define         AUSCBPTR_EN             0x80
1319 #define         SCBPTR_ADDR             0x38
1320 #define         SCBPTR_OFF              0x07
1321
1322 #define CCSGADDR                        0xac
1323
1324 #define CCSCBADDR                       0xac
1325
1326 #define CCSCBADR_BK                     0xac
1327
1328 #define CMC_RAMBIST                     0xad
1329 #define         SG_ELEMENT_SIZE         0x80
1330 #define         SCBRAMBIST_FAIL         0x40
1331 #define         SG_BIST_FAIL            0x20
1332 #define         SG_BIST_EN              0x10
1333 #define         CMC_BUFFER_BIST_FAIL    0x02
1334 #define         CMC_BUFFER_BIST_EN      0x01
1335
1336 #define CCSCBCTL                        0xad
1337 #define         CCSCBDONE               0x80
1338 #define         ARRDONE                 0x40
1339 #define         CCARREN                 0x10
1340 #define         CCSCBEN                 0x08
1341 #define         CCSCBDIR                0x04
1342 #define         CCSCBRESET              0x01
1343
1344 #define CCSGCTL                         0xad
1345 #define         CCSGEN                  0x0c
1346 #define         CCSGDONE                0x80
1347 #define         SG_CACHE_AVAIL          0x10
1348 #define         CCSGENACK               0x08
1349 #define         SG_FETCH_REQ            0x02
1350 #define         CCSGRESET               0x01
1351
1352 #define CCSGRAM                         0xb0
1353
1354 #define FLEXADR                         0xb0
1355
1356 #define CCSCBRAM                        0xb0
1357
1358 #define FLEXCNT                         0xb3
1359
1360 #define FLEXDMASTAT                     0xb5
1361 #define         FLEXDMAERR              0x02
1362 #define         FLEXDMADONE             0x01
1363
1364 #define FLEXDATA                        0xb6
1365
1366 #define BRDDAT                          0xb8
1367
1368 #define BRDCTL                          0xb9
1369 #define         FLXARBACK               0x80
1370 #define         FLXARBREQ               0x40
1371 #define         BRDADDR                 0x38
1372 #define         BRDEN                   0x04
1373 #define         BRDRW                   0x02
1374 #define         BRDSTB                  0x01
1375
1376 #define SEEADR                          0xba
1377
1378 #define SEEDAT                          0xbc
1379
1380 #define SEECTL                          0xbe
1381 #define         SEEOP_EWDS              0x40
1382 #define         SEEOP_WALL              0x40
1383 #define         SEEOP_EWEN              0x40
1384 #define         SEEOPCODE               0x70
1385 #define         SEERST                  0x02
1386 #define         SEESTART                0x01
1387 #define         SEEOP_ERASE             0x70
1388 #define         SEEOP_READ              0x60
1389 #define         SEEOP_WRITE             0x50
1390 #define         SEEOP_ERAL              0x40
1391
1392 #define SEESTAT                         0xbe
1393 #define         INIT_DONE               0x80
1394 #define         LDALTID_L               0x08
1395 #define         SEEARBACK               0x04
1396 #define         SEEBUSY                 0x02
1397
1398 #define SCBCNT                          0xbf
1399
1400 #define DSPFLTRCTL                      0xc0
1401 #define         FLTRDISABLE             0x20
1402 #define         EDGESENSE               0x10
1403 #define         DSPFCNTSEL              0x0f
1404
1405 #define DFWADDR                         0xc0
1406
1407 #define DSPDATACTL                      0xc1
1408 #define         BYPASSENAB              0x80
1409 #define         DESQDIS                 0x10
1410 #define         RCVROFFSTDIS            0x04
1411 #define         XMITOFFSTDIS            0x02
1412
1413 #define DSPREQCTL                       0xc2
1414 #define         MANREQCTL               0xc0
1415 #define         MANREQDLY               0x3f
1416
1417 #define DFRADDR                         0xc2
1418
1419 #define DSPACKCTL                       0xc3
1420 #define         MANACKCTL               0xc0
1421 #define         MANACKDLY               0x3f
1422
1423 #define DFDAT                           0xc4
1424
1425 #define DSPSELECT                       0xc4
1426 #define         AUTOINCEN               0x80
1427 #define         DSPSEL                  0x1f
1428
1429 #define WRTBIASCTL                      0xc5
1430 #define         AUTOXBCDIS              0x80
1431 #define         XMITMANVAL              0x3f
1432
1433 #define RCVRBIOSCTL                     0xc6
1434 #define         AUTORBCDIS              0x80
1435 #define         RCVRMANVAL              0x3f
1436
1437 #define WRTBIASCALC                     0xc7
1438
1439 #define DFPTRS                          0xc8
1440
1441 #define RCVRBIASCALC                    0xc8
1442
1443 #define DFBKPTR                         0xc9
1444
1445 #define SKEWCALC                        0xc9
1446
1447 #define DFDBCTL                         0xcb
1448 #define         DFF_CIO_WR_RDY          0x20
1449 #define         DFF_CIO_RD_RDY          0x10
1450 #define         DFF_DIR_ERR             0x08
1451 #define         DFF_RAMBIST_FAIL        0x04
1452 #define         DFF_RAMBIST_DONE        0x02
1453 #define         DFF_RAMBIST_EN          0x01
1454
1455 #define DFSCNT                          0xcc
1456
1457 #define DFBCNT                          0xce
1458
1459 #define OVLYADDR                        0xd4
1460
1461 #define SEQCTL0                         0xd6
1462 #define         PERRORDIS               0x80
1463 #define         PAUSEDIS                0x40
1464 #define         FAILDIS                 0x20
1465 #define         FASTMODE                0x10
1466 #define         BRKADRINTEN             0x08
1467 #define         STEP                    0x04
1468 #define         SEQRESET                0x02
1469 #define         LOADRAM                 0x01
1470
1471 #define SEQCTL1                         0xd7
1472 #define         OVRLAY_DATA_CHK         0x08
1473 #define         RAMBIST_DONE            0x04
1474 #define         RAMBIST_FAIL            0x02
1475 #define         RAMBIST_EN              0x01
1476
1477 #define FLAGS                           0xd8
1478 #define         ZERO                    0x02
1479 #define         CARRY                   0x01
1480
1481 #define SEQINTCTL                       0xd9
1482 #define         INTVEC1DSL              0x80
1483 #define         INT1_CONTEXT            0x20
1484 #define         SCS_SEQ_INT1M1          0x10
1485 #define         SCS_SEQ_INT1M0          0x08
1486 #define         INTMASK2                0x04
1487 #define         INTMASK1                0x02
1488 #define         IRET                    0x01
1489
1490 #define SEQRAM                          0xda
1491
1492 #define PRGMCNT                         0xde
1493
1494 #define ACCUM                           0xe0
1495
1496 #define SINDEX                          0xe2
1497
1498 #define DINDEX                          0xe4
1499
1500 #define BRKADDR0                        0xe6
1501
1502 #define BRKADDR1                        0xe6
1503 #define         BRKDIS                  0x80
1504
1505 #define ALLONES                         0xe8
1506
1507 #define ALLZEROS                        0xea
1508
1509 #define NONE                            0xea
1510
1511 #define SINDIR                          0xec
1512
1513 #define DINDIR                          0xed
1514
1515 #define FUNCTION1                       0xf0
1516
1517 #define STACK                           0xf2
1518
1519 #define INTVEC1_ADDR                    0xf4
1520
1521 #define CURADDR                         0xf4
1522
1523 #define LASTADDR                        0xf6
1524
1525 #define INTVEC2_ADDR                    0xf6
1526
1527 #define LONGJMP_ADDR                    0xf8
1528
1529 #define ACCUM_SAVE                      0xfa
1530
1531 #define AHD_PCI_CONFIG_BASE             0x100
1532
1533 #define SRAM_BASE                       0x100
1534
1535 #define WAITING_SCB_TAILS               0x100
1536
1537 #define WAITING_TID_HEAD                0x120
1538
1539 #define WAITING_TID_TAIL                0x122
1540
1541 #define NEXT_QUEUED_SCB_ADDR            0x124
1542
1543 #define COMPLETE_SCB_HEAD               0x128
1544
1545 #define COMPLETE_SCB_DMAINPROG_HEAD             0x12a
1546
1547 #define COMPLETE_DMA_SCB_HEAD           0x12c
1548
1549 #define COMPLETE_DMA_SCB_TAIL           0x12e
1550
1551 #define COMPLETE_ON_QFREEZE_HEAD                0x130
1552
1553 #define QFREEZE_COUNT                   0x132
1554
1555 #define KERNEL_QFREEZE_COUNT            0x134
1556
1557 #define SAVED_MODE                      0x136
1558
1559 #define MSG_OUT                         0x137
1560
1561 #define DMAPARAMS                       0x138
1562 #define         PRELOADEN               0x80
1563 #define         WIDEODD                 0x40
1564 #define         SCSIEN                  0x20
1565 #define         SDMAENACK               0x10
1566 #define         SDMAEN                  0x10
1567 #define         HDMAEN                  0x08
1568 #define         HDMAENACK               0x08
1569 #define         DIRECTION               0x04
1570 #define         FIFOFLUSH               0x02
1571 #define         FIFORESET               0x01
1572
1573 #define SEQ_FLAGS                       0x139
1574 #define         NOT_IDENTIFIED          0x80
1575 #define         NO_CDB_SENT             0x40
1576 #define         TARGET_CMD_IS_TAGGED    0x40
1577 #define         DPHASE                  0x20
1578 #define         TARG_CMD_PENDING        0x10
1579 #define         CMDPHASE_PENDING        0x08
1580 #define         DPHASE_PENDING          0x04
1581 #define         SPHASE_PENDING          0x02
1582 #define         NO_DISCONNECT           0x01
1583
1584 #define SAVED_SCSIID                    0x13a
1585
1586 #define SAVED_LUN                       0x13b
1587
1588 #define LASTPHASE                       0x13c
1589 #define         PHASE_MASK              0xe0
1590 #define         CDI                     0x80
1591 #define         IOI                     0x40
1592 #define         MSGI                    0x20
1593 #define         P_BUSFREE               0x01
1594 #define         P_MESGIN                0xe0
1595 #define         P_STATUS                0xc0
1596 #define         P_MESGOUT               0xa0
1597 #define         P_COMMAND               0x80
1598 #define         P_DATAIN_DT             0x60
1599 #define         P_DATAIN                0x40
1600 #define         P_DATAOUT_DT            0x20
1601 #define         P_DATAOUT               0x00
1602
1603 #define QOUTFIFO_ENTRY_VALID_TAG                0x13d
1604
1605 #define KERNEL_TQINPOS                  0x13e
1606
1607 #define TQINPOS                         0x13f
1608
1609 #define SHARED_DATA_ADDR                0x140
1610
1611 #define QOUTFIFO_NEXT_ADDR              0x144
1612
1613 #define ARG_1                           0x148
1614 #define RETURN_1                        0x148
1615 #define         SEND_MSG                0x80
1616 #define         SEND_SENSE              0x40
1617 #define         SEND_REJ                0x20
1618 #define         MSGOUT_PHASEMIS         0x10
1619 #define         EXIT_MSG_LOOP           0x08
1620 #define         CONT_MSG_LOOP_WRITE     0x04
1621 #define         CONT_MSG_LOOP_READ      0x03
1622 #define         CONT_MSG_LOOP_TARG      0x02
1623
1624 #define ARG_2                           0x149
1625 #define RETURN_2                        0x149
1626
1627 #define LAST_MSG                        0x14a
1628
1629 #define SCSISEQ_TEMPLATE                0x14b
1630 #define         MANUALCTL               0x40
1631 #define         ENSELI                  0x20
1632 #define         ENRSELI                 0x10
1633 #define         MANUALP                 0x0c
1634 #define         ENAUTOATNP              0x02
1635 #define         ALTSTIM                 0x01
1636
1637 #define INITIATOR_TAG                   0x14c
1638
1639 #define SEQ_FLAGS2                      0x14d
1640 #define         SELECTOUT_QFROZEN       0x04
1641 #define         TARGET_MSG_PENDING      0x02
1642 #define         PENDING_MK_MESSAGE      0x01
1643
1644 #define ALLOCFIFO_SCBPTR                0x14e
1645
1646 #define INT_COALESCING_TIMER            0x150
1647
1648 #define INT_COALESCING_MAXCMDS          0x152
1649
1650 #define INT_COALESCING_MINCMDS          0x153
1651
1652 #define CMDS_PENDING                    0x154
1653
1654 #define INT_COALESCING_CMDCOUNT         0x156
1655
1656 #define LOCAL_HS_MAILBOX                0x157
1657
1658 #define CMDSIZE_TABLE                   0x158
1659
1660 #define MK_MESSAGE_SCB                  0x160
1661
1662 #define MK_MESSAGE_SCSIID               0x162
1663
1664 #define SCB_RESIDUAL_DATACNT            0x180
1665 #define SCB_CDB_STORE                   0x180
1666 #define SCB_HOST_CDB_PTR                0x180
1667
1668 #define SCB_BASE                        0x180
1669
1670 #define SCB_RESIDUAL_SGPTR              0x184
1671 #define         SG_ADDR_MASK            0xf8
1672 #define         SG_OVERRUN_RESID        0x02
1673
1674 #define SCB_SCSI_STATUS                 0x188
1675 #define SCB_HOST_CDB_LEN                0x188
1676
1677 #define SCB_TARGET_PHASES               0x189
1678
1679 #define SCB_TARGET_DATA_DIR             0x18a
1680
1681 #define SCB_TARGET_ITAG                 0x18b
1682
1683 #define SCB_SENSE_BUSADDR               0x18c
1684 #define SCB_NEXT_COMPLETE               0x18c
1685
1686 #define SCB_TAG                         0x190
1687 #define SCB_FIFO_USE_COUNT              0x190
1688
1689 #define SCB_CONTROL                     0x192
1690 #define         TARGET_SCB              0x80
1691 #define         DISCENB                 0x40
1692 #define         TAG_ENB                 0x20
1693 #define         MK_MESSAGE              0x10
1694 #define         STATUS_RCVD             0x08
1695 #define         DISCONNECTED            0x04
1696 #define         SCB_TAG_TYPE            0x03
1697
1698 #define SCB_SCSIID                      0x193
1699 #define         TID                     0xf0
1700 #define         OID                     0x0f
1701
1702 #define SCB_LUN                         0x194
1703 #define         LID                     0xff
1704
1705 #define SCB_TASK_ATTRIBUTE              0x195
1706 #define         SCB_XFERLEN_ODD         0x01
1707
1708 #define SCB_CDB_LEN                     0x196
1709 #define         SCB_CDB_LEN_PTR         0x80
1710
1711 #define SCB_TASK_MANAGEMENT             0x197
1712
1713 #define SCB_DATAPTR                     0x198
1714
1715 #define SCB_DATACNT                     0x1a0
1716 #define         SG_LAST_SEG             0x80
1717 #define         SG_HIGH_ADDR_BITS       0x7f
1718
1719 #define SCB_SGPTR                       0x1a4
1720 #define         SG_STATUS_VALID         0x04
1721 #define         SG_FULL_RESID           0x02
1722 #define         SG_LIST_NULL            0x01
1723
1724 #define SCB_BUSADDR                     0x1a8
1725
1726 #define SCB_NEXT                        0x1ac
1727 #define SCB_NEXT_SCB_BUSADDR            0x1ac
1728
1729 #define SCB_NEXT2                       0x1ae
1730
1731 #define SCB_SPARE                       0x1b0
1732 #define SCB_PKT_LUN                     0x1b0
1733
1734 #define SCB_DISCONNECTED_LISTS          0x1b8
1735
1736
1737 #define STIMESEL_SHIFT  0x03
1738 #define STIMESEL_MIN    0x18
1739 #define INVALID_ADDR    0x80
1740 #define CMD_GROUP_CODE_SHIFT    0x05
1741 #define AHD_PRECOMP_MASK        0x07
1742 #define TARGET_DATA_IN  0x01
1743 #define SEEOP_EWEN_ADDR 0xc0
1744 #define NUMDSPS         0x14
1745 #define DST_MODE_SHIFT  0x04
1746 #define CCSCBADDR_MAX   0x80
1747 #define AHD_ANNEXCOL_PER_DEV0   0x04
1748 #define TARGET_CMD_CMPLT        0xfe
1749 #define SEEOP_WRAL_ADDR 0x40
1750 #define BUS_8_BIT       0x00
1751 #define AHD_TIMER_MAX_US        0x18ffe7
1752 #define AHD_TIMER_MAX_TICKS     0xffff
1753 #define AHD_SENSE_BUFSIZE       0x100
1754 #define AHD_PRECOMP_SHIFT       0x00
1755 #define AHD_PRECOMP_CUTBACK_37  0x07
1756 #define AHD_ANNEXCOL_PRECOMP_SLEW       0x04
1757 #define AHD_AMPLITUDE_DEF       0x07
1758 #define WRTBIASCTL_HP_DEFAULT   0x00
1759 #define TID_SHIFT       0x04
1760 #define STATUS_QUEUE_FULL       0x28
1761 #define STATUS_BUSY     0x08
1762 #define SEEOP_EWDS_ADDR 0x00
1763 #define SCB_TRANSFER_SIZE_FULL_LUN      0x38
1764 #define MK_MESSAGE_BIT_OFFSET   0x04
1765 #define MAX_OFFSET_PACED        0xfe
1766 #define MAX_OFFSET_NON_PACED    0x7f
1767 #define LUNLEN_SINGLE_LEVEL_LUN 0x0f
1768 #define CCSGADDR_MAX    0x80
1769 #define B_CURRFIFO_0    0x02
1770 #define BUS_32_BIT      0x02
1771 #define AHD_TIMER_US_PER_TICK   0x19
1772 #define AHD_SLEWRATE_SHIFT      0x03
1773 #define AHD_SLEWRATE_MASK       0x78
1774 #define AHD_SLEWRATE_DEF_REVA   0x08
1775 #define AHD_PRECOMP_CUTBACK_29  0x06
1776 #define AHD_NUM_PER_DEV_ANNEXCOLS       0x04
1777 #define AHD_ANNEXCOL_AMPLITUDE  0x06
1778 #define AHD_AMPLITUDE_SHIFT     0x00
1779 #define AHD_AMPLITUDE_MASK      0x07
1780 #define STIMESEL_BUG_ADJ        0x08
1781 #define STATUS_PKT_SENSE        0xff
1782 #define SRC_MODE_SHIFT  0x00
1783 #define SEEOP_ERAL_ADDR 0x80
1784 #define NVRAM_SCB_OFFSET        0x2c
1785 #define MAX_OFFSET_PACED_BUG    0x7f
1786 #define CCSGRAM_MAXSEGS 0x10
1787 #define AHD_SLEWRATE_DEF_REVB   0x08
1788 #define AHD_PRECOMP_CUTBACK_17  0x04
1789 #define SCB_TRANSFER_SIZE_1BYTE_LUN     0x30
1790 #define PKT_OVERRUN_BUFSIZE     0x200
1791 #define MAX_OFFSET      0xfe
1792 #define HOST_MSG        0xff
1793 #define BUS_16_BIT      0x01
1794
1795
1796 /* Downloaded Constant Definitions */
1797 #define SG_SIZEOF       0x04
1798 #define SG_PREFETCH_ALIGN_MASK  0x02
1799 #define SG_PREFETCH_CNT_LIMIT   0x01
1800 #define CACHELINE_MASK  0x07
1801 #define SCB_TRANSFER_SIZE       0x06
1802 #define PKT_OVERRUN_BUFOFFSET   0x05
1803 #define SG_PREFETCH_ADDR_MASK   0x03
1804 #define SG_PREFETCH_CNT 0x00
1805 #define DOWNLOAD_CONST_COUNT    0x08
1806
1807
1808 /* Exported Labels */
1809 #define LABEL_timer_isr 0x28b
1810 #define LABEL_seq_isr   0x28f