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WIP FPC-III support
[linux/fpc-iii.git] / drivers / scsi / arcmsr / arcmsr.h
blob0f6abd23361418d0e4fd717dda238c3ca1ca894f
1 /*
2 *******************************************************************************
3 ** O.S : Linux
4 ** FILE NAME : arcmsr.h
5 ** BY : Nick Cheng
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA RAID Host adapter
8 *******************************************************************************
9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
10 **
11 ** Web site: www.areca.com.tw
12 ** E-mail: support@areca.com.tw
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License version 2 as
16 ** published by the Free Software Foundation.
17 ** This program is distributed in the hope that it will be useful,
18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ** GNU General Public License for more details.
21 *******************************************************************************
22 ** Redistribution and use in source and binary forms, with or without
23 ** modification, are permitted provided that the following conditions
24 ** are met:
25 ** 1. Redistributions of source code must retain the above copyright
26 ** notice, this list of conditions and the following disclaimer.
27 ** 2. Redistributions in binary form must reproduce the above copyright
28 ** notice, this list of conditions and the following disclaimer in the
29 ** documentation and/or other materials provided with the distribution.
30 ** 3. The name of the author may not be used to endorse or promote products
31 ** derived from this software without specific prior written permission.
32 **
33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *******************************************************************************
44 */
45 #include <linux/interrupt.h>
46 struct device_attribute;
47 /*The limit of outstanding scsi command that firmware can handle*/
48 #define ARCMSR_MAX_FREECCB_NUM 1024
49 #define ARCMSR_MAX_OUTSTANDING_CMD 1024
50 #define ARCMSR_DEFAULT_OUTSTANDING_CMD 128
51 #define ARCMSR_MIN_OUTSTANDING_CMD 32
52 #define ARCMSR_DRIVER_VERSION "v1.50.00.02-20200819"
53 #define ARCMSR_SCSI_INITIATOR_ID 255
54 #define ARCMSR_MAX_XFER_SECTORS 512
55 #define ARCMSR_MAX_XFER_SECTORS_B 4096
56 #define ARCMSR_MAX_XFER_SECTORS_C 304
57 #define ARCMSR_MAX_TARGETID 17
58 #define ARCMSR_MAX_TARGETLUN 8
59 #define ARCMSR_MAX_CMD_PERLUN 128
60 #define ARCMSR_DEFAULT_CMD_PERLUN 32
61 #define ARCMSR_MIN_CMD_PERLUN 1
62 #define ARCMSR_MAX_QBUFFER 4096
63 #define ARCMSR_DEFAULT_SG_ENTRIES 38
64 #define ARCMSR_MAX_HBB_POSTQUEUE 264
65 #define ARCMSR_MAX_ARC1214_POSTQUEUE 256
66 #define ARCMSR_MAX_ARC1214_DONEQUEUE 257
67 #define ARCMSR_MAX_HBE_DONEQUEUE 512
68 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
69 #define ARCMSR_CDB_SG_PAGE_LENGTH 256
70 #define ARCMST_NUM_MSIX_VECTORS 4
71 #ifndef PCI_DEVICE_ID_ARECA_1880
72 #define PCI_DEVICE_ID_ARECA_1880 0x1880
73 #endif
74 #ifndef PCI_DEVICE_ID_ARECA_1214
75 #define PCI_DEVICE_ID_ARECA_1214 0x1214
76 #endif
77 #ifndef PCI_DEVICE_ID_ARECA_1203
78 #define PCI_DEVICE_ID_ARECA_1203 0x1203
79 #endif
80 #ifndef PCI_DEVICE_ID_ARECA_1884
81 #define PCI_DEVICE_ID_ARECA_1884 0x1884
82 #endif
83 #define PCI_DEVICE_ID_ARECA_1886 0x188A
84 #define ARCMSR_HOURS (1000 * 60 * 60 * 4)
85 #define ARCMSR_MINUTES (1000 * 60 * 60)
86 #define ARCMSR_DEFAULT_TIMEOUT 90
87 /*
88 **********************************************************************************
89 **
90 **********************************************************************************
91 */
92 #define ARC_SUCCESS 0
93 #define ARC_FAILURE 1
94 /*
95 *******************************************************************************
96 ** split 64bits dma addressing
97 *******************************************************************************
98 */
99 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
100 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
101 /*
102 *******************************************************************************
103 ** MESSAGE CONTROL CODE
104 *******************************************************************************
105 */
106 struct CMD_MESSAGE
107 {
108 uint32_t HeaderLength;
109 uint8_t Signature[8];
110 uint32_t Timeout;
111 uint32_t ControlCode;
112 uint32_t ReturnCode;
113 uint32_t Length;
114 };
115 /*
116 *******************************************************************************
117 ** IOP Message Transfer Data for user space
118 *******************************************************************************
119 */
120 #define ARCMSR_API_DATA_BUFLEN 1032
121 struct CMD_MESSAGE_FIELD
122 {
123 struct CMD_MESSAGE cmdmessage;
124 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN];
125 };
126 /* IOP message transfer */
127 #define ARCMSR_MESSAGE_FAIL 0x0001
128 /* DeviceType */
129 #define ARECA_SATA_RAID 0x90000000
130 /* FunctionCode */
131 #define FUNCTION_READ_RQBUFFER 0x0801
132 #define FUNCTION_WRITE_WQBUFFER 0x0802
133 #define FUNCTION_CLEAR_RQBUFFER 0x0803
134 #define FUNCTION_CLEAR_WQBUFFER 0x0804
135 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
136 #define FUNCTION_RETURN_CODE_3F 0x0806
137 #define FUNCTION_SAY_HELLO 0x0807
138 #define FUNCTION_SAY_GOODBYE 0x0808
139 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
140 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A
141 #define FUNCTION_HARDWARE_RESET 0x080B
142 /* ARECA IO CONTROL CODE*/
143 #define ARCMSR_MESSAGE_READ_RQBUFFER \
144 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
145 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \
146 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
147 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
148 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
149 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
150 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
151 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
152 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
153 #define ARCMSR_MESSAGE_RETURN_CODE_3F \
154 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
155 #define ARCMSR_MESSAGE_SAY_HELLO \
156 ARECA_SATA_RAID | FUNCTION_SAY_HELLO
157 #define ARCMSR_MESSAGE_SAY_GOODBYE \
158 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
159 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
160 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
161 /* ARECA IOCTL ReturnCode */
162 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
163 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
164 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
165 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
166 /*
167 *************************************************************
168 ** structure for holding DMA address data
169 *************************************************************
170 */
171 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
172 #define IS_SG64_ADDR 0x01000000 /* bit24 */
173 struct SG32ENTRY
174 {
175 __le32 length;
176 __le32 address;
177 }__attribute__ ((packed));
178 struct SG64ENTRY
179 {
180 __le32 length;
181 __le32 address;
182 __le32 addresshigh;
183 }__attribute__ ((packed));
184 /*
185 ********************************************************************
186 ** Q Buffer of IOP Message Transfer
187 ********************************************************************
188 */
189 struct QBUFFER
190 {
191 uint32_t data_len;
192 uint8_t data[124];
193 };
194 /*
195 *******************************************************************************
196 ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
197 *******************************************************************************
198 */
199 struct FIRMWARE_INFO
200 {
201 uint32_t signature; /*0, 00-03*/
202 uint32_t request_len; /*1, 04-07*/
203 uint32_t numbers_queue; /*2, 08-11*/
204 uint32_t sdram_size; /*3, 12-15*/
205 uint32_t ide_channels; /*4, 16-19*/
206 char vendor[40]; /*5, 20-59*/
207 char model[8]; /*15, 60-67*/
208 char firmware_ver[16]; /*17, 68-83*/
209 char device_map[16]; /*21, 84-99*/
210 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
211 uint8_t cfgSerial[16]; /*26,104-119*/
212 uint32_t cfgPicStatus; /*30,120-123*/
213 };
214 /* signature of set and get firmware config */
215 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
216 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
217 /* message code of inbound message register */
218 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
219 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
220 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
221 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
222 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
223 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
224 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
225 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
226 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
227 /* doorbell interrupt generator */
228 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
229 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
230 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
231 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
232 /* ccb areca cdb flag */
233 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
234 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
235 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
236 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
237 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
238 /* outbound firmware ok */
239 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
240 /* ARC-1680 Bus Reset*/
241 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
242 /* ARC-1880 Bus Reset*/
243 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
244 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
245
246 /*
247 ************************************************************************
248 ** SPEC. for Areca Type B adapter
249 ************************************************************************
250 */
251 /* ARECA HBB COMMAND for its FIRMWARE */
252 /* window of "instruction flags" from driver to iop */
253 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400
254 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
255 /* window of "instruction flags" from iop to driver */
256 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408
257 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
258 /* window of "instruction flags" from iop to driver */
259 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870
260 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
261 /* window of "instruction flags" from driver to iop */
262 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878
263 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
264 /* ARECA FLAG LANGUAGE */
265 /* ioctl transfer */
266 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
267 /* ioctl transfer */
268 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
269 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
270 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
271
272 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
273 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
274 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
275 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
276 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
277 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
278 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
279 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
280 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
281 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
282 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
283 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
284 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
285 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
286 #define ARCMSR_MESSAGE_START_BGRB 0x00060008
287 #define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
288 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
289 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
290 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
291 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
292 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
293 /* ioctl transfer */
294 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
295 /* ioctl transfer */
296 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
297 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
298 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
299 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
300
301 /* data tunnel buffer between user space program and its firmware */
302 /* user space data to iop 128bytes */
303 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
304 /* iop data to user space 128bytes */
305 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
306 /* iop message_rwbuffer for message command */
307 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
308
309 #define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x)
310 #define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x)
311 /*
312 ************************************************************************
313 ** SPEC. for Areca HBC adapter
314 ************************************************************************
315 */
316 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
317 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
318 /* Host Interrupt Mask */
319 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
320 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
321 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
322 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
323 /* Host Interrupt Status */
324 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
325 /*
326 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
327 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
328 */
329 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
330 /*
331 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
332 ** value. This bit clears only when Outbound Doorbell bits
333 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
334 ** Clear register clears bits in the Outbound Doorbell register.
335 */
336 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
337 /*
338 ** Set whenever the Outbound Post List Producer/Consumer
339 ** Register (FIFO) is not empty. It clears when the Outbound
340 ** Post List FIFO is empty.
341 */
342 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
343 /*
344 ** This bit indicates a SAS interrupt from a source external to
345 ** the PCIe core. This bit is not maskable.
346 */
347 /* DoorBell*/
348 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
349 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
350 /*inbound message 0 ready*/
351 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
352 /*more than 12 request completed in a time*/
353 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
354 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
355 /*outbound DATA WRITE isr door bell clear*/
356 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
357 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
358 /*outbound DATA READ isr door bell clear*/
359 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
360 /*outbound message 0 ready*/
361 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
362 /*outbound message cmd isr door bell clear*/
363 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
364 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
365 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
366 /*
367 *******************************************************************************
368 ** SPEC. for Areca Type D adapter
369 *******************************************************************************
370 */
371 #define ARCMSR_ARC1214_CHIP_ID 0x00004
372 #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
373 #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
374 #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
375 #define ARCMSR_ARC1214_RESET_REQUEST 0x00108
376 #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
377 #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
378 #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
379 #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
380 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
381 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
382 #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
383 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
384 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
385 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
386 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
387 #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
388 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
389 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
390 #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
391 #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
392 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
393 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
394 #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
395 #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
396 #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
397 /* Host Interrupt Mask */
398 #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
399 #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
400 /* Host Interrupt Status */
401 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
402 #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
403 /* DoorBell*/
404 #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
405 #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
406 /*inbound message 0 ready*/
407 #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
408 /*outbound DATA WRITE isr door bell clear*/
409 #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
410 /*outbound message 0 ready*/
411 #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
412 /*outbound message cmd isr door bell clear*/
413 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
414 #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
415 #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
416 /*
417 *******************************************************************************
418 ** SPEC. for Areca Type E adapter
419 *******************************************************************************
420 */
421 #define ARCMSR_SIGNATURE_1884 0x188417D3
422
423 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
424 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
425 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
426
427 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
428 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
429 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
430
431 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000
432
433 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
434 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
435 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009
436
437 /* ARC-1884 doorbell sync */
438 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
439 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
440 #define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080
441
442 /*
443 *******************************************************************************
444 ** SPEC. for Areca Type F adapter
445 *******************************************************************************
446 */
447 #define ARCMSR_SIGNATURE_1886 0x188617D3
448 // Doorbell and interrupt definition are same as Type E adapter
449 /* ARC-1886 doorbell sync */
450 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
451 //set host rw buffer physical address at inbound message 0, 1 (low,high)
452 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
453 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
454 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
455
456 /*
457 *******************************************************************************
458 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
459 *******************************************************************************
460 */
461 struct ARCMSR_CDB
462 {
463 uint8_t Bus;
464 uint8_t TargetID;
465 uint8_t LUN;
466 uint8_t Function;
467 uint8_t CdbLength;
468 uint8_t sgcount;
469 uint8_t Flags;
470 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
471 #define ARCMSR_CDB_FLAG_BIOS 0x02
472 #define ARCMSR_CDB_FLAG_WRITE 0x04
473 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
474 #define ARCMSR_CDB_FLAG_HEADQ 0x08
475 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
476
477 uint8_t msgPages;
478 uint32_t msgContext;
479 uint32_t DataLength;
480 uint8_t Cdb[16];
481 uint8_t DeviceStatus;
482 #define ARCMSR_DEV_CHECK_CONDITION 0x02
483 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
484 #define ARCMSR_DEV_ABORTED 0xF1
485 #define ARCMSR_DEV_INIT_FAIL 0xF2
486
487 uint8_t SenseData[15];
488 union
489 {
490 struct SG32ENTRY sg32entry[1];
491 struct SG64ENTRY sg64entry[1];
492 } u;
493 };
494 /*
495 *******************************************************************************
496 ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
497 *******************************************************************************
498 */
499 struct MessageUnit_A
500 {
501 uint32_t resrved0[4]; /*0000 000F*/
502 uint32_t inbound_msgaddr0; /*0010 0013*/
503 uint32_t inbound_msgaddr1; /*0014 0017*/
504 uint32_t outbound_msgaddr0; /*0018 001B*/
505 uint32_t outbound_msgaddr1; /*001C 001F*/
506 uint32_t inbound_doorbell; /*0020 0023*/
507 uint32_t inbound_intstatus; /*0024 0027*/
508 uint32_t inbound_intmask; /*0028 002B*/
509 uint32_t outbound_doorbell; /*002C 002F*/
510 uint32_t outbound_intstatus; /*0030 0033*/
511 uint32_t outbound_intmask; /*0034 0037*/
512 uint32_t reserved1[2]; /*0038 003F*/
513 uint32_t inbound_queueport; /*0040 0043*/
514 uint32_t outbound_queueport; /*0044 0047*/
515 uint32_t reserved2[2]; /*0048 004F*/
516 uint32_t reserved3[492]; /*0050 07FF 492*/
517 uint32_t reserved4[128]; /*0800 09FF 128*/
518 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
519 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
520 uint32_t reserved5[32]; /*0E80 0EFF 32*/
521 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
522 uint32_t reserved6[32]; /*0F80 0FFF 32*/
523 };
524
525 struct MessageUnit_B
526 {
527 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
528 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
529 uint32_t postq_index;
530 uint32_t doneq_index;
531 uint32_t __iomem *drv2iop_doorbell;
532 uint32_t __iomem *drv2iop_doorbell_mask;
533 uint32_t __iomem *iop2drv_doorbell;
534 uint32_t __iomem *iop2drv_doorbell_mask;
535 uint32_t __iomem *message_rwbuffer;
536 uint32_t __iomem *message_wbuffer;
537 uint32_t __iomem *message_rbuffer;
538 };
539 /*
540 *********************************************************************
541 ** LSI
542 *********************************************************************
543 */
544 struct MessageUnit_C{
545 uint32_t message_unit_status; /*0000 0003*/
546 uint32_t slave_error_attribute; /*0004 0007*/
547 uint32_t slave_error_address; /*0008 000B*/
548 uint32_t posted_outbound_doorbell; /*000C 000F*/
549 uint32_t master_error_attribute; /*0010 0013*/
550 uint32_t master_error_address_low; /*0014 0017*/
551 uint32_t master_error_address_high; /*0018 001B*/
552 uint32_t hcb_size; /*001C 001F*/
553 uint32_t inbound_doorbell; /*0020 0023*/
554 uint32_t diagnostic_rw_data; /*0024 0027*/
555 uint32_t diagnostic_rw_address_low; /*0028 002B*/
556 uint32_t diagnostic_rw_address_high; /*002C 002F*/
557 uint32_t host_int_status; /*0030 0033*/
558 uint32_t host_int_mask; /*0034 0037*/
559 uint32_t dcr_data; /*0038 003B*/
560 uint32_t dcr_address; /*003C 003F*/
561 uint32_t inbound_queueport; /*0040 0043*/
562 uint32_t outbound_queueport; /*0044 0047*/
563 uint32_t hcb_pci_address_low; /*0048 004B*/
564 uint32_t hcb_pci_address_high; /*004C 004F*/
565 uint32_t iop_int_status; /*0050 0053*/
566 uint32_t iop_int_mask; /*0054 0057*/
567 uint32_t iop_inbound_queue_port; /*0058 005B*/
568 uint32_t iop_outbound_queue_port; /*005C 005F*/
569 uint32_t inbound_free_list_index; /*0060 0063*/
570 uint32_t inbound_post_list_index; /*0064 0067*/
571 uint32_t outbound_free_list_index; /*0068 006B*/
572 uint32_t outbound_post_list_index; /*006C 006F*/
573 uint32_t inbound_doorbell_clear; /*0070 0073*/
574 uint32_t i2o_message_unit_control; /*0074 0077*/
575 uint32_t last_used_message_source_address_low; /*0078 007B*/
576 uint32_t last_used_message_source_address_high; /*007C 007F*/
577 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
578 uint32_t message_dest_address_index; /*0090 0093*/
579 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
580 uint32_t utility_A_int_counter_timer; /*0098 009B*/
581 uint32_t outbound_doorbell; /*009C 009F*/
582 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
583 uint32_t message_source_address_index; /*00A4 00A7*/
584 uint32_t message_done_queue_index; /*00A8 00AB*/
585 uint32_t reserved0; /*00AC 00AF*/
586 uint32_t inbound_msgaddr0; /*00B0 00B3*/
587 uint32_t inbound_msgaddr1; /*00B4 00B7*/
588 uint32_t outbound_msgaddr0; /*00B8 00BB*/
589 uint32_t outbound_msgaddr1; /*00BC 00BF*/
590 uint32_t inbound_queueport_low; /*00C0 00C3*/
591 uint32_t inbound_queueport_high; /*00C4 00C7*/
592 uint32_t outbound_queueport_low; /*00C8 00CB*/
593 uint32_t outbound_queueport_high; /*00CC 00CF*/
594 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
595 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
596 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
597 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
598 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
599 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
600 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
601 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
602 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
603 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
604 uint32_t host_diagnostic; /*00F8 00FB*/
605 uint32_t write_sequence; /*00FC 00FF*/
606 uint32_t reserved1[34]; /*0100 0187*/
607 uint32_t reserved2[1950]; /*0188 1FFF*/
608 uint32_t message_wbuffer[32]; /*2000 207F*/
609 uint32_t reserved3[32]; /*2080 20FF*/
610 uint32_t message_rbuffer[32]; /*2100 217F*/
611 uint32_t reserved4[32]; /*2180 21FF*/
612 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
613 };
614 /*
615 *********************************************************************
616 ** Messaging Unit (MU) of Type D processor
617 *********************************************************************
618 */
619 struct InBound_SRB {
620 uint32_t addressLow; /* pointer to SRB block */
621 uint32_t addressHigh;
622 uint32_t length; /* in DWORDs */
623 uint32_t reserved0;
624 };
625
626 struct OutBound_SRB {
627 uint32_t addressLow; /* pointer to SRB block */
628 uint32_t addressHigh;
629 };
630
631 struct MessageUnit_D {
632 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
633 volatile struct OutBound_SRB
634 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
635 u16 postq_index;
636 volatile u16 doneq_index;
637 u32 __iomem *chip_id; /* 0x00004 */
638 u32 __iomem *cpu_mem_config; /* 0x00008 */
639 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
640 u32 __iomem *sample_at_reset; /* 0x00100 */
641 u32 __iomem *reset_request; /* 0x00108 */
642 u32 __iomem *host_int_status; /* 0x00200 */
643 u32 __iomem *pcief0_int_enable; /* 0x0020C */
644 u32 __iomem *inbound_msgaddr0; /* 0x00400 */
645 u32 __iomem *inbound_msgaddr1; /* 0x00404 */
646 u32 __iomem *outbound_msgaddr0; /* 0x00420 */
647 u32 __iomem *outbound_msgaddr1; /* 0x00424 */
648 u32 __iomem *inbound_doorbell; /* 0x00460 */
649 u32 __iomem *outbound_doorbell; /* 0x00480 */
650 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
651 u32 __iomem *inboundlist_base_low; /* 0x01000 */
652 u32 __iomem *inboundlist_base_high; /* 0x01004 */
653 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
654 u32 __iomem *outboundlist_base_low; /* 0x01060 */
655 u32 __iomem *outboundlist_base_high; /* 0x01064 */
656 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
657 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
658 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
659 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
660 u32 __iomem *message_wbuffer; /* 0x2000 */
661 u32 __iomem *message_rbuffer; /* 0x2100 */
662 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
663 };
664 /*
665 *********************************************************************
666 ** Messaging Unit (MU) of Type E processor(LSI)
667 *********************************************************************
668 */
669 struct MessageUnit_E{
670 uint32_t iobound_doorbell; /*0000 0003*/
671 uint32_t write_sequence_3xxx; /*0004 0007*/
672 uint32_t host_diagnostic_3xxx; /*0008 000B*/
673 uint32_t posted_outbound_doorbell; /*000C 000F*/
674 uint32_t master_error_attribute; /*0010 0013*/
675 uint32_t master_error_address_low; /*0014 0017*/
676 uint32_t master_error_address_high; /*0018 001B*/
677 uint32_t hcb_size; /*001C 001F*/
678 uint32_t inbound_doorbell; /*0020 0023*/
679 uint32_t diagnostic_rw_data; /*0024 0027*/
680 uint32_t diagnostic_rw_address_low; /*0028 002B*/
681 uint32_t diagnostic_rw_address_high; /*002C 002F*/
682 uint32_t host_int_status; /*0030 0033*/
683 uint32_t host_int_mask; /*0034 0037*/
684 uint32_t dcr_data; /*0038 003B*/
685 uint32_t dcr_address; /*003C 003F*/
686 uint32_t inbound_queueport; /*0040 0043*/
687 uint32_t outbound_queueport; /*0044 0047*/
688 uint32_t hcb_pci_address_low; /*0048 004B*/
689 uint32_t hcb_pci_address_high; /*004C 004F*/
690 uint32_t iop_int_status; /*0050 0053*/
691 uint32_t iop_int_mask; /*0054 0057*/
692 uint32_t iop_inbound_queue_port; /*0058 005B*/
693 uint32_t iop_outbound_queue_port; /*005C 005F*/
694 uint32_t inbound_free_list_index; /*0060 0063*/
695 uint32_t inbound_post_list_index; /*0064 0067*/
696 uint32_t reply_post_producer_index; /*0068 006B*/
697 uint32_t reply_post_consumer_index; /*006C 006F*/
698 uint32_t inbound_doorbell_clear; /*0070 0073*/
699 uint32_t i2o_message_unit_control; /*0074 0077*/
700 uint32_t last_used_message_source_address_low; /*0078 007B*/
701 uint32_t last_used_message_source_address_high; /*007C 007F*/
702 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
703 uint32_t message_dest_address_index; /*0090 0093*/
704 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
705 uint32_t utility_A_int_counter_timer; /*0098 009B*/
706 uint32_t outbound_doorbell; /*009C 009F*/
707 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
708 uint32_t message_source_address_index; /*00A4 00A7*/
709 uint32_t message_done_queue_index; /*00A8 00AB*/
710 uint32_t reserved0; /*00AC 00AF*/
711 uint32_t inbound_msgaddr0; /*00B0 00B3*/
712 uint32_t inbound_msgaddr1; /*00B4 00B7*/
713 uint32_t outbound_msgaddr0; /*00B8 00BB*/
714 uint32_t outbound_msgaddr1; /*00BC 00BF*/
715 uint32_t inbound_queueport_low; /*00C0 00C3*/
716 uint32_t inbound_queueport_high; /*00C4 00C7*/
717 uint32_t outbound_queueport_low; /*00C8 00CB*/
718 uint32_t outbound_queueport_high; /*00CC 00CF*/
719 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
720 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
721 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
722 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
723 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
724 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
725 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
726 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
727 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
728 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
729 uint32_t host_diagnostic; /*00F8 00FB*/
730 uint32_t write_sequence; /*00FC 00FF*/
731 uint32_t reserved1[34]; /*0100 0187*/
732 uint32_t reserved2[1950]; /*0188 1FFF*/
733 uint32_t message_wbuffer[32]; /*2000 207F*/
734 uint32_t reserved3[32]; /*2080 20FF*/
735 uint32_t message_rbuffer[32]; /*2100 217F*/
736 uint32_t reserved4[32]; /*2180 21FF*/
737 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
738 };
739
740 /*
741 *********************************************************************
742 ** Messaging Unit (MU) of Type F processor(LSI)
743 *********************************************************************
744 */
745 struct MessageUnit_F {
746 uint32_t iobound_doorbell; /*0000 0003*/
747 uint32_t write_sequence_3xxx; /*0004 0007*/
748 uint32_t host_diagnostic_3xxx; /*0008 000B*/
749 uint32_t posted_outbound_doorbell; /*000C 000F*/
750 uint32_t master_error_attribute; /*0010 0013*/
751 uint32_t master_error_address_low; /*0014 0017*/
752 uint32_t master_error_address_high; /*0018 001B*/
753 uint32_t hcb_size; /*001C 001F*/
754 uint32_t inbound_doorbell; /*0020 0023*/
755 uint32_t diagnostic_rw_data; /*0024 0027*/
756 uint32_t diagnostic_rw_address_low; /*0028 002B*/
757 uint32_t diagnostic_rw_address_high; /*002C 002F*/
758 uint32_t host_int_status; /*0030 0033*/
759 uint32_t host_int_mask; /*0034 0037*/
760 uint32_t dcr_data; /*0038 003B*/
761 uint32_t dcr_address; /*003C 003F*/
762 uint32_t inbound_queueport; /*0040 0043*/
763 uint32_t outbound_queueport; /*0044 0047*/
764 uint32_t hcb_pci_address_low; /*0048 004B*/
765 uint32_t hcb_pci_address_high; /*004C 004F*/
766 uint32_t iop_int_status; /*0050 0053*/
767 uint32_t iop_int_mask; /*0054 0057*/
768 uint32_t iop_inbound_queue_port; /*0058 005B*/
769 uint32_t iop_outbound_queue_port; /*005C 005F*/
770 uint32_t inbound_free_list_index; /*0060 0063*/
771 uint32_t inbound_post_list_index; /*0064 0067*/
772 uint32_t reply_post_producer_index; /*0068 006B*/
773 uint32_t reply_post_consumer_index; /*006C 006F*/
774 uint32_t inbound_doorbell_clear; /*0070 0073*/
775 uint32_t i2o_message_unit_control; /*0074 0077*/
776 uint32_t last_used_message_source_address_low; /*0078 007B*/
777 uint32_t last_used_message_source_address_high; /*007C 007F*/
778 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
779 uint32_t message_dest_address_index; /*0090 0093*/
780 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
781 uint32_t utility_A_int_counter_timer; /*0098 009B*/
782 uint32_t outbound_doorbell; /*009C 009F*/
783 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
784 uint32_t message_source_address_index; /*00A4 00A7*/
785 uint32_t message_done_queue_index; /*00A8 00AB*/
786 uint32_t reserved0; /*00AC 00AF*/
787 uint32_t inbound_msgaddr0; /*00B0 00B3*/
788 uint32_t inbound_msgaddr1; /*00B4 00B7*/
789 uint32_t outbound_msgaddr0; /*00B8 00BB*/
790 uint32_t outbound_msgaddr1; /*00BC 00BF*/
791 uint32_t inbound_queueport_low; /*00C0 00C3*/
792 uint32_t inbound_queueport_high; /*00C4 00C7*/
793 uint32_t outbound_queueport_low; /*00C8 00CB*/
794 uint32_t outbound_queueport_high; /*00CC 00CF*/
795 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
796 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
797 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
798 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
799 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
800 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
801 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
802 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
803 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
804 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
805 uint32_t host_diagnostic; /*00F8 00FB*/
806 uint32_t write_sequence; /*00FC 00FF*/
807 uint32_t reserved1[46]; /*0100 01B7*/
808 uint32_t reply_post_producer_index1; /*01B8 01BB*/
809 uint32_t reply_post_consumer_index1; /*01BC 01BF*/
810 };
811
812 #define MESG_RW_BUFFER_SIZE (256 * 3)
813
814 typedef struct deliver_completeQ {
815 uint16_t cmdFlag;
816 uint16_t cmdSMID;
817 uint16_t cmdLMID; // reserved (0)
818 uint16_t cmdFlag2; // reserved (0)
819 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
820 /*
821 *******************************************************************************
822 ** Adapter Control Block
823 *******************************************************************************
824 */
825 struct AdapterControlBlock
826 {
827 uint32_t adapter_type; /* adapter A,B..... */
828 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
829 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
830 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
831 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
832 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
833 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */
834 u32 ioqueue_size;
835 struct pci_dev * pdev;
836 struct Scsi_Host * host;
837 unsigned long vir2phy_offset;
838 /* Offset is used in making arc cdb physical to virtual calculations */
839 uint32_t outbound_int_enable;
840 uint32_t cdb_phyaddr_hi32;
841 uint32_t reg_mu_acc_handle0;
842 uint64_t cdb_phyadd_hipart;
843 spinlock_t eh_lock;
844 spinlock_t ccblist_lock;
845 spinlock_t postq_lock;
846 spinlock_t doneq_lock;
847 spinlock_t rqbuffer_lock;
848 spinlock_t wqbuffer_lock;
849 union {
850 struct MessageUnit_A __iomem *pmuA;
851 struct MessageUnit_B *pmuB;
852 struct MessageUnit_C __iomem *pmuC;
853 struct MessageUnit_D *pmuD;
854 struct MessageUnit_E __iomem *pmuE;
855 struct MessageUnit_F __iomem *pmuF;
856 };
857 /* message unit ATU inbound base address0 */
858 void __iomem *mem_base0;
859 void __iomem *mem_base1;
860 //0x000 - COMPORT_IN (Host sent to ROC)
861 uint32_t *message_wbuffer;
862 //0x100 - COMPORT_OUT (ROC sent to Host)
863 uint32_t *message_rbuffer;
864 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
865 uint32_t acb_flags;
866 u16 dev_id;
867 uint8_t adapter_index;
868 #define ACB_F_SCSISTOPADAPTER 0x0001
869 #define ACB_F_MSG_STOP_BGRB 0x0002
870 /* stop RAID background rebuild */
871 #define ACB_F_MSG_START_BGRB 0x0004
872 /* stop RAID background rebuild */
873 #define ACB_F_IOPDATA_OVERFLOW 0x0008
874 /* iop message data rqbuffer overflow */
875 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
876 /* message clear wqbuffer */
877 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
878 /* message clear rqbuffer */
879 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
880 #define ACB_F_BUS_RESET 0x0080
881
882 #define ACB_F_IOP_INITED 0x0100
883 /* iop init */
884 #define ACB_F_ABORT 0x0200
885 #define ACB_F_FIRMWARE_TRAP 0x0400
886 #define ACB_F_ADAPTER_REMOVED 0x0800
887 #define ACB_F_MSG_GET_CONFIG 0x1000
888 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
889 /* used for memory free */
890 struct list_head ccb_free_list;
891 /* head of free ccb list */
892
893 atomic_t ccboutstandingcount;
894 /*The present outstanding command number that in the IOP that
895 waiting for being handled by FW*/
896
897 void * dma_coherent;
898 /* dma_coherent used for memory free */
899 dma_addr_t dma_coherent_handle;
900 /* dma_coherent_handle used for memory free */
901 dma_addr_t dma_coherent_handle2;
902 void *dma_coherent2;
903 unsigned int uncache_size;
904 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
905 /* data collection buffer for read from 80331 */
906 int32_t rqbuf_getIndex;
907 /* first of read buffer */
908 int32_t rqbuf_putIndex;
909 /* last of read buffer */
910 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
911 /* data collection buffer for write to 80331 */
912 int32_t wqbuf_getIndex;
913 /* first of write buffer */
914 int32_t wqbuf_putIndex;
915 /* last of write buffer */
916 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
917 /* id0 ..... id15, lun0...lun7 */
918 #define ARECA_RAID_GONE 0x55
919 #define ARECA_RAID_GOOD 0xaa
920 uint32_t num_resets;
921 uint32_t num_aborts;
922 uint32_t signature;
923 uint32_t firm_request_len;
924 uint32_t firm_numbers_queue;
925 uint32_t firm_sdram_size;
926 uint32_t firm_hd_channels;
927 uint32_t firm_cfg_version;
928 char firm_model[12];
929 char firm_version[20];
930 char device_map[20]; /*21,84-99*/
931 struct work_struct arcmsr_do_message_isr_bh;
932 struct timer_list eternal_timer;
933 unsigned short fw_flag;
934 #define FW_NORMAL 0x0000
935 #define FW_BOG 0x0001
936 #define FW_DEADLOCK 0x0010
937 uint32_t maxOutstanding;
938 int vector_count;
939 uint32_t maxFreeCCB;
940 struct timer_list refresh_timer;
941 uint32_t doneq_index;
942 uint32_t ccbsize;
943 uint32_t in_doorbell;
944 uint32_t out_doorbell;
945 uint32_t completionQ_entry;
946 pCompletion_Q pCompletionQ;
947 uint32_t completeQ_size;
948 };/* HW_DEVICE_EXTENSION */
949 /*
950 *******************************************************************************
951 ** Command Control Block
952 ** this CCB length must be 32 bytes boundary
953 *******************************************************************************
954 */
955 struct CommandControlBlock{
956 /*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
957 struct list_head list; /*x32: 8byte, x64: 16byte*/
958 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
959 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
960 unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/
961 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
962 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
963 #define CCB_FLAG_READ 0x0000
964 #define CCB_FLAG_WRITE 0x0001
965 #define CCB_FLAG_ERROR 0x0002
966 #define CCB_FLAG_FLUSHCACHE 0x0004
967 #define CCB_FLAG_MASTER_ABORTED 0x0008
968 uint16_t startdone; /*x32:2byte,x32:2byte*/
969 #define ARCMSR_CCB_DONE 0x0000
970 #define ARCMSR_CCB_START 0x55AA
971 #define ARCMSR_CCB_ABORTED 0xAA55
972 #define ARCMSR_CCB_ILLEGAL 0xFFFF
973 uint32_t smid;
974 #if BITS_PER_LONG == 64
975 /* ======================512+64 bytes======================== */
976 uint32_t reserved[3]; /*12 byte*/
977 #else
978 /* ======================512+32 bytes======================== */
979 uint32_t reserved[8]; /*32 byte*/
980 #endif
981 /* ======================================================= */
982 struct ARCMSR_CDB arcmsr_cdb;
983 };
984 /*
985 *******************************************************************************
986 ** ARECA SCSI sense data
987 *******************************************************************************
988 */
989 struct SENSE_DATA
990 {
991 uint8_t ErrorCode:7;
992 #define SCSI_SENSE_CURRENT_ERRORS 0x70
993 #define SCSI_SENSE_DEFERRED_ERRORS 0x71
994 uint8_t Valid:1;
995 uint8_t SegmentNumber;
996 uint8_t SenseKey:4;
997 uint8_t Reserved:1;
998 uint8_t IncorrectLength:1;
999 uint8_t EndOfMedia:1;
1000 uint8_t FileMark:1;
1001 uint8_t Information[4];
1002 uint8_t AdditionalSenseLength;
1003 uint8_t CommandSpecificInformation[4];
1004 uint8_t AdditionalSenseCode;
1005 uint8_t AdditionalSenseCodeQualifier;
1006 uint8_t FieldReplaceableUnitCode;
1007 uint8_t SenseKeySpecific[3];
1008 };
1009 /*
1010 *******************************************************************************
1011 ** Outbound Interrupt Status Register - OISR
1012 *******************************************************************************
1013 */
1014 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
1015 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
1016 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
1017 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
1018 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
1019 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
1020 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \
1021 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
1022 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
1023 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \
1024 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
1025 |ARCMSR_MU_OUTBOUND_PCI_INT)
1026 /*
1027 *******************************************************************************
1028 ** Outbound Interrupt Mask Register - OIMR
1029 *******************************************************************************
1030 */
1031 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
1032 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
1033 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
1034 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
1035 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
1036 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
1037 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
1038
1039 extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
1040 extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
1041 struct QBUFFER __iomem *);
1042 extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *);
1043 extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
1044 extern struct device_attribute *arcmsr_host_attrs[];
1045 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
1046 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
Linux with added FPC-III support