drivers/scsi/mpt3sas/mpi/mpi2_pci.h

   1 /*
   2  * Copyright 2000-2020 Broadcom Inc. All rights reserved.
   3  *
   4  *
   5  *          Name:  mpi2_pci.h
   6  *         Title:  MPI PCIe Attached Devices structures and definitions.
   7  * Creation Date:  October 9, 2012
   8  *
   9  * mpi2_pci.h Version:  02.00.04
  10  *
  11  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  12  *       prefix are for use only on MPI v2.5 products, and must not be used
  13  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
  14  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  15  *
  16  * Version History
  17  * ---------------
  18  *
  19  * Date      Version   Description
  20  * --------  --------  ------------------------------------------------------
  21  * 03-16-15  02.00.00  Initial version.
  22  * 02-17-16  02.00.01  Removed AHCI support.
  23  *                     Removed SOP support.
  24  * 07-01-16  02.00.02  Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to
  25  *                     NVME Encapsulated Request.
  26  * 07-22-18  02.00.03  Updted flags field for NVME Encapsulated req
  27  * 12-17-18  02.00.04  Added MPI26_PCIE_DEVINFO_SCSI
  28  *                      Shortten some defines to be compatible with DOS
  29  * --------------------------------------------------------------------------
  30  */
  31
  32 #ifndef MPI2_PCI_H
  33 #define MPI2_PCI_H
  34
  35
  36 /*
  37  *Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event
  38  *data and PCIe Configuration pages.
  39  */
  40 #define MPI26_PCIE_DEVINFO_DIRECT_ATTACH        (0x00000010)
  41
  42 #define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE     (0x0000000F)
  43 #define MPI26_PCIE_DEVINFO_NO_DEVICE            (0x00000000)
  44 #define MPI26_PCIE_DEVINFO_PCI_SWITCH           (0x00000001)
  45 #define MPI26_PCIE_DEVINFO_NVME                 (0x00000003)
  46 #define MPI26_PCIE_DEVINFO_SCSI                 (0x00000004)
  47
  48 /****************************************************************************
  49 *  NVMe Encapsulated message
  50 ****************************************************************************/
  51
  52 /*NVME Encapsulated Request Message */
  53 typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST {
  54         U16     DevHandle;                      /*0x00 */
  55         U8      ChainOffset;                    /*0x02 */
  56         U8      Function;                       /*0x03 */
  57         U16     EncapsulatedCommandLength;      /*0x04 */
  58         U8      Reserved1;                      /*0x06 */
  59         U8      MsgFlags;                       /*0x07 */
  60         U8      VP_ID;                          /*0x08 */
  61         U8      VF_ID;                          /*0x09 */
  62         U16     Reserved2;                      /*0x0A */
  63         U32     Reserved3;                      /*0x0C */
  64         U64     ErrorResponseBaseAddress;       /*0x10 */
  65         U16     ErrorResponseAllocationLength;  /*0x18 */
  66         U16     Flags;                          /*0x1A */
  67         U32     DataLength;                     /*0x1C */
  68         U8      NVMe_Command[4];                /*0x20 */
  69
  70 } MPI26_NVME_ENCAPSULATED_REQUEST, *PTR_MPI26_NVME_ENCAPSULATED_REQUEST,
  71         Mpi26NVMeEncapsulatedRequest_t, *pMpi26NVMeEncapsulatedRequest_t;
  72
  73 /*defines for the Flags field */
  74 #define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP       (0x0020)
  75 /*Submission Queue Type*/
  76 #define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK           (0x0010)
  77 #define MPI26_NVME_FLAGS_SUBMISSIONQ_IO             (0x0000)
  78 #define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN          (0x0010)
  79 /*Error Response Address Space */
  80 #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_MASK          (0x000C)
  81 #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_SYSTEM        (0x0000)
  82 #define MPI26_NVME_FLAGS_ERR_RSP_ADDR_IOCTL         (0x0008)
  83 /* Data Direction*/
  84 #define MPI26_NVME_FLAGS_DATADIRECTION_MASK         (0x0003)
  85 #define MPI26_NVME_FLAGS_NODATATRANSFER             (0x0000)
  86 #define MPI26_NVME_FLAGS_WRITE                      (0x0001)
  87 #define MPI26_NVME_FLAGS_READ                       (0x0002)
  88 #define MPI26_NVME_FLAGS_BIDIRECTIONAL              (0x0003)
  89
  90
  91 /*NVMe Encapuslated Reply Message */
  92 typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY {
  93         U16     DevHandle;                      /*0x00 */
  94         U8      MsgLength;                      /*0x02 */
  95         U8      Function;                       /*0x03 */
  96         U16     EncapsulatedCommandLength;      /*0x04 */
  97         U8      Reserved1;                      /*0x06 */
  98         U8      MsgFlags;                       /*0x07 */
  99         U8      VP_ID;                          /*0x08 */
 100         U8      VF_ID;                          /*0x09 */
 101         U16     Reserved2;                      /*0x0A */
 102         U16     Reserved3;                      /*0x0C */
 103         U16     IOCStatus;                      /*0x0E */
 104         U32     IOCLogInfo;                     /*0x10 */
 105         U16     ErrorResponseCount;             /*0x14 */
 106         U16     Reserved4;                      /*0x16 */
 107 } MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
 108         *PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
 109         Mpi26NVMeEncapsulatedErrorReply_t,
 110         *pMpi26NVMeEncapsulatedErrorReply_t;
 111
 112
 113 #endif