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WIP FPC-III support
[linux/fpc-iii.git] / drivers / scsi / mvsas / mv_init.c
blob6aa2697c4a15d24adabdb308c762258a9e4d7337
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Marvell 88SE64xx/88SE94xx pci init
4 *
5 * Copyright 2007 Red Hat, Inc.
6 * Copyright 2008 Marvell. <kewei@marvell.com>
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 */
9
10
11 #include "mv_sas.h"
12
13 int interrupt_coalescing = 0x80;
14
15 static struct scsi_transport_template *mvs_stt;
16 static const struct mvs_chip_info mvs_chips[] = {
17 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
18 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
19 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
20 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
21 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
22 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
23 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
24 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
25 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
26 };
27
28 static struct device_attribute *mvst_host_attrs[];
29
30 #define SOC_SAS_NUM 2
31
32 static struct scsi_host_template mvs_sht = {
33 .module = THIS_MODULE,
34 .name = DRV_NAME,
35 .queuecommand = sas_queuecommand,
36 .dma_need_drain = ata_scsi_dma_need_drain,
37 .target_alloc = sas_target_alloc,
38 .slave_configure = sas_slave_configure,
39 .scan_finished = mvs_scan_finished,
40 .scan_start = mvs_scan_start,
41 .change_queue_depth = sas_change_queue_depth,
42 .bios_param = sas_bios_param,
43 .can_queue = 1,
44 .this_id = -1,
45 .sg_tablesize = SG_ALL,
46 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
47 .eh_device_reset_handler = sas_eh_device_reset_handler,
48 .eh_target_reset_handler = sas_eh_target_reset_handler,
49 .target_destroy = sas_target_destroy,
50 .ioctl = sas_ioctl,
51 #ifdef CONFIG_COMPAT
52 .compat_ioctl = sas_ioctl,
53 #endif
54 .shost_attrs = mvst_host_attrs,
55 .track_queue_depth = 1,
56 };
57
58 static struct sas_domain_function_template mvs_transport_ops = {
59 .lldd_dev_found = mvs_dev_found,
60 .lldd_dev_gone = mvs_dev_gone,
61 .lldd_execute_task = mvs_queue_command,
62 .lldd_control_phy = mvs_phy_control,
63
64 .lldd_abort_task = mvs_abort_task,
65 .lldd_abort_task_set = mvs_abort_task_set,
66 .lldd_clear_aca = mvs_clear_aca,
67 .lldd_clear_task_set = mvs_clear_task_set,
68 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
69 .lldd_lu_reset = mvs_lu_reset,
70 .lldd_query_task = mvs_query_task,
71 .lldd_port_formed = mvs_port_formed,
72 .lldd_port_deformed = mvs_port_deformed,
73
74 .lldd_write_gpio = mvs_gpio_write,
75
76 };
77
78 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
79 {
80 struct mvs_phy *phy = &mvi->phy[phy_id];
81 struct asd_sas_phy *sas_phy = &phy->sas_phy;
82
83 phy->mvi = mvi;
84 phy->port = NULL;
85 timer_setup(&phy->timer, NULL, 0);
86 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
87 sas_phy->class = SAS;
88 sas_phy->iproto = SAS_PROTOCOL_ALL;
89 sas_phy->tproto = 0;
90 sas_phy->type = PHY_TYPE_PHYSICAL;
91 sas_phy->role = PHY_ROLE_INITIATOR;
92 sas_phy->oob_mode = OOB_NOT_CONNECTED;
93 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
94
95 sas_phy->id = phy_id;
96 sas_phy->sas_addr = &mvi->sas_addr[0];
97 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
98 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
99 sas_phy->lldd_phy = phy;
100 }
101
102 static void mvs_free(struct mvs_info *mvi)
103 {
104 struct mvs_wq *mwq;
105 int slot_nr;
106
107 if (!mvi)
108 return;
109
110 if (mvi->flags & MVF_FLAG_SOC)
111 slot_nr = MVS_SOC_SLOTS;
112 else
113 slot_nr = MVS_CHIP_SLOT_SZ;
114
115 dma_pool_destroy(mvi->dma_pool);
116
117 if (mvi->tx)
118 dma_free_coherent(mvi->dev,
119 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
120 mvi->tx, mvi->tx_dma);
121 if (mvi->rx_fis)
122 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
123 mvi->rx_fis, mvi->rx_fis_dma);
124 if (mvi->rx)
125 dma_free_coherent(mvi->dev,
126 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
127 mvi->rx, mvi->rx_dma);
128 if (mvi->slot)
129 dma_free_coherent(mvi->dev,
130 sizeof(*mvi->slot) * slot_nr,
131 mvi->slot, mvi->slot_dma);
132
133 if (mvi->bulk_buffer)
134 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
135 mvi->bulk_buffer, mvi->bulk_buffer_dma);
136 if (mvi->bulk_buffer1)
137 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
138 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
139
140 MVS_CHIP_DISP->chip_iounmap(mvi);
141 if (mvi->shost)
142 scsi_host_put(mvi->shost);
143 list_for_each_entry(mwq, &mvi->wq_list, entry)
144 cancel_delayed_work(&mwq->work_q);
145 kfree(mvi->tags);
146 kfree(mvi);
147 }
148
149 #ifdef CONFIG_SCSI_MVSAS_TASKLET
150 static void mvs_tasklet(unsigned long opaque)
151 {
152 u32 stat;
153 u16 core_nr, i = 0;
154
155 struct mvs_info *mvi;
156 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
157
158 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
159 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
160
161 if (unlikely(!mvi))
162 BUG_ON(1);
163
164 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
165 if (!stat)
166 goto out;
167
168 for (i = 0; i < core_nr; i++) {
169 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
170 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
171 }
172 out:
173 MVS_CHIP_DISP->interrupt_enable(mvi);
174
175 }
176 #endif
177
178 static irqreturn_t mvs_interrupt(int irq, void *opaque)
179 {
180 u32 stat;
181 struct mvs_info *mvi;
182 struct sas_ha_struct *sha = opaque;
183 #ifndef CONFIG_SCSI_MVSAS_TASKLET
184 u32 i;
185 u32 core_nr;
186
187 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
188 #endif
189
190 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
191
192 if (unlikely(!mvi))
193 return IRQ_NONE;
194 #ifdef CONFIG_SCSI_MVSAS_TASKLET
195 MVS_CHIP_DISP->interrupt_disable(mvi);
196 #endif
197
198 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
199 if (!stat) {
200 #ifdef CONFIG_SCSI_MVSAS_TASKLET
201 MVS_CHIP_DISP->interrupt_enable(mvi);
202 #endif
203 return IRQ_NONE;
204 }
205
206 #ifdef CONFIG_SCSI_MVSAS_TASKLET
207 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
208 #else
209 for (i = 0; i < core_nr; i++) {
210 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
211 MVS_CHIP_DISP->isr(mvi, irq, stat);
212 }
213 #endif
214 return IRQ_HANDLED;
215 }
216
217 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
218 {
219 int i = 0, slot_nr;
220 char pool_name[32];
221
222 if (mvi->flags & MVF_FLAG_SOC)
223 slot_nr = MVS_SOC_SLOTS;
224 else
225 slot_nr = MVS_CHIP_SLOT_SZ;
226
227 spin_lock_init(&mvi->lock);
228 for (i = 0; i < mvi->chip->n_phy; i++) {
229 mvs_phy_init(mvi, i);
230 mvi->port[i].wide_port_phymap = 0;
231 mvi->port[i].port_attached = 0;
232 INIT_LIST_HEAD(&mvi->port[i].list);
233 }
234 for (i = 0; i < MVS_MAX_DEVICES; i++) {
235 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
236 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
237 mvi->devices[i].device_id = i;
238 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
239 }
240
241 /*
242 * alloc and init our DMA areas
243 */
244 mvi->tx = dma_alloc_coherent(mvi->dev,
245 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
246 &mvi->tx_dma, GFP_KERNEL);
247 if (!mvi->tx)
248 goto err_out;
249 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
250 &mvi->rx_fis_dma, GFP_KERNEL);
251 if (!mvi->rx_fis)
252 goto err_out;
253
254 mvi->rx = dma_alloc_coherent(mvi->dev,
255 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
256 &mvi->rx_dma, GFP_KERNEL);
257 if (!mvi->rx)
258 goto err_out;
259 mvi->rx[0] = cpu_to_le32(0xfff);
260 mvi->rx_cons = 0xfff;
261
262 mvi->slot = dma_alloc_coherent(mvi->dev,
263 sizeof(*mvi->slot) * slot_nr,
264 &mvi->slot_dma, GFP_KERNEL);
265 if (!mvi->slot)
266 goto err_out;
267
268 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
269 TRASH_BUCKET_SIZE,
270 &mvi->bulk_buffer_dma, GFP_KERNEL);
271 if (!mvi->bulk_buffer)
272 goto err_out;
273
274 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
275 TRASH_BUCKET_SIZE,
276 &mvi->bulk_buffer_dma1, GFP_KERNEL);
277 if (!mvi->bulk_buffer1)
278 goto err_out;
279
280 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
281 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,
282 MVS_SLOT_BUF_SZ, 16, 0);
283 if (!mvi->dma_pool) {
284 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
285 goto err_out;
286 }
287 mvi->tags_num = slot_nr;
288
289 /* Initialize tags */
290 mvs_tag_init(mvi);
291 return 0;
292 err_out:
293 return 1;
294 }
295
296
297 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
298 {
299 unsigned long res_start, res_len, res_flag_ex = 0;
300 struct pci_dev *pdev = mvi->pdev;
301 if (bar_ex != -1) {
302 /*
303 * ioremap main and peripheral registers
304 */
305 res_start = pci_resource_start(pdev, bar_ex);
306 res_len = pci_resource_len(pdev, bar_ex);
307 if (!res_start || !res_len)
308 goto err_out;
309
310 res_flag_ex = pci_resource_flags(pdev, bar_ex);
311 if (res_flag_ex & IORESOURCE_MEM)
312 mvi->regs_ex = ioremap(res_start, res_len);
313 else
314 mvi->regs_ex = (void *)res_start;
315 if (!mvi->regs_ex)
316 goto err_out;
317 }
318
319 res_start = pci_resource_start(pdev, bar);
320 res_len = pci_resource_len(pdev, bar);
321 if (!res_start || !res_len) {
322 iounmap(mvi->regs_ex);
323 mvi->regs_ex = NULL;
324 goto err_out;
325 }
326
327 mvi->regs = ioremap(res_start, res_len);
328
329 if (!mvi->regs) {
330 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
331 iounmap(mvi->regs_ex);
332 mvi->regs_ex = NULL;
333 goto err_out;
334 }
335
336 return 0;
337 err_out:
338 return -1;
339 }
340
341 void mvs_iounmap(void __iomem *regs)
342 {
343 iounmap(regs);
344 }
345
346 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
347 const struct pci_device_id *ent,
348 struct Scsi_Host *shost, unsigned int id)
349 {
350 struct mvs_info *mvi = NULL;
351 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
352
353 mvi = kzalloc(sizeof(*mvi) +
354 (1L << mvs_chips[ent->driver_data].slot_width) *
355 sizeof(struct mvs_slot_info), GFP_KERNEL);
356 if (!mvi)
357 return NULL;
358
359 mvi->pdev = pdev;
360 mvi->dev = &pdev->dev;
361 mvi->chip_id = ent->driver_data;
362 mvi->chip = &mvs_chips[mvi->chip_id];
363 INIT_LIST_HEAD(&mvi->wq_list);
364
365 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
366 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
367
368 mvi->id = id;
369 mvi->sas = sha;
370 mvi->shost = shost;
371
372 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
373 if (!mvi->tags)
374 goto err_out;
375
376 if (MVS_CHIP_DISP->chip_ioremap(mvi))
377 goto err_out;
378 if (!mvs_alloc(mvi, shost))
379 return mvi;
380 err_out:
381 mvs_free(mvi);
382 return NULL;
383 }
384
385 static int pci_go_64(struct pci_dev *pdev)
386 {
387 int rc;
388
389 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
390 if (rc) {
391 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
392 if (rc) {
393 dev_printk(KERN_ERR, &pdev->dev,
394 "32-bit DMA enable failed\n");
395 return rc;
396 }
397 }
398
399 return rc;
400 }
401
402 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
403 const struct mvs_chip_info *chip_info)
404 {
405 int phy_nr, port_nr; unsigned short core_nr;
406 struct asd_sas_phy **arr_phy;
407 struct asd_sas_port **arr_port;
408 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
409
410 core_nr = chip_info->n_host;
411 phy_nr = core_nr * chip_info->n_phy;
412 port_nr = phy_nr;
413
414 memset(sha, 0x00, sizeof(struct sas_ha_struct));
415 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
416 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
417 if (!arr_phy || !arr_port)
418 goto exit_free;
419
420 sha->sas_phy = arr_phy;
421 sha->sas_port = arr_port;
422 sha->core.shost = shost;
423
424 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
425 if (!sha->lldd_ha)
426 goto exit_free;
427
428 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
429
430 shost->transportt = mvs_stt;
431 shost->max_id = MVS_MAX_DEVICES;
432 shost->max_lun = ~0;
433 shost->max_channel = 1;
434 shost->max_cmd_len = 16;
435
436 return 0;
437 exit_free:
438 kfree(arr_phy);
439 kfree(arr_port);
440 return -1;
441
442 }
443
444 static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
445 const struct mvs_chip_info *chip_info)
446 {
447 int can_queue, i = 0, j = 0;
448 struct mvs_info *mvi = NULL;
449 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
450 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
451
452 for (j = 0; j < nr_core; j++) {
453 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
454 for (i = 0; i < chip_info->n_phy; i++) {
455 sha->sas_phy[j * chip_info->n_phy + i] =
456 &mvi->phy[i].sas_phy;
457 sha->sas_port[j * chip_info->n_phy + i] =
458 &mvi->port[i].sas_port;
459 }
460 }
461
462 sha->sas_ha_name = DRV_NAME;
463 sha->dev = mvi->dev;
464 sha->lldd_module = THIS_MODULE;
465 sha->sas_addr = &mvi->sas_addr[0];
466
467 sha->num_phys = nr_core * chip_info->n_phy;
468
469 if (mvi->flags & MVF_FLAG_SOC)
470 can_queue = MVS_SOC_CAN_QUEUE;
471 else
472 can_queue = MVS_CHIP_SLOT_SZ;
473
474 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
475 shost->can_queue = can_queue;
476 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
477 sha->core.shost = mvi->shost;
478 }
479
480 static void mvs_init_sas_add(struct mvs_info *mvi)
481 {
482 u8 i;
483 for (i = 0; i < mvi->chip->n_phy; i++) {
484 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
485 mvi->phy[i].dev_sas_addr =
486 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
487 }
488
489 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
490 }
491
492 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
493 {
494 unsigned int rc, nhost = 0;
495 struct mvs_info *mvi;
496 struct mvs_prv_info *mpi;
497 irq_handler_t irq_handler = mvs_interrupt;
498 struct Scsi_Host *shost = NULL;
499 const struct mvs_chip_info *chip;
500
501 dev_printk(KERN_INFO, &pdev->dev,
502 "mvsas: driver version %s\n", DRV_VERSION);
503 rc = pci_enable_device(pdev);
504 if (rc)
505 goto err_out_enable;
506
507 pci_set_master(pdev);
508
509 rc = pci_request_regions(pdev, DRV_NAME);
510 if (rc)
511 goto err_out_disable;
512
513 rc = pci_go_64(pdev);
514 if (rc)
515 goto err_out_regions;
516
517 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
518 if (!shost) {
519 rc = -ENOMEM;
520 goto err_out_regions;
521 }
522
523 chip = &mvs_chips[ent->driver_data];
524 SHOST_TO_SAS_HA(shost) =
525 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
526 if (!SHOST_TO_SAS_HA(shost)) {
527 scsi_host_put(shost);
528 rc = -ENOMEM;
529 goto err_out_regions;
530 }
531
532 rc = mvs_prep_sas_ha_init(shost, chip);
533 if (rc) {
534 scsi_host_put(shost);
535 rc = -ENOMEM;
536 goto err_out_regions;
537 }
538
539 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
540
541 do {
542 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
543 if (!mvi) {
544 rc = -ENOMEM;
545 goto err_out_regions;
546 }
547
548 memset(&mvi->hba_info_param, 0xFF,
549 sizeof(struct hba_info_page));
550
551 mvs_init_sas_add(mvi);
552
553 mvi->instance = nhost;
554 rc = MVS_CHIP_DISP->chip_init(mvi);
555 if (rc) {
556 mvs_free(mvi);
557 goto err_out_regions;
558 }
559 nhost++;
560 } while (nhost < chip->n_host);
561 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
562 #ifdef CONFIG_SCSI_MVSAS_TASKLET
563 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
564 (unsigned long)SHOST_TO_SAS_HA(shost));
565 #endif
566
567 mvs_post_sas_ha_init(shost, chip);
568
569 rc = scsi_add_host(shost, &pdev->dev);
570 if (rc)
571 goto err_out_shost;
572
573 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
574 if (rc)
575 goto err_out_shost;
576 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
577 DRV_NAME, SHOST_TO_SAS_HA(shost));
578 if (rc)
579 goto err_not_sas;
580
581 MVS_CHIP_DISP->interrupt_enable(mvi);
582
583 scsi_scan_host(mvi->shost);
584
585 return 0;
586
587 err_not_sas:
588 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
589 err_out_shost:
590 scsi_remove_host(mvi->shost);
591 err_out_regions:
592 pci_release_regions(pdev);
593 err_out_disable:
594 pci_disable_device(pdev);
595 err_out_enable:
596 return rc;
597 }
598
599 static void mvs_pci_remove(struct pci_dev *pdev)
600 {
601 unsigned short core_nr, i = 0;
602 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
603 struct mvs_info *mvi = NULL;
604
605 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
606 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
607
608 #ifdef CONFIG_SCSI_MVSAS_TASKLET
609 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
610 #endif
611
612 sas_unregister_ha(sha);
613 sas_remove_host(mvi->shost);
614
615 MVS_CHIP_DISP->interrupt_disable(mvi);
616 free_irq(mvi->pdev->irq, sha);
617 for (i = 0; i < core_nr; i++) {
618 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
619 mvs_free(mvi);
620 }
621 kfree(sha->sas_phy);
622 kfree(sha->sas_port);
623 kfree(sha);
624 pci_release_regions(pdev);
625 pci_disable_device(pdev);
626 return;
627 }
628
629 static struct pci_device_id mvs_pci_table[] = {
630 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
631 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
632 {
633 .vendor = PCI_VENDOR_ID_MARVELL,
634 .device = 0x6440,
635 .subvendor = PCI_ANY_ID,
636 .subdevice = 0x6480,
637 .class = 0,
638 .class_mask = 0,
639 .driver_data = chip_6485,
640 },
641 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
642 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
643 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
644 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
645 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
646 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
647 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
648 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
649 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
650 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
651 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
652 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
653 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
654 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
655 {
656 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
657 .device = 0x9480,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = 0x9480,
660 .class = 0,
661 .class_mask = 0,
662 .driver_data = chip_9480,
663 },
664 {
665 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
666 .device = 0x9445,
667 .subvendor = PCI_ANY_ID,
668 .subdevice = 0x9480,
669 .class = 0,
670 .class_mask = 0,
671 .driver_data = chip_9445,
672 },
673 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */
674 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
675 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
676 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
677 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
678 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
679 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
680 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
681 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
682 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
683 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
684
685 { } /* terminate list */
686 };
687
688 static struct pci_driver mvs_pci_driver = {
689 .name = DRV_NAME,
690 .id_table = mvs_pci_table,
691 .probe = mvs_pci_init,
692 .remove = mvs_pci_remove,
693 };
694
695 static ssize_t
696 mvs_show_driver_version(struct device *cdev,
697 struct device_attribute *attr, char *buffer)
698 {
699 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
700 }
701
702 static DEVICE_ATTR(driver_version,
703 S_IRUGO,
704 mvs_show_driver_version,
705 NULL);
706
707 static ssize_t
708 mvs_store_interrupt_coalescing(struct device *cdev,
709 struct device_attribute *attr,
710 const char *buffer, size_t size)
711 {
712 unsigned int val = 0;
713 struct mvs_info *mvi = NULL;
714 struct Scsi_Host *shost = class_to_shost(cdev);
715 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
716 u8 i, core_nr;
717 if (buffer == NULL)
718 return size;
719
720 if (sscanf(buffer, "%u", &val) != 1)
721 return -EINVAL;
722
723 if (val >= 0x10000) {
724 mv_dprintk("interrupt coalescing timer %d us is"
725 "too long\n", val);
726 return strlen(buffer);
727 }
728
729 interrupt_coalescing = val;
730
731 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
732 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
733
734 if (unlikely(!mvi))
735 return -EINVAL;
736
737 for (i = 0; i < core_nr; i++) {
738 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
739 if (MVS_CHIP_DISP->tune_interrupt)
740 MVS_CHIP_DISP->tune_interrupt(mvi,
741 interrupt_coalescing);
742 }
743 mv_dprintk("set interrupt coalescing time to %d us\n",
744 interrupt_coalescing);
745 return strlen(buffer);
746 }
747
748 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
749 struct device_attribute *attr, char *buffer)
750 {
751 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
752 }
753
754 static DEVICE_ATTR(interrupt_coalescing,
755 S_IRUGO|S_IWUSR,
756 mvs_show_interrupt_coalescing,
757 mvs_store_interrupt_coalescing);
758
759 static int __init mvs_init(void)
760 {
761 int rc;
762 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
763 if (!mvs_stt)
764 return -ENOMEM;
765
766 rc = pci_register_driver(&mvs_pci_driver);
767 if (rc)
768 goto err_out;
769
770 return 0;
771
772 err_out:
773 sas_release_transport(mvs_stt);
774 return rc;
775 }
776
777 static void __exit mvs_exit(void)
778 {
779 pci_unregister_driver(&mvs_pci_driver);
780 sas_release_transport(mvs_stt);
781 }
782
783 static struct device_attribute *mvst_host_attrs[] = {
784 &dev_attr_driver_version,
785 &dev_attr_interrupt_coalescing,
786 NULL,
787 };
788
789 module_init(mvs_init);
790 module_exit(mvs_exit);
791
792 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
793 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
794 MODULE_VERSION(DRV_VERSION);
795 MODULE_LICENSE("GPL");
796 #ifdef CONFIG_PCI
797 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
798 #endif
Linux with added FPC-III support