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WIP FPC-III support
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_fw.h
blob12b689e32883430f37a0f48e41e651876f8bd855
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #ifndef __QLA_FW_H
7 #define __QLA_FW_H
8
9 #include <linux/nvme.h>
10 #include <linux/nvme-fc.h>
11
12 #include "qla_dsd.h"
13
14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
16
17 /*
18 * Firmware Options.
19 */
20 #define FO1_ENABLE_PUREX BIT_10
21 #define FO1_DISABLE_LED_CTRL BIT_6
22 #define FO1_ENABLE_8016 BIT_0
23 #define FO2_ENABLE_SEL_CLASS2 BIT_5
24 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
25 #define FO3_HOLD_STS_IOCB BIT_12
26
27 /*
28 * Port Database structure definition for ISP 24xx.
29 */
30 #define PDO_FORCE_ADISC BIT_1
31 #define PDO_FORCE_PLOGI BIT_0
32
33 struct buffer_credit_24xx {
34 u32 parameter[28];
35 };
36
37 #define PORT_DATABASE_24XX_SIZE 64
38 struct port_database_24xx {
39 uint16_t flags;
40 #define PDF_TASK_RETRY_ID BIT_14
41 #define PDF_FC_TAPE BIT_7
42 #define PDF_ACK0_CAPABLE BIT_6
43 #define PDF_FCP2_CONF BIT_5
44 #define PDF_CLASS_2 BIT_4
45 #define PDF_HARD_ADDR BIT_1
46
47 /*
48 * for NVMe, the login_state field has been
49 * split into nibbles.
50 * The lower nibble is for FCP.
51 * The upper nibble is for NVMe.
52 */
53 uint8_t current_login_state;
54 uint8_t last_login_state;
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
63
64 uint8_t hard_address[3];
65 uint8_t reserved_1;
66
67 uint8_t port_id[3];
68 uint8_t sequence_id;
69
70 uint16_t port_timer;
71
72 uint16_t nport_handle; /* N_PORT handle. */
73
74 uint16_t receive_data_size;
75 uint16_t reserved_2;
76
77 uint8_t prli_svc_param_word_0[2]; /* Big endian */
78 /* Bits 15-0 of word 0 */
79 uint8_t prli_svc_param_word_3[2]; /* Big endian */
80 /* Bits 15-0 of word 3 */
81
82 uint8_t port_name[WWN_SIZE];
83 uint8_t node_name[WWN_SIZE];
84
85 uint8_t reserved_3[4];
86 uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */
87 uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */
88 uint16_t nvme_first_burst_size;
89 uint8_t reserved_4[14];
90 };
91
92 /*
93 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
94 * However, in this case it returns 1st 40 bytes.
95 */
96 struct get_name_list_extended {
97 __le16 flags;
98 u8 current_login_state;
99 u8 last_login_state;
100 u8 hard_address[3];
101 u8 reserved_1;
102 u8 port_id[3];
103 u8 sequence_id;
104 __le16 port_timer;
105 __le16 nport_handle; /* N_PORT handle. */
106 __le16 receive_data_size;
107 __le16 reserved_2;
108
109 /* PRLI SVC Param are Big endian */
110 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
111 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
112 u8 port_name[WWN_SIZE];
113 u8 node_name[WWN_SIZE];
114 };
115
116 /* MB 75h: This is the short version of the database */
117 struct get_name_list {
118 u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
119 __le16 nport_handle;
120 u8 reserved;
121 };
122
123 struct vp_database_24xx {
124 uint16_t vp_status;
125 uint8_t options;
126 uint8_t id;
127 uint8_t port_name[WWN_SIZE];
128 uint8_t node_name[WWN_SIZE];
129 uint16_t port_id_low;
130 uint16_t port_id_high;
131 };
132
133 struct nvram_24xx {
134 /* NVRAM header. */
135 uint8_t id[4];
136 __le16 nvram_version;
137 uint16_t reserved_0;
138
139 /* Firmware Initialization Control Block. */
140 __le16 version;
141 uint16_t reserved_1;
142 __le16 frame_payload_size;
143 __le16 execution_throttle;
144 __le16 exchange_count;
145 __le16 hard_address;
146
147 uint8_t port_name[WWN_SIZE];
148 uint8_t node_name[WWN_SIZE];
149
150 __le16 login_retry_count;
151 __le16 link_down_on_nos;
152 __le16 interrupt_delay_timer;
153 __le16 login_timeout;
154
155 __le32 firmware_options_1;
156 __le32 firmware_options_2;
157 __le32 firmware_options_3;
158
159 /* Offset 56. */
160
161 /*
162 * BIT 0 = Control Enable
163 * BIT 1-15 =
164 *
165 * BIT 0-7 = Reserved
166 * BIT 8-10 = Output Swing 1G
167 * BIT 11-13 = Output Emphasis 1G
168 * BIT 14-15 = Reserved
169 *
170 * BIT 0-7 = Reserved
171 * BIT 8-10 = Output Swing 2G
172 * BIT 11-13 = Output Emphasis 2G
173 * BIT 14-15 = Reserved
174 *
175 * BIT 0-7 = Reserved
176 * BIT 8-10 = Output Swing 4G
177 * BIT 11-13 = Output Emphasis 4G
178 * BIT 14-15 = Reserved
179 */
180 __le16 seriallink_options[4];
181
182 uint16_t reserved_2[16];
183
184 /* Offset 96. */
185 uint16_t reserved_3[16];
186
187 /* PCIe table entries. */
188 uint16_t reserved_4[16];
189
190 /* Offset 160. */
191 uint16_t reserved_5[16];
192
193 /* Offset 192. */
194 uint16_t reserved_6[16];
195
196 /* Offset 224. */
197 uint16_t reserved_7[16];
198
199 /*
200 * BIT 0 = Enable spinup delay
201 * BIT 1 = Disable BIOS
202 * BIT 2 = Enable Memory Map BIOS
203 * BIT 3 = Enable Selectable Boot
204 * BIT 4 = Disable RISC code load
205 * BIT 5 = Disable Serdes
206 * BIT 6 =
207 * BIT 7 =
208 *
209 * BIT 8 =
210 * BIT 9 =
211 * BIT 10 = Enable lip full login
212 * BIT 11 = Enable target reset
213 * BIT 12 =
214 * BIT 13 =
215 * BIT 14 =
216 * BIT 15 = Enable alternate WWN
217 *
218 * BIT 16-31 =
219 */
220 __le32 host_p;
221
222 uint8_t alternate_port_name[WWN_SIZE];
223 uint8_t alternate_node_name[WWN_SIZE];
224
225 uint8_t boot_port_name[WWN_SIZE];
226 __le16 boot_lun_number;
227 uint16_t reserved_8;
228
229 uint8_t alt1_boot_port_name[WWN_SIZE];
230 __le16 alt1_boot_lun_number;
231 uint16_t reserved_9;
232
233 uint8_t alt2_boot_port_name[WWN_SIZE];
234 __le16 alt2_boot_lun_number;
235 uint16_t reserved_10;
236
237 uint8_t alt3_boot_port_name[WWN_SIZE];
238 __le16 alt3_boot_lun_number;
239 uint16_t reserved_11;
240
241 /*
242 * BIT 0 = Selective Login
243 * BIT 1 = Alt-Boot Enable
244 * BIT 2 = Reserved
245 * BIT 3 = Boot Order List
246 * BIT 4 = Reserved
247 * BIT 5 = Selective LUN
248 * BIT 6 = Reserved
249 * BIT 7-31 =
250 */
251 __le32 efi_parameters;
252
253 uint8_t reset_delay;
254 uint8_t reserved_12;
255 uint16_t reserved_13;
256
257 __le16 boot_id_number;
258 uint16_t reserved_14;
259
260 __le16 max_luns_per_target;
261 uint16_t reserved_15;
262
263 __le16 port_down_retry_count;
264 __le16 link_down_timeout;
265
266 /* FCode parameters. */
267 __le16 fcode_parameter;
268
269 uint16_t reserved_16[3];
270
271 /* Offset 352. */
272 uint8_t prev_drv_ver_major;
273 uint8_t prev_drv_ver_submajob;
274 uint8_t prev_drv_ver_minor;
275 uint8_t prev_drv_ver_subminor;
276
277 __le16 prev_bios_ver_major;
278 __le16 prev_bios_ver_minor;
279
280 __le16 prev_efi_ver_major;
281 __le16 prev_efi_ver_minor;
282
283 __le16 prev_fw_ver_major;
284 uint8_t prev_fw_ver_minor;
285 uint8_t prev_fw_ver_subminor;
286
287 uint16_t reserved_17[8];
288
289 /* Offset 384. */
290 uint16_t reserved_18[16];
291
292 /* Offset 416. */
293 uint16_t reserved_19[16];
294
295 /* Offset 448. */
296 uint16_t reserved_20[16];
297
298 /* Offset 480. */
299 uint8_t model_name[16];
300
301 uint16_t reserved_21[2];
302
303 /* Offset 500. */
304 /* HW Parameter Block. */
305 uint16_t pcie_table_sig;
306 uint16_t pcie_table_offset;
307
308 uint16_t subsystem_vendor_id;
309 uint16_t subsystem_device_id;
310
311 __le32 checksum;
312 };
313
314 /*
315 * ISP Initialization Control Block.
316 * Little endian except where noted.
317 */
318 #define ICB_VERSION 1
319 struct init_cb_24xx {
320 __le16 version;
321 uint16_t reserved_1;
322
323 __le16 frame_payload_size;
324 __le16 execution_throttle;
325 __le16 exchange_count;
326
327 __le16 hard_address;
328
329 uint8_t port_name[WWN_SIZE]; /* Big endian. */
330 uint8_t node_name[WWN_SIZE]; /* Big endian. */
331
332 __le16 response_q_inpointer;
333 __le16 request_q_outpointer;
334
335 __le16 login_retry_count;
336
337 __le16 prio_request_q_outpointer;
338
339 __le16 response_q_length;
340 __le16 request_q_length;
341
342 __le16 link_down_on_nos; /* Milliseconds. */
343
344 __le16 prio_request_q_length;
345
346 __le64 request_q_address __packed;
347 __le64 response_q_address __packed;
348 __le64 prio_request_q_address __packed;
349
350 __le16 msix;
351 __le16 msix_atio;
352 uint8_t reserved_2[4];
353
354 __le16 atio_q_inpointer;
355 __le16 atio_q_length;
356 __le64 atio_q_address __packed;
357
358 __le16 interrupt_delay_timer; /* 100us increments. */
359 __le16 login_timeout;
360
361 /*
362 * BIT 0 = Enable Hard Loop Id
363 * BIT 1 = Enable Fairness
364 * BIT 2 = Enable Full-Duplex
365 * BIT 3 = Reserved
366 * BIT 4 = Enable Target Mode
367 * BIT 5 = Disable Initiator Mode
368 * BIT 6 = Acquire FA-WWN
369 * BIT 7 = Enable D-port Diagnostics
370 *
371 * BIT 8 = Reserved
372 * BIT 9 = Non Participating LIP
373 * BIT 10 = Descending Loop ID Search
374 * BIT 11 = Acquire Loop ID in LIPA
375 * BIT 12 = Reserved
376 * BIT 13 = Full Login after LIP
377 * BIT 14 = Node Name Option
378 * BIT 15-31 = Reserved
379 */
380 __le32 firmware_options_1;
381
382 /*
383 * BIT 0 = Operation Mode bit 0
384 * BIT 1 = Operation Mode bit 1
385 * BIT 2 = Operation Mode bit 2
386 * BIT 3 = Operation Mode bit 3
387 * BIT 4 = Connection Options bit 0
388 * BIT 5 = Connection Options bit 1
389 * BIT 6 = Connection Options bit 2
390 * BIT 7 = Enable Non part on LIHA failure
391 *
392 * BIT 8 = Enable Class 2
393 * BIT 9 = Enable ACK0
394 * BIT 10 = Reserved
395 * BIT 11 = Enable FC-SP Security
396 * BIT 12 = FC Tape Enable
397 * BIT 13 = Reserved
398 * BIT 14 = Enable Target PRLI Control
399 * BIT 15-31 = Reserved
400 */
401 __le32 firmware_options_2;
402
403 /*
404 * BIT 0 = Reserved
405 * BIT 1 = Soft ID only
406 * BIT 2 = Reserved
407 * BIT 3 = Reserved
408 * BIT 4 = FCP RSP Payload bit 0
409 * BIT 5 = FCP RSP Payload bit 1
410 * BIT 6 = Enable Receive Out-of-Order data frame handling
411 * BIT 7 = Disable Automatic PLOGI on Local Loop
412 *
413 * BIT 8 = Reserved
414 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
415 * BIT 10 = Reserved
416 * BIT 11 = Reserved
417 * BIT 12 = Reserved
418 * BIT 13 = Data Rate bit 0
419 * BIT 14 = Data Rate bit 1
420 * BIT 15 = Data Rate bit 2
421 * BIT 16 = Enable 75 ohm Termination Select
422 * BIT 17-28 = Reserved
423 * BIT 29 = Enable response queue 0 in index shadowing
424 * BIT 30 = Enable request queue 0 out index shadowing
425 * BIT 31 = Reserved
426 */
427 __le32 firmware_options_3;
428 __le16 qos;
429 __le16 rid;
430 uint8_t reserved_3[20];
431 };
432
433 /*
434 * ISP queue - command entry structure definition.
435 */
436 #define COMMAND_BIDIRECTIONAL 0x75
437 struct cmd_bidir {
438 uint8_t entry_type; /* Entry type. */
439 uint8_t entry_count; /* Entry count. */
440 uint8_t sys_define; /* System defined */
441 uint8_t entry_status; /* Entry status. */
442
443 uint32_t handle; /* System handle. */
444
445 __le16 nport_handle; /* N_PORT handle. */
446
447 __le16 timeout; /* Command timeout. */
448
449 __le16 wr_dseg_count; /* Write Data segment count. */
450 __le16 rd_dseg_count; /* Read Data segment count. */
451
452 struct scsi_lun lun; /* FCP LUN (BE). */
453
454 __le16 control_flags; /* Control flags. */
455 #define BD_WRAP_BACK BIT_3
456 #define BD_READ_DATA BIT_1
457 #define BD_WRITE_DATA BIT_0
458
459 __le16 fcp_cmnd_dseg_len; /* Data segment length. */
460 __le64 fcp_cmnd_dseg_address __packed;/* Data segment address. */
461
462 uint16_t reserved[2]; /* Reserved */
463
464 __le32 rd_byte_count; /* Total Byte count Read. */
465 __le32 wr_byte_count; /* Total Byte count write. */
466
467 uint8_t port_id[3]; /* PortID of destination port.*/
468 uint8_t vp_index;
469
470 struct dsd64 fcp_dsd;
471 };
472
473 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
474 struct cmd_type_6 {
475 uint8_t entry_type; /* Entry type. */
476 uint8_t entry_count; /* Entry count. */
477 uint8_t sys_define; /* System defined. */
478 uint8_t entry_status; /* Entry Status. */
479
480 uint32_t handle; /* System handle. */
481
482 __le16 nport_handle; /* N_PORT handle. */
483 __le16 timeout; /* Command timeout. */
484
485 __le16 dseg_count; /* Data segment count. */
486
487 __le16 fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
488
489 struct scsi_lun lun; /* FCP LUN (BE). */
490
491 __le16 control_flags; /* Control flags. */
492 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
493 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
494 #define CF_READ_DATA BIT_1
495 #define CF_WRITE_DATA BIT_0
496
497 __le16 fcp_cmnd_dseg_len; /* Data segment length. */
498 /* Data segment address. */
499 __le64 fcp_cmnd_dseg_address __packed;
500 /* Data segment address. */
501 __le64 fcp_rsp_dseg_address __packed;
502
503 __le32 byte_count; /* Total byte count. */
504
505 uint8_t port_id[3]; /* PortID of destination port. */
506 uint8_t vp_index;
507
508 struct dsd64 fcp_dsd;
509 };
510
511 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
512 struct cmd_type_7 {
513 uint8_t entry_type; /* Entry type. */
514 uint8_t entry_count; /* Entry count. */
515 uint8_t sys_define; /* System defined. */
516 uint8_t entry_status; /* Entry Status. */
517
518 uint32_t handle; /* System handle. */
519
520 __le16 nport_handle; /* N_PORT handle. */
521 __le16 timeout; /* Command timeout. */
522 #define FW_MAX_TIMEOUT 0x1999
523
524 __le16 dseg_count; /* Data segment count. */
525 uint16_t reserved_1;
526
527 struct scsi_lun lun; /* FCP LUN (BE). */
528
529 __le16 task_mgmt_flags; /* Task management flags. */
530 #define TMF_CLEAR_ACA BIT_14
531 #define TMF_TARGET_RESET BIT_13
532 #define TMF_LUN_RESET BIT_12
533 #define TMF_CLEAR_TASK_SET BIT_10
534 #define TMF_ABORT_TASK_SET BIT_9
535 #define TMF_DSD_LIST_ENABLE BIT_2
536 #define TMF_READ_DATA BIT_1
537 #define TMF_WRITE_DATA BIT_0
538
539 uint8_t task;
540 #define TSK_SIMPLE 0
541 #define TSK_HEAD_OF_QUEUE 1
542 #define TSK_ORDERED 2
543 #define TSK_ACA 4
544 #define TSK_UNTAGGED 5
545
546 uint8_t crn;
547
548 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
549 __le32 byte_count; /* Total byte count. */
550
551 uint8_t port_id[3]; /* PortID of destination port. */
552 uint8_t vp_index;
553
554 struct dsd64 dsd;
555 };
556
557 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
558 * (T10-DIF) */
559 struct cmd_type_crc_2 {
560 uint8_t entry_type; /* Entry type. */
561 uint8_t entry_count; /* Entry count. */
562 uint8_t sys_define; /* System defined. */
563 uint8_t entry_status; /* Entry Status. */
564
565 uint32_t handle; /* System handle. */
566
567 __le16 nport_handle; /* N_PORT handle. */
568 __le16 timeout; /* Command timeout. */
569
570 __le16 dseg_count; /* Data segment count. */
571
572 __le16 fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
573
574 struct scsi_lun lun; /* FCP LUN (BE). */
575
576 __le16 control_flags; /* Control flags. */
577
578 __le16 fcp_cmnd_dseg_len; /* Data segment length. */
579 __le64 fcp_cmnd_dseg_address __packed;
580 /* Data segment address. */
581 __le64 fcp_rsp_dseg_address __packed;
582
583 __le32 byte_count; /* Total byte count. */
584
585 uint8_t port_id[3]; /* PortID of destination port. */
586 uint8_t vp_index;
587
588 __le64 crc_context_address __packed; /* Data segment address. */
589 __le16 crc_context_len; /* Data segment length. */
590 uint16_t reserved_1; /* MUST be set to 0. */
591 };
592
593
594 /*
595 * ISP queue - status entry structure definition.
596 */
597 #define STATUS_TYPE 0x03 /* Status entry. */
598 struct sts_entry_24xx {
599 uint8_t entry_type; /* Entry type. */
600 uint8_t entry_count; /* Entry count. */
601 uint8_t sys_define; /* System defined. */
602 uint8_t entry_status; /* Entry Status. */
603
604 uint32_t handle; /* System handle. */
605
606 __le16 comp_status; /* Completion status. */
607 __le16 ox_id; /* OX_ID used by the firmware. */
608
609 __le32 residual_len; /* FW calc residual transfer length. */
610
611 union {
612 __le16 reserved_1;
613 __le16 nvme_rsp_pyld_len;
614 };
615
616 __le16 state_flags; /* State flags. */
617 #define SF_TRANSFERRED_DATA BIT_11
618 #define SF_NVME_ERSP BIT_6
619 #define SF_FCP_RSP_DMA BIT_0
620
621 __le16 status_qualifier;
622 __le16 scsi_status; /* SCSI status. */
623 #define SS_CONFIRMATION_REQ BIT_12
624
625 __le32 rsp_residual_count; /* FCP RSP residual count. */
626
627 __le32 sense_len; /* FCP SENSE length. */
628
629 union {
630 struct {
631 __le32 rsp_data_len; /* FCP response data length */
632 uint8_t data[28]; /* FCP rsp/sense information */
633 };
634 struct nvme_fc_ersp_iu nvme_ersp;
635 uint8_t nvme_ersp_data[32];
636 };
637
638 /*
639 * If DIF Error is set in comp_status, these additional fields are
640 * defined:
641 *
642 * !!! NOTE: Firmware sends expected/actual DIF data in big endian
643 * format; but all of the "data" field gets swab32-d in the beginning
644 * of qla2x00_status_entry().
645 *
646 * &data[10] : uint8_t report_runt_bg[2]; - computed guard
647 * &data[12] : uint8_t actual_dif[8]; - DIF Data received
648 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed
649 */
650 };
651
652
653 /*
654 * Status entry completion status
655 */
656 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
657 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
658 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
659 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
660 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
661
662 /*
663 * ISP queue - marker entry structure definition.
664 */
665 #define MARKER_TYPE 0x04 /* Marker entry. */
666 struct mrk_entry_24xx {
667 uint8_t entry_type; /* Entry type. */
668 uint8_t entry_count; /* Entry count. */
669 uint8_t handle_count; /* Handle count. */
670 uint8_t entry_status; /* Entry Status. */
671
672 uint32_t handle; /* System handle. */
673
674 __le16 nport_handle; /* N_PORT handle. */
675
676 uint8_t modifier; /* Modifier (7-0). */
677 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
678 #define MK_SYNC_ID 1 /* Synchronize ID */
679 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
680 uint8_t reserved_1;
681
682 uint8_t reserved_2;
683 uint8_t vp_index;
684
685 uint16_t reserved_3;
686
687 uint8_t lun[8]; /* FCP LUN (BE). */
688 uint8_t reserved_4[40];
689 };
690
691 /*
692 * ISP queue - CT Pass-Through entry structure definition.
693 */
694 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
695 struct ct_entry_24xx {
696 uint8_t entry_type; /* Entry type. */
697 uint8_t entry_count; /* Entry count. */
698 uint8_t sys_define; /* System Defined. */
699 uint8_t entry_status; /* Entry Status. */
700
701 uint32_t handle; /* System handle. */
702
703 __le16 comp_status; /* Completion status. */
704
705 __le16 nport_handle; /* N_PORT handle. */
706
707 __le16 cmd_dsd_count;
708
709 uint8_t vp_index;
710 uint8_t reserved_1;
711
712 __le16 timeout; /* Command timeout. */
713 uint16_t reserved_2;
714
715 __le16 rsp_dsd_count;
716
717 uint8_t reserved_3[10];
718
719 __le32 rsp_byte_count;
720 __le32 cmd_byte_count;
721
722 struct dsd64 dsd[2];
723 };
724
725 #define PURX_ELS_HEADER_SIZE 0x18
726
727 /*
728 * ISP queue - PUREX IOCB entry structure definition
729 */
730 #define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */
731 struct purex_entry_24xx {
732 uint8_t entry_type; /* Entry type. */
733 uint8_t entry_count; /* Entry count. */
734 uint8_t sys_define; /* System defined. */
735 uint8_t entry_status; /* Entry Status. */
736
737 __le16 reserved1;
738 uint8_t vp_idx;
739 uint8_t reserved2;
740
741 __le16 status_flags;
742 __le16 nport_handle;
743
744 __le16 frame_size;
745 __le16 trunc_frame_size;
746
747 __le32 rx_xchg_addr;
748
749 uint8_t d_id[3];
750 uint8_t r_ctl;
751
752 uint8_t s_id[3];
753 uint8_t cs_ctl;
754
755 uint8_t f_ctl[3];
756 uint8_t type;
757
758 __le16 seq_cnt;
759 uint8_t df_ctl;
760 uint8_t seq_id;
761
762 __le16 rx_id;
763 __le16 ox_id;
764 __le32 param;
765
766 uint8_t els_frame_payload[20];
767 };
768
769 /*
770 * ISP queue - ELS Pass-Through entry structure definition.
771 */
772 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
773 struct els_entry_24xx {
774 uint8_t entry_type; /* Entry type. */
775 uint8_t entry_count; /* Entry count. */
776 uint8_t sys_define; /* System Defined. */
777 uint8_t entry_status; /* Entry Status. */
778
779 uint32_t handle; /* System handle. */
780
781 __le16 comp_status; /* response only */
782 __le16 nport_handle;
783
784 __le16 tx_dsd_count;
785
786 uint8_t vp_index;
787 uint8_t sof_type;
788 #define EST_SOFI3 (1 << 4)
789 #define EST_SOFI2 (3 << 4)
790
791 __le32 rx_xchg_address; /* Receive exchange address. */
792 __le16 rx_dsd_count;
793
794 uint8_t opcode;
795 uint8_t reserved_2;
796
797 uint8_t d_id[3];
798 uint8_t s_id[3];
799
800 __le16 control_flags; /* Control flags. */
801 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
802 #define EPD_ELS_COMMAND (0 << 13)
803 #define EPD_ELS_ACC (1 << 13)
804 #define EPD_ELS_RJT (2 << 13)
805 #define EPD_RX_XCHG (3 << 13)
806 #define ECF_CLR_PASSTHRU_PEND BIT_12
807 #define ECF_INCL_FRAME_HDR BIT_11
808
809 union {
810 struct {
811 __le32 rx_byte_count;
812 __le32 tx_byte_count;
813
814 __le64 tx_address __packed; /* DSD 0 address. */
815 __le32 tx_len; /* DSD 0 length. */
816
817 __le64 rx_address __packed; /* DSD 1 address. */
818 __le32 rx_len; /* DSD 1 length. */
819 };
820 struct {
821 __le32 total_byte_count;
822 __le32 error_subcode_1;
823 __le32 error_subcode_2;
824 __le32 error_subcode_3;
825 };
826 };
827 };
828
829 struct els_sts_entry_24xx {
830 uint8_t entry_type; /* Entry type. */
831 uint8_t entry_count; /* Entry count. */
832 uint8_t sys_define; /* System Defined. */
833 uint8_t entry_status; /* Entry Status. */
834
835 __le32 handle; /* System handle. */
836
837 __le16 comp_status;
838
839 __le16 nport_handle; /* N_PORT handle. */
840
841 __le16 reserved_1;
842
843 uint8_t vp_index;
844 uint8_t sof_type;
845
846 __le32 rx_xchg_address; /* Receive exchange address. */
847 __le16 reserved_2;
848
849 uint8_t opcode;
850 uint8_t reserved_3;
851
852 uint8_t d_id[3];
853 uint8_t s_id[3];
854
855 __le16 control_flags; /* Control flags. */
856 __le32 total_byte_count;
857 __le32 error_subcode_1;
858 __le32 error_subcode_2;
859 __le32 error_subcode_3;
860
861 __le32 reserved_4[4];
862 };
863 /*
864 * ISP queue - Mailbox Command entry structure definition.
865 */
866 #define MBX_IOCB_TYPE 0x39
867 struct mbx_entry_24xx {
868 uint8_t entry_type; /* Entry type. */
869 uint8_t entry_count; /* Entry count. */
870 uint8_t handle_count; /* Handle count. */
871 uint8_t entry_status; /* Entry Status. */
872
873 uint32_t handle; /* System handle. */
874
875 uint16_t mbx[28];
876 };
877
878
879 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
880 struct logio_entry_24xx {
881 uint8_t entry_type; /* Entry type. */
882 uint8_t entry_count; /* Entry count. */
883 uint8_t sys_define; /* System defined. */
884 uint8_t entry_status; /* Entry Status. */
885
886 uint32_t handle; /* System handle. */
887
888 __le16 comp_status; /* Completion status. */
889 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
890
891 __le16 nport_handle; /* N_PORT handle. */
892
893 __le16 control_flags; /* Control flags. */
894 /* Modifiers. */
895 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
896 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
897 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
898 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
899 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
900 #define LCF_NVME_PRLI BIT_6 /* Perform NVME FC4 PRLI */
901 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
902 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
903 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
904 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
905 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
906 /* Commands. */
907 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
908 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
909 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
910 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
911 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
912 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
913 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
914
915 uint8_t vp_index;
916 uint8_t reserved_1;
917
918 uint8_t port_id[3]; /* PortID of destination port. */
919
920 uint8_t rsp_size; /* Response size in 32bit words. */
921
922 __le32 io_parameter[11]; /* General I/O parameters. */
923 #define LSC_SCODE_NOLINK 0x01
924 #define LSC_SCODE_NOIOCB 0x02
925 #define LSC_SCODE_NOXCB 0x03
926 #define LSC_SCODE_CMD_FAILED 0x04
927 #define LSC_SCODE_NOFABRIC 0x05
928 #define LSC_SCODE_FW_NOT_READY 0x07
929 #define LSC_SCODE_NOT_LOGGED_IN 0x09
930 #define LSC_SCODE_NOPCB 0x0A
931
932 #define LSC_SCODE_ELS_REJECT 0x18
933 #define LSC_SCODE_CMD_PARAM_ERR 0x19
934 #define LSC_SCODE_PORTID_USED 0x1A
935 #define LSC_SCODE_NPORT_USED 0x1B
936 #define LSC_SCODE_NONPORT 0x1C
937 #define LSC_SCODE_LOGGED_IN 0x1D
938 #define LSC_SCODE_NOFLOGI_ACC 0x1F
939 };
940
941 #define TSK_MGMT_IOCB_TYPE 0x14
942 struct tsk_mgmt_entry {
943 uint8_t entry_type; /* Entry type. */
944 uint8_t entry_count; /* Entry count. */
945 uint8_t handle_count; /* Handle count. */
946 uint8_t entry_status; /* Entry Status. */
947
948 uint32_t handle; /* System handle. */
949
950 __le16 nport_handle; /* N_PORT handle. */
951
952 uint16_t reserved_1;
953
954 __le16 delay; /* Activity delay in seconds. */
955
956 __le16 timeout; /* Command timeout. */
957
958 struct scsi_lun lun; /* FCP LUN (BE). */
959
960 __le32 control_flags; /* Control Flags. */
961 #define TCF_NOTMCMD_TO_TARGET BIT_31
962 #define TCF_LUN_RESET BIT_4
963 #define TCF_ABORT_TASK_SET BIT_3
964 #define TCF_CLEAR_TASK_SET BIT_2
965 #define TCF_TARGET_RESET BIT_1
966 #define TCF_CLEAR_ACA BIT_0
967
968 uint8_t reserved_2[20];
969
970 uint8_t port_id[3]; /* PortID of destination port. */
971 uint8_t vp_index;
972
973 uint8_t reserved_3[12];
974 };
975
976 #define ABORT_IOCB_TYPE 0x33
977 struct abort_entry_24xx {
978 uint8_t entry_type; /* Entry type. */
979 uint8_t entry_count; /* Entry count. */
980 uint8_t handle_count; /* Handle count. */
981 uint8_t entry_status; /* Entry Status. */
982
983 uint32_t handle; /* System handle. */
984
985 __le16 nport_handle; /* N_PORT handle. */
986 /* or Completion status. */
987
988 __le16 options; /* Options. */
989 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
990
991 uint32_t handle_to_abort; /* System handle to abort. */
992
993 __le16 req_que_no;
994 uint8_t reserved_1[30];
995
996 uint8_t port_id[3]; /* PortID of destination port. */
997 uint8_t vp_index;
998
999 uint8_t reserved_2[12];
1000 };
1001
1002 #define ABTS_RCV_TYPE 0x54
1003 #define ABTS_RSP_TYPE 0x55
1004 struct abts_entry_24xx {
1005 uint8_t entry_type;
1006 uint8_t entry_count;
1007 uint8_t handle_count;
1008 uint8_t entry_status;
1009
1010 __le32 handle; /* type 0x55 only */
1011
1012 __le16 comp_status; /* type 0x55 only */
1013 __le16 nport_handle; /* type 0x54 only */
1014
1015 __le16 control_flags; /* type 0x55 only */
1016 uint8_t vp_idx;
1017 uint8_t sof_type; /* sof_type is upper nibble */
1018
1019 __le32 rx_xch_addr;
1020
1021 uint8_t d_id[3];
1022 uint8_t r_ctl;
1023
1024 uint8_t s_id[3];
1025 uint8_t cs_ctl;
1026
1027 uint8_t f_ctl[3];
1028 uint8_t type;
1029
1030 __le16 seq_cnt;
1031 uint8_t df_ctl;
1032 uint8_t seq_id;
1033
1034 __le16 rx_id;
1035 __le16 ox_id;
1036
1037 __le32 param;
1038
1039 union {
1040 struct {
1041 __le32 subcode3;
1042 __le32 rsvd;
1043 __le32 subcode1;
1044 __le32 subcode2;
1045 } error;
1046 struct {
1047 __le16 rsrvd1;
1048 uint8_t last_seq_id;
1049 uint8_t seq_id_valid;
1050 __le16 aborted_rx_id;
1051 __le16 aborted_ox_id;
1052 __le16 high_seq_cnt;
1053 __le16 low_seq_cnt;
1054 } ba_acc;
1055 struct {
1056 uint8_t vendor_unique;
1057 uint8_t explanation;
1058 uint8_t reason;
1059 } ba_rjt;
1060 } payload;
1061
1062 __le32 rx_xch_addr_to_abort;
1063 } __packed;
1064
1065 /* ABTS payload explanation values */
1066 #define BA_RJT_EXP_NO_ADDITIONAL 0
1067 #define BA_RJT_EXP_INV_OX_RX_ID 3
1068 #define BA_RJT_EXP_SEQ_ABORTED 5
1069
1070 /* ABTS payload reason values */
1071 #define BA_RJT_RSN_INV_CMD_CODE 1
1072 #define BA_RJT_RSN_LOGICAL_ERROR 3
1073 #define BA_RJT_RSN_LOGICAL_BUSY 5
1074 #define BA_RJT_RSN_PROTOCOL_ERROR 7
1075 #define BA_RJT_RSN_UNABLE_TO_PERFORM 9
1076 #define BA_RJT_RSN_VENDOR_SPECIFIC 0xff
1077
1078 /* FC_F values */
1079 #define FC_TYPE_BLD 0x000 /* Basic link data */
1080 #define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */
1081 #define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */
1082 #define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */
1083 #define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */
1084 #define FC_ROUTING_BLD 0x80 /* Basic link data frame */
1085 #define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */
1086
1087 /*
1088 * ISP I/O Register Set structure definitions.
1089 */
1090 struct device_reg_24xx {
1091 __le32 flash_addr; /* Flash/NVRAM BIOS address. */
1092 #define FARX_DATA_FLAG BIT_31
1093 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1094 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1095 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
1096 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
1097
1098 #define FA_NVRAM_FUNC0_ADDR 0x80
1099 #define FA_NVRAM_FUNC1_ADDR 0x180
1100
1101 #define FA_NVRAM_VPD_SIZE 0x200
1102 #define FA_NVRAM_VPD0_ADDR 0x00
1103 #define FA_NVRAM_VPD1_ADDR 0x100
1104
1105 #define FA_BOOT_CODE_ADDR 0x00000
1106 /*
1107 * RISC code begins at offset 512KB
1108 * within flash. Consisting of two
1109 * contiguous RISC code segments.
1110 */
1111 #define FA_RISC_CODE_ADDR 0x20000
1112 #define FA_RISC_CODE_SEGMENTS 2
1113
1114 #define FA_FLASH_DESCR_ADDR_24 0x11000
1115 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
1116 #define FA_NPIV_CONF0_ADDR_24 0x16000
1117 #define FA_NPIV_CONF1_ADDR_24 0x17000
1118
1119 #define FA_FW_AREA_ADDR 0x40000
1120 #define FA_VPD_NVRAM_ADDR 0x48000
1121 #define FA_FEATURE_ADDR 0x4C000
1122 #define FA_FLASH_DESCR_ADDR 0x50000
1123 #define FA_FLASH_LAYOUT_ADDR 0x50400
1124 #define FA_HW_EVENT0_ADDR 0x54000
1125 #define FA_HW_EVENT1_ADDR 0x54400
1126 #define FA_HW_EVENT_SIZE 0x200
1127 #define FA_HW_EVENT_ENTRY_SIZE 4
1128 #define FA_NPIV_CONF0_ADDR 0x5C000
1129 #define FA_NPIV_CONF1_ADDR 0x5D000
1130 #define FA_FCP_PRIO0_ADDR 0x10000
1131 #define FA_FCP_PRIO1_ADDR 0x12000
1132
1133 /*
1134 * Flash Error Log Event Codes.
1135 */
1136 #define HW_EVENT_RESET_ERR 0xF00B
1137 #define HW_EVENT_ISP_ERR 0xF020
1138 #define HW_EVENT_PARITY_ERR 0xF022
1139 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
1140 #define HW_EVENT_FLASH_FW_ERR 0xF024
1141
1142 __le32 flash_data; /* Flash/NVRAM BIOS data. */
1143
1144 __le32 ctrl_status; /* Control/Status. */
1145 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
1146 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
1147 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
1148 #define CSRX_FUNCTION BIT_15 /* Function number. */
1149 /* PCI-X Bus Mode. */
1150 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
1151 #define PBM_PCI_33MHZ (0 << 8)
1152 #define PBM_PCIX_M1_66MHZ (1 << 8)
1153 #define PBM_PCIX_M1_100MHZ (2 << 8)
1154 #define PBM_PCIX_M1_133MHZ (3 << 8)
1155 #define PBM_PCIX_M2_66MHZ (5 << 8)
1156 #define PBM_PCIX_M2_100MHZ (6 << 8)
1157 #define PBM_PCIX_M2_133MHZ (7 << 8)
1158 #define PBM_PCI_66MHZ (8 << 8)
1159 /* Max Write Burst byte count. */
1160 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1161 #define MWB_512_BYTES (0 << 4)
1162 #define MWB_1024_BYTES (1 << 4)
1163 #define MWB_2048_BYTES (2 << 4)
1164 #define MWB_4096_BYTES (3 << 4)
1165
1166 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
1167 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1168 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1169
1170 __le32 ictrl; /* Interrupt control. */
1171 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
1172
1173 __le32 istatus; /* Interrupt status. */
1174 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
1175
1176 __le32 unused_1[2]; /* Gap. */
1177
1178 /* Request Queue. */
1179 __le32 req_q_in; /* In-Pointer. */
1180 __le32 req_q_out; /* Out-Pointer. */
1181 /* Response Queue. */
1182 __le32 rsp_q_in; /* In-Pointer. */
1183 __le32 rsp_q_out; /* Out-Pointer. */
1184 /* Priority Request Queue. */
1185 __le32 preq_q_in; /* In-Pointer. */
1186 __le32 preq_q_out; /* Out-Pointer. */
1187
1188 __le32 unused_2[2]; /* Gap. */
1189
1190 /* ATIO Queue. */
1191 __le32 atio_q_in; /* In-Pointer. */
1192 __le32 atio_q_out; /* Out-Pointer. */
1193
1194 __le32 host_status;
1195 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1196 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
1197
1198 __le32 hccr; /* Host command & control register. */
1199 /* HCCR statuses. */
1200 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
1201 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
1202 /* HCCR commands. */
1203 /* NOOP. */
1204 #define HCCRX_NOOP 0x00000000
1205 /* Set RISC Reset. */
1206 #define HCCRX_SET_RISC_RESET 0x10000000
1207 /* Clear RISC Reset. */
1208 #define HCCRX_CLR_RISC_RESET 0x20000000
1209 /* Set RISC Pause. */
1210 #define HCCRX_SET_RISC_PAUSE 0x30000000
1211 /* Releases RISC Pause. */
1212 #define HCCRX_REL_RISC_PAUSE 0x40000000
1213 /* Set HOST to RISC interrupt. */
1214 #define HCCRX_SET_HOST_INT 0x50000000
1215 /* Clear HOST to RISC interrupt. */
1216 #define HCCRX_CLR_HOST_INT 0x60000000
1217 /* Clear RISC to PCI interrupt. */
1218 #define HCCRX_CLR_RISC_INT 0xA0000000
1219
1220 __le32 gpiod; /* GPIO Data register. */
1221
1222 /* LED update mask. */
1223 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
1224 /* Data update mask. */
1225 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
1226 /* Data update mask. */
1227 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1228 /* LED control mask. */
1229 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1230 /* LED bit values. Color names as
1231 * referenced in fw spec.
1232 */
1233 #define GPDX_LED_YELLOW_ON BIT_2
1234 #define GPDX_LED_GREEN_ON BIT_3
1235 #define GPDX_LED_AMBER_ON BIT_4
1236 /* Data in/out. */
1237 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1238
1239 __le32 gpioe; /* GPIO Enable register. */
1240 /* Enable update mask. */
1241 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1242 /* Enable update mask. */
1243 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1244 /* Enable. */
1245 #define GPEX_ENABLE (BIT_1|BIT_0)
1246
1247 __le32 iobase_addr; /* I/O Bus Base Address register. */
1248
1249 __le32 unused_3[10]; /* Gap. */
1250
1251 __le16 mailbox0;
1252 __le16 mailbox1;
1253 __le16 mailbox2;
1254 __le16 mailbox3;
1255 __le16 mailbox4;
1256 __le16 mailbox5;
1257 __le16 mailbox6;
1258 __le16 mailbox7;
1259 __le16 mailbox8;
1260 __le16 mailbox9;
1261 __le16 mailbox10;
1262 __le16 mailbox11;
1263 __le16 mailbox12;
1264 __le16 mailbox13;
1265 __le16 mailbox14;
1266 __le16 mailbox15;
1267 __le16 mailbox16;
1268 __le16 mailbox17;
1269 __le16 mailbox18;
1270 __le16 mailbox19;
1271 __le16 mailbox20;
1272 __le16 mailbox21;
1273 __le16 mailbox22;
1274 __le16 mailbox23;
1275 __le16 mailbox24;
1276 __le16 mailbox25;
1277 __le16 mailbox26;
1278 __le16 mailbox27;
1279 __le16 mailbox28;
1280 __le16 mailbox29;
1281 __le16 mailbox30;
1282 __le16 mailbox31;
1283
1284 __le32 iobase_window;
1285 __le32 iobase_c4;
1286 __le32 iobase_c8;
1287 __le32 unused_4_1[6]; /* Gap. */
1288 __le32 iobase_q;
1289 __le32 unused_5[2]; /* Gap. */
1290 __le32 iobase_select;
1291 __le32 unused_6[2]; /* Gap. */
1292 __le32 iobase_sdata;
1293 };
1294 /* RISC-RISC semaphore register PCI offet */
1295 #define RISC_REGISTER_BASE_OFFSET 0x7010
1296 #define RISC_REGISTER_WINDOW_OFFSET 0x6
1297
1298 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1299
1300 #define RISC_SEMAPHORE 0x1UL
1301 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16)
1302 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
1303 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1304
1305 #define RISC_SEMAPHORE_FORCE 0x8000UL
1306 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16)
1307 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1308 #define RISC_SEMAPHORE_FORCE_SET \
1309 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1310
1311 /* RISC semaphore timeouts (ms) */
1312 #define TIMEOUT_SEMAPHORE 2500
1313 #define TIMEOUT_SEMAPHORE_FORCE 2000
1314 #define TIMEOUT_TOTAL_ELAPSED 4500
1315
1316 /* Trace Control *************************************************************/
1317
1318 #define TC_AEN_DISABLE 0
1319
1320 #define TC_EFT_ENABLE 4
1321 #define TC_EFT_DISABLE 5
1322
1323 #define TC_FCE_ENABLE 8
1324 #define TC_FCE_OPTIONS 0
1325 #define TC_FCE_DEFAULT_RX_SIZE 2112
1326 #define TC_FCE_DEFAULT_TX_SIZE 2112
1327 #define TC_FCE_DISABLE 9
1328 #define TC_FCE_DISABLE_TRACE BIT_0
1329
1330 /* MID Support ***************************************************************/
1331
1332 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
1333 #define MAX_MULTI_ID_FABRIC 256 /* ... */
1334
1335 struct mid_conf_entry_24xx {
1336 uint16_t reserved_1;
1337
1338 /*
1339 * BIT 0 = Enable Hard Loop Id
1340 * BIT 1 = Acquire Loop ID in LIPA
1341 * BIT 2 = ID not Acquired
1342 * BIT 3 = Enable VP
1343 * BIT 4 = Enable Initiator Mode
1344 * BIT 5 = Disable Target Mode
1345 * BIT 6-7 = Reserved
1346 */
1347 uint8_t options;
1348
1349 uint8_t hard_address;
1350
1351 uint8_t port_name[WWN_SIZE];
1352 uint8_t node_name[WWN_SIZE];
1353 };
1354
1355 struct mid_init_cb_24xx {
1356 struct init_cb_24xx init_cb;
1357
1358 __le16 count;
1359 __le16 options;
1360
1361 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1362 };
1363
1364
1365 struct mid_db_entry_24xx {
1366 uint16_t status;
1367 #define MDBS_NON_PARTIC BIT_3
1368 #define MDBS_ID_ACQUIRED BIT_1
1369 #define MDBS_ENABLED BIT_0
1370
1371 uint8_t options;
1372 uint8_t hard_address;
1373
1374 uint8_t port_name[WWN_SIZE];
1375 uint8_t node_name[WWN_SIZE];
1376
1377 uint8_t port_id[3];
1378 uint8_t reserved_1;
1379 };
1380
1381 /*
1382 * Virtual Port Control IOCB
1383 */
1384 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
1385 struct vp_ctrl_entry_24xx {
1386 uint8_t entry_type; /* Entry type. */
1387 uint8_t entry_count; /* Entry count. */
1388 uint8_t sys_define; /* System defined. */
1389 uint8_t entry_status; /* Entry Status. */
1390
1391 uint32_t handle; /* System handle. */
1392
1393 __le16 vp_idx_failed;
1394
1395 __le16 comp_status; /* Completion status. */
1396 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1397 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1398 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1399
1400 __le16 command;
1401 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1402 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1403 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1404 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1405 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1406
1407 __le16 vp_count;
1408
1409 uint8_t vp_idx_map[16];
1410 __le16 flags;
1411 __le16 id;
1412 uint16_t reserved_4;
1413 __le16 hopct;
1414 uint8_t reserved_5[24];
1415 };
1416
1417 /*
1418 * Modify Virtual Port Configuration IOCB
1419 */
1420 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
1421 struct vp_config_entry_24xx {
1422 uint8_t entry_type; /* Entry type. */
1423 uint8_t entry_count; /* Entry count. */
1424 uint8_t handle_count;
1425 uint8_t entry_status; /* Entry Status. */
1426
1427 uint32_t handle; /* System handle. */
1428
1429 __le16 flags;
1430 #define CS_VF_BIND_VPORTS_TO_VF BIT_0
1431 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
1432 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1433
1434 __le16 comp_status; /* Completion status. */
1435 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1436 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1437 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1438 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1439 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1440
1441 uint8_t command;
1442 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1443 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1444
1445 uint8_t vp_count;
1446
1447 uint8_t vp_index1;
1448 uint8_t vp_index2;
1449
1450 uint8_t options_idx1;
1451 uint8_t hard_address_idx1;
1452 uint16_t reserved_vp1;
1453 uint8_t port_name_idx1[WWN_SIZE];
1454 uint8_t node_name_idx1[WWN_SIZE];
1455
1456 uint8_t options_idx2;
1457 uint8_t hard_address_idx2;
1458 uint16_t reserved_vp2;
1459 uint8_t port_name_idx2[WWN_SIZE];
1460 uint8_t node_name_idx2[WWN_SIZE];
1461 __le16 id;
1462 uint16_t reserved_4;
1463 __le16 hopct;
1464 uint8_t reserved_5[2];
1465 };
1466
1467 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1468 enum VP_STATUS {
1469 VP_STAT_COMPL,
1470 VP_STAT_FAIL,
1471 VP_STAT_ID_CHG,
1472 VP_STAT_SNS_TO, /* timeout */
1473 VP_STAT_SNS_RJT,
1474 VP_STAT_SCR_TO, /* timeout */
1475 VP_STAT_SCR_RJT,
1476 };
1477
1478 enum VP_FLAGS {
1479 VP_FLAGS_CON_FLOOP = 1,
1480 VP_FLAGS_CON_P2P = 2,
1481 VP_FLAGS_CON_FABRIC = 3,
1482 VP_FLAGS_NAME_VALID = BIT_5,
1483 };
1484
1485 struct vp_rpt_id_entry_24xx {
1486 uint8_t entry_type; /* Entry type. */
1487 uint8_t entry_count; /* Entry count. */
1488 uint8_t sys_define; /* System defined. */
1489 uint8_t entry_status; /* Entry Status. */
1490 __le32 resv1;
1491 uint8_t vp_acquired;
1492 uint8_t vp_setup;
1493 uint8_t vp_idx; /* Format 0=reserved */
1494 uint8_t vp_status; /* Format 0=reserved */
1495
1496 uint8_t port_id[3];
1497 uint8_t format;
1498 union {
1499 struct _f0 {
1500 /* format 0 loop */
1501 uint8_t vp_idx_map[16];
1502 uint8_t reserved_4[32];
1503 } f0;
1504 struct _f1 {
1505 /* format 1 fabric */
1506 uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1507 uint8_t flags;
1508 #define TOPO_MASK 0xE
1509 #define TOPO_FL 0x2
1510 #define TOPO_N2N 0x4
1511 #define TOPO_F 0x6
1512
1513 uint16_t fip_flags;
1514 uint8_t rsv2[12];
1515
1516 uint8_t ls_rjt_vendor;
1517 uint8_t ls_rjt_explanation;
1518 uint8_t ls_rjt_reason;
1519 uint8_t rsv3[5];
1520
1521 uint8_t port_name[8];
1522 uint8_t node_name[8];
1523 uint16_t bbcr;
1524 uint8_t reserved_5[6];
1525 } f1;
1526 struct _f2 { /* format 2: N2N direct connect */
1527 uint8_t vpstat1_subcode;
1528 uint8_t flags;
1529 uint16_t fip_flags;
1530 uint8_t rsv2[12];
1531
1532 uint8_t ls_rjt_vendor;
1533 uint8_t ls_rjt_explanation;
1534 uint8_t ls_rjt_reason;
1535 uint8_t rsv3[5];
1536
1537 uint8_t port_name[8];
1538 uint8_t node_name[8];
1539 uint16_t bbcr;
1540 uint8_t reserved_5[2];
1541 uint8_t remote_nport_id[4];
1542 } f2;
1543 } u;
1544 };
1545
1546 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1547 struct vf_evfp_entry_24xx {
1548 uint8_t entry_type; /* Entry type. */
1549 uint8_t entry_count; /* Entry count. */
1550 uint8_t sys_define; /* System defined. */
1551 uint8_t entry_status; /* Entry Status. */
1552
1553 uint32_t handle; /* System handle. */
1554 __le16 comp_status; /* Completion status. */
1555 __le16 timeout; /* timeout */
1556 __le16 adim_tagging_mode;
1557
1558 __le16 vfport_id;
1559 uint32_t exch_addr;
1560
1561 __le16 nport_handle; /* N_PORT handle. */
1562 __le16 control_flags;
1563 uint32_t io_parameter_0;
1564 uint32_t io_parameter_1;
1565 __le64 tx_address __packed; /* Data segment 0 address. */
1566 uint32_t tx_len; /* Data segment 0 length. */
1567 __le64 rx_address __packed; /* Data segment 1 address. */
1568 uint32_t rx_len; /* Data segment 1 length. */
1569 };
1570
1571 /* END MID Support ***********************************************************/
1572
1573 /* Flash Description Table ***************************************************/
1574
1575 struct qla_fdt_layout {
1576 uint8_t sig[4];
1577 __le16 version;
1578 __le16 len;
1579 __le16 checksum;
1580 uint8_t unused1[2];
1581 uint8_t model[16];
1582 __le16 man_id;
1583 __le16 id;
1584 uint8_t flags;
1585 uint8_t erase_cmd;
1586 uint8_t alt_erase_cmd;
1587 uint8_t wrt_enable_cmd;
1588 uint8_t wrt_enable_bits;
1589 uint8_t wrt_sts_reg_cmd;
1590 uint8_t unprotect_sec_cmd;
1591 uint8_t read_man_id_cmd;
1592 __le32 block_size;
1593 __le32 alt_block_size;
1594 __le32 flash_size;
1595 __le32 wrt_enable_data;
1596 uint8_t read_id_addr_len;
1597 uint8_t wrt_disable_bits;
1598 uint8_t read_dev_id_len;
1599 uint8_t chip_erase_cmd;
1600 __le16 read_timeout;
1601 uint8_t protect_sec_cmd;
1602 uint8_t unused2[65];
1603 };
1604
1605 /* Flash Layout Table ********************************************************/
1606
1607 struct qla_flt_location {
1608 uint8_t sig[4];
1609 __le16 start_lo;
1610 __le16 start_hi;
1611 uint8_t version;
1612 uint8_t unused[5];
1613 __le16 checksum;
1614 };
1615
1616 #define FLT_REG_FW 0x01
1617 #define FLT_REG_BOOT_CODE 0x07
1618 #define FLT_REG_VPD_0 0x14
1619 #define FLT_REG_NVRAM_0 0x15
1620 #define FLT_REG_VPD_1 0x16
1621 #define FLT_REG_NVRAM_1 0x17
1622 #define FLT_REG_VPD_2 0xD4
1623 #define FLT_REG_NVRAM_2 0xD5
1624 #define FLT_REG_VPD_3 0xD6
1625 #define FLT_REG_NVRAM_3 0xD7
1626 #define FLT_REG_FDT 0x1a
1627 #define FLT_REG_FLT 0x1c
1628 #define FLT_REG_HW_EVENT_0 0x1d
1629 #define FLT_REG_HW_EVENT_1 0x1f
1630 #define FLT_REG_NPIV_CONF_0 0x29
1631 #define FLT_REG_NPIV_CONF_1 0x2a
1632 #define FLT_REG_GOLD_FW 0x2f
1633 #define FLT_REG_FCP_PRIO_0 0x87
1634 #define FLT_REG_FCP_PRIO_1 0x88
1635 #define FLT_REG_CNA_FW 0x97
1636 #define FLT_REG_BOOT_CODE_8044 0xA2
1637 #define FLT_REG_FCOE_FW 0xA4
1638 #define FLT_REG_FCOE_NVRAM_0 0xAA
1639 #define FLT_REG_FCOE_NVRAM_1 0xAC
1640
1641 /* 27xx */
1642 #define FLT_REG_IMG_PRI_27XX 0x95
1643 #define FLT_REG_IMG_SEC_27XX 0x96
1644 #define FLT_REG_FW_SEC_27XX 0x02
1645 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
1646 #define FLT_REG_VPD_SEC_27XX_0 0x50
1647 #define FLT_REG_VPD_SEC_27XX_1 0x52
1648 #define FLT_REG_VPD_SEC_27XX_2 0xD8
1649 #define FLT_REG_VPD_SEC_27XX_3 0xDA
1650
1651 /* 28xx */
1652 #define FLT_REG_AUX_IMG_PRI_28XX 0x125
1653 #define FLT_REG_AUX_IMG_SEC_28XX 0x126
1654 #define FLT_REG_VPD_SEC_28XX_0 0x10C
1655 #define FLT_REG_VPD_SEC_28XX_1 0x10E
1656 #define FLT_REG_VPD_SEC_28XX_2 0x110
1657 #define FLT_REG_VPD_SEC_28XX_3 0x112
1658 #define FLT_REG_NVRAM_SEC_28XX_0 0x10D
1659 #define FLT_REG_NVRAM_SEC_28XX_1 0x10F
1660 #define FLT_REG_NVRAM_SEC_28XX_2 0x111
1661 #define FLT_REG_NVRAM_SEC_28XX_3 0x113
1662 #define FLT_REG_MPI_PRI_28XX 0xD3
1663 #define FLT_REG_MPI_SEC_28XX 0xF0
1664 #define FLT_REG_PEP_PRI_28XX 0xD1
1665 #define FLT_REG_PEP_SEC_28XX 0xF1
1666
1667 struct qla_flt_region {
1668 __le16 code;
1669 uint8_t attribute;
1670 uint8_t reserved;
1671 __le32 size;
1672 __le32 start;
1673 __le32 end;
1674 };
1675
1676 struct qla_flt_header {
1677 __le16 version;
1678 __le16 length;
1679 __le16 checksum;
1680 __le16 unused;
1681 struct qla_flt_region region[0];
1682 };
1683
1684 #define FLT_REGION_SIZE 16
1685 #define FLT_MAX_REGIONS 0xFF
1686 #define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
1687
1688 /* Flash NPIV Configuration Table ********************************************/
1689
1690 struct qla_npiv_header {
1691 uint8_t sig[2];
1692 __le16 version;
1693 __le16 entries;
1694 __le16 unused[4];
1695 __le16 checksum;
1696 };
1697
1698 struct qla_npiv_entry {
1699 __le16 flags;
1700 __le16 vf_id;
1701 uint8_t q_qos;
1702 uint8_t f_qos;
1703 __le16 unused1;
1704 uint8_t port_name[WWN_SIZE];
1705 uint8_t node_name[WWN_SIZE];
1706 };
1707
1708 /* 84XX Support **************************************************************/
1709
1710 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1711 #define A84_PANIC_RECOVERY 0x1
1712 #define A84_OP_LOGIN_COMPLETE 0x2
1713 #define A84_DIAG_LOGIN_COMPLETE 0x3
1714 #define A84_GOLD_LOGIN_COMPLETE 0x4
1715
1716 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1717
1718 #define FSTATE_REMOTE_FC_DOWN BIT_0
1719 #define FSTATE_NSL_LINK_DOWN BIT_1
1720 #define FSTATE_IS_DIAG_FW BIT_2
1721 #define FSTATE_LOGGED_IN BIT_3
1722 #define FSTATE_WAITING_FOR_VERIFY BIT_4
1723
1724 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1725 struct verify_chip_entry_84xx {
1726 uint8_t entry_type;
1727 uint8_t entry_count;
1728 uint8_t sys_defined;
1729 uint8_t entry_status;
1730
1731 uint32_t handle;
1732
1733 __le16 options;
1734 #define VCO_DONT_UPDATE_FW BIT_0
1735 #define VCO_FORCE_UPDATE BIT_1
1736 #define VCO_DONT_RESET_UPDATE BIT_2
1737 #define VCO_DIAG_FW BIT_3
1738 #define VCO_END_OF_DATA BIT_14
1739 #define VCO_ENABLE_DSD BIT_15
1740
1741 __le16 reserved_1;
1742
1743 __le16 data_seg_cnt;
1744 __le16 reserved_2[3];
1745
1746 __le32 fw_ver;
1747 __le32 exchange_address;
1748
1749 __le32 reserved_3[3];
1750 __le32 fw_size;
1751 __le32 fw_seq_size;
1752 __le32 relative_offset;
1753
1754 struct dsd64 dsd;
1755 };
1756
1757 struct verify_chip_rsp_84xx {
1758 uint8_t entry_type;
1759 uint8_t entry_count;
1760 uint8_t sys_defined;
1761 uint8_t entry_status;
1762
1763 uint32_t handle;
1764
1765 __le16 comp_status;
1766 #define CS_VCS_CHIP_FAILURE 0x3
1767 #define CS_VCS_BAD_EXCHANGE 0x8
1768 #define CS_VCS_SEQ_COMPLETEi 0x40
1769
1770 __le16 failure_code;
1771 #define VFC_CHECKSUM_ERROR 0x1
1772 #define VFC_INVALID_LEN 0x2
1773 #define VFC_ALREADY_IN_PROGRESS 0x8
1774
1775 __le16 reserved_1[4];
1776
1777 __le32 fw_ver;
1778 __le32 exchange_address;
1779
1780 __le32 reserved_2[6];
1781 };
1782
1783 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1784 struct access_chip_84xx {
1785 uint8_t entry_type;
1786 uint8_t entry_count;
1787 uint8_t sys_defined;
1788 uint8_t entry_status;
1789
1790 uint32_t handle;
1791
1792 __le16 options;
1793 #define ACO_DUMP_MEMORY 0x0
1794 #define ACO_LOAD_MEMORY 0x1
1795 #define ACO_CHANGE_CONFIG_PARAM 0x2
1796 #define ACO_REQUEST_INFO 0x3
1797
1798 __le16 reserved1;
1799
1800 __le16 dseg_count;
1801 __le16 reserved2[3];
1802
1803 __le32 parameter1;
1804 __le32 parameter2;
1805 __le32 parameter3;
1806
1807 __le32 reserved3[3];
1808 __le32 total_byte_cnt;
1809 __le32 reserved4;
1810
1811 struct dsd64 dsd;
1812 };
1813
1814 struct access_chip_rsp_84xx {
1815 uint8_t entry_type;
1816 uint8_t entry_count;
1817 uint8_t sys_defined;
1818 uint8_t entry_status;
1819
1820 uint32_t handle;
1821
1822 __le16 comp_status;
1823 __le16 failure_code;
1824 __le32 residual_count;
1825
1826 __le32 reserved[12];
1827 };
1828
1829 /* 81XX Support **************************************************************/
1830
1831 #define MBA_DCBX_START 0x8016
1832 #define MBA_DCBX_COMPLETE 0x8030
1833 #define MBA_FCF_CONF_ERR 0x8031
1834 #define MBA_DCBX_PARAM_UPDATE 0x8032
1835 #define MBA_IDC_COMPLETE 0x8100
1836 #define MBA_IDC_NOTIFY 0x8101
1837 #define MBA_IDC_TIME_EXT 0x8102
1838
1839 #define MBC_IDC_ACK 0x101
1840 #define MBC_RESTART_MPI_FW 0x3d
1841 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1842 #define MBC_GET_XGMAC_STATS 0x7a
1843 #define MBC_GET_DCBX_PARAMS 0x51
1844
1845 /*
1846 * ISP83xx mailbox commands
1847 */
1848 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1849 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
1850 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
1851 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
1852
1853 /* Flash access control option field bit definitions */
1854 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
1855 #define FAC_OPT_REQUESTOR_ID BIT_14
1856 #define FAC_OPT_CMD_SUBCODE 0xff
1857
1858 /* Flash access control command subcodes */
1859 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1860 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1861 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1862 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1863 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1864 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1865
1866 /* enhanced features bit definitions */
1867 #define NEF_LR_DIST_ENABLE BIT_0
1868
1869 /* LR Distance bit positions */
1870 #define LR_DIST_NV_POS 2
1871 #define LR_DIST_NV_MASK 0xf
1872 #define LR_DIST_FW_POS 12
1873
1874 /* FAC semaphore defines */
1875 #define FAC_SEMAPHORE_UNLOCK 0
1876 #define FAC_SEMAPHORE_LOCK 1
1877
1878 struct nvram_81xx {
1879 /* NVRAM header. */
1880 uint8_t id[4];
1881 __le16 nvram_version;
1882 __le16 reserved_0;
1883
1884 /* Firmware Initialization Control Block. */
1885 __le16 version;
1886 __le16 reserved_1;
1887 __le16 frame_payload_size;
1888 __le16 execution_throttle;
1889 __le16 exchange_count;
1890 __le16 reserved_2;
1891
1892 uint8_t port_name[WWN_SIZE];
1893 uint8_t node_name[WWN_SIZE];
1894
1895 __le16 login_retry_count;
1896 __le16 reserved_3;
1897 __le16 interrupt_delay_timer;
1898 __le16 login_timeout;
1899
1900 __le32 firmware_options_1;
1901 __le32 firmware_options_2;
1902 __le32 firmware_options_3;
1903
1904 __le16 reserved_4[4];
1905
1906 /* Offset 64. */
1907 uint8_t enode_mac[6];
1908 __le16 reserved_5[5];
1909
1910 /* Offset 80. */
1911 __le16 reserved_6[24];
1912
1913 /* Offset 128. */
1914 __le16 ex_version;
1915 uint8_t prio_fcf_matching_flags;
1916 uint8_t reserved_6_1[3];
1917 __le16 pri_fcf_vlan_id;
1918 uint8_t pri_fcf_fabric_name[8];
1919 __le16 reserved_6_2[7];
1920 uint8_t spma_mac_addr[6];
1921 __le16 reserved_6_3[14];
1922
1923 /* Offset 192. */
1924 uint8_t min_supported_speed;
1925 uint8_t reserved_7_0;
1926 __le16 reserved_7[31];
1927
1928 /*
1929 * BIT 0 = Enable spinup delay
1930 * BIT 1 = Disable BIOS
1931 * BIT 2 = Enable Memory Map BIOS
1932 * BIT 3 = Enable Selectable Boot
1933 * BIT 4 = Disable RISC code load
1934 * BIT 5 = Disable Serdes
1935 * BIT 6 = Opt boot mode
1936 * BIT 7 = Interrupt enable
1937 *
1938 * BIT 8 = EV Control enable
1939 * BIT 9 = Enable lip reset
1940 * BIT 10 = Enable lip full login
1941 * BIT 11 = Enable target reset
1942 * BIT 12 = Stop firmware
1943 * BIT 13 = Enable nodename option
1944 * BIT 14 = Default WWPN valid
1945 * BIT 15 = Enable alternate WWN
1946 *
1947 * BIT 16 = CLP LUN string
1948 * BIT 17 = CLP Target string
1949 * BIT 18 = CLP BIOS enable string
1950 * BIT 19 = CLP Serdes string
1951 * BIT 20 = CLP WWPN string
1952 * BIT 21 = CLP WWNN string
1953 * BIT 22 =
1954 * BIT 23 =
1955 * BIT 24 = Keep WWPN
1956 * BIT 25 = Temp WWPN
1957 * BIT 26-31 =
1958 */
1959 __le32 host_p;
1960
1961 uint8_t alternate_port_name[WWN_SIZE];
1962 uint8_t alternate_node_name[WWN_SIZE];
1963
1964 uint8_t boot_port_name[WWN_SIZE];
1965 __le16 boot_lun_number;
1966 __le16 reserved_8;
1967
1968 uint8_t alt1_boot_port_name[WWN_SIZE];
1969 __le16 alt1_boot_lun_number;
1970 __le16 reserved_9;
1971
1972 uint8_t alt2_boot_port_name[WWN_SIZE];
1973 __le16 alt2_boot_lun_number;
1974 __le16 reserved_10;
1975
1976 uint8_t alt3_boot_port_name[WWN_SIZE];
1977 __le16 alt3_boot_lun_number;
1978 __le16 reserved_11;
1979
1980 /*
1981 * BIT 0 = Selective Login
1982 * BIT 1 = Alt-Boot Enable
1983 * BIT 2 = Reserved
1984 * BIT 3 = Boot Order List
1985 * BIT 4 = Reserved
1986 * BIT 5 = Selective LUN
1987 * BIT 6 = Reserved
1988 * BIT 7-31 =
1989 */
1990 __le32 efi_parameters;
1991
1992 uint8_t reset_delay;
1993 uint8_t reserved_12;
1994 __le16 reserved_13;
1995
1996 __le16 boot_id_number;
1997 __le16 reserved_14;
1998
1999 __le16 max_luns_per_target;
2000 __le16 reserved_15;
2001
2002 __le16 port_down_retry_count;
2003 __le16 link_down_timeout;
2004
2005 /* FCode parameters. */
2006 __le16 fcode_parameter;
2007
2008 __le16 reserved_16[3];
2009
2010 /* Offset 352. */
2011 uint8_t reserved_17[4];
2012 __le16 reserved_18[5];
2013 uint8_t reserved_19[2];
2014 __le16 reserved_20[8];
2015
2016 /* Offset 384. */
2017 uint8_t reserved_21[16];
2018 __le16 reserved_22[3];
2019
2020 /* Offset 406 (0x196) Enhanced Features
2021 * BIT 0 = Extended BB credits for LR
2022 * BIT 1 = Virtual Fabric Enable
2023 * BIT 2-5 = Distance Support if BIT 0 is on
2024 * BIT 6 = Prefer FCP
2025 * BIT 7 = SCM Disabled if BIT is set (1)
2026 * BIT 8-15 = Unused
2027 */
2028 uint16_t enhanced_features;
2029
2030 uint16_t reserved_24[4];
2031
2032 /* Offset 416. */
2033 __le16 reserved_25[32];
2034
2035 /* Offset 480. */
2036 uint8_t model_name[16];
2037
2038 /* Offset 496. */
2039 __le16 feature_mask_l;
2040 __le16 feature_mask_h;
2041 __le16 reserved_26[2];
2042
2043 __le16 subsystem_vendor_id;
2044 __le16 subsystem_device_id;
2045
2046 __le32 checksum;
2047 };
2048
2049 /*
2050 * ISP Initialization Control Block.
2051 * Little endian except where noted.
2052 */
2053 #define ICB_VERSION 1
2054 struct init_cb_81xx {
2055 __le16 version;
2056 __le16 reserved_1;
2057
2058 __le16 frame_payload_size;
2059 __le16 execution_throttle;
2060 __le16 exchange_count;
2061
2062 __le16 reserved_2;
2063
2064 uint8_t port_name[WWN_SIZE]; /* Big endian. */
2065 uint8_t node_name[WWN_SIZE]; /* Big endian. */
2066
2067 __le16 response_q_inpointer;
2068 __le16 request_q_outpointer;
2069
2070 __le16 login_retry_count;
2071
2072 __le16 prio_request_q_outpointer;
2073
2074 __le16 response_q_length;
2075 __le16 request_q_length;
2076
2077 __le16 reserved_3;
2078
2079 __le16 prio_request_q_length;
2080
2081 __le64 request_q_address __packed;
2082 __le64 response_q_address __packed;
2083 __le64 prio_request_q_address __packed;
2084
2085 uint8_t reserved_4[8];
2086
2087 __le16 atio_q_inpointer;
2088 __le16 atio_q_length;
2089 __le64 atio_q_address __packed;
2090
2091 __le16 interrupt_delay_timer; /* 100us increments. */
2092 __le16 login_timeout;
2093
2094 /*
2095 * BIT 0-3 = Reserved
2096 * BIT 4 = Enable Target Mode
2097 * BIT 5 = Disable Initiator Mode
2098 * BIT 6 = Reserved
2099 * BIT 7 = Reserved
2100 *
2101 * BIT 8-13 = Reserved
2102 * BIT 14 = Node Name Option
2103 * BIT 15-31 = Reserved
2104 */
2105 __le32 firmware_options_1;
2106
2107 /*
2108 * BIT 0 = Operation Mode bit 0
2109 * BIT 1 = Operation Mode bit 1
2110 * BIT 2 = Operation Mode bit 2
2111 * BIT 3 = Operation Mode bit 3
2112 * BIT 4-7 = Reserved
2113 *
2114 * BIT 8 = Enable Class 2
2115 * BIT 9 = Enable ACK0
2116 * BIT 10 = Reserved
2117 * BIT 11 = Enable FC-SP Security
2118 * BIT 12 = FC Tape Enable
2119 * BIT 13 = Reserved
2120 * BIT 14 = Enable Target PRLI Control
2121 * BIT 15-31 = Reserved
2122 */
2123 __le32 firmware_options_2;
2124
2125 /*
2126 * BIT 0-3 = Reserved
2127 * BIT 4 = FCP RSP Payload bit 0
2128 * BIT 5 = FCP RSP Payload bit 1
2129 * BIT 6 = Enable Receive Out-of-Order data frame handling
2130 * BIT 7 = Reserved
2131 *
2132 * BIT 8 = Reserved
2133 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
2134 * BIT 10-16 = Reserved
2135 * BIT 17 = Enable multiple FCFs
2136 * BIT 18-20 = MAC addressing mode
2137 * BIT 21-25 = Ethernet data rate
2138 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
2139 * BIT 27 = Enable ethernet header rx IOCB for response q
2140 * BIT 28 = SPMA selection bit 0
2141 * BIT 28 = SPMA selection bit 1
2142 * BIT 30-31 = Reserved
2143 */
2144 __le32 firmware_options_3;
2145
2146 uint8_t reserved_5[8];
2147
2148 uint8_t enode_mac[6];
2149
2150 uint8_t reserved_6[10];
2151 };
2152
2153 struct mid_init_cb_81xx {
2154 struct init_cb_81xx init_cb;
2155
2156 uint16_t count;
2157 uint16_t options;
2158
2159 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
2160 };
2161
2162 struct ex_init_cb_81xx {
2163 uint16_t ex_version;
2164 uint8_t prio_fcf_matching_flags;
2165 uint8_t reserved_1[3];
2166 uint16_t pri_fcf_vlan_id;
2167 uint8_t pri_fcf_fabric_name[8];
2168 uint16_t reserved_2[7];
2169 uint8_t spma_mac_addr[6];
2170 uint16_t reserved_3[14];
2171 };
2172
2173 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
2174 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
2175 #define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
2176 #define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
2177
2178 /* FCP priority config defines *************************************/
2179 /* operations */
2180 #define QLFC_FCP_PRIO_DISABLE 0x0
2181 #define QLFC_FCP_PRIO_ENABLE 0x1
2182 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
2183 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
2184
2185 struct qla_fcp_prio_entry {
2186 uint16_t flags; /* Describes parameter(s) in FCP */
2187 /* priority entry that are valid */
2188 #define FCP_PRIO_ENTRY_VALID 0x1
2189 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
2190 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
2191 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
2192 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
2193 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
2194 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
2195 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
2196 uint8_t tag; /* Priority value */
2197 uint8_t reserved; /* Reserved for future use */
2198 uint32_t src_pid; /* Src port id. high order byte */
2199 /* unused; -1 (wild card) */
2200 uint32_t dst_pid; /* Src port id. high order byte */
2201 /* unused; -1 (wild card) */
2202 uint16_t lun_beg; /* 1st lun num of lun range. */
2203 /* -1 (wild card) */
2204 uint16_t lun_end; /* 2nd lun num of lun range. */
2205 /* -1 (wild card) */
2206 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */
2207 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */
2208 };
2209
2210 struct qla_fcp_prio_cfg {
2211 uint8_t signature[4]; /* "HQOS" signature of config data */
2212 uint16_t version; /* 1: Initial version */
2213 uint16_t length; /* config data size in num bytes */
2214 uint16_t checksum; /* config data bytes checksum */
2215 uint16_t num_entries; /* Number of entries */
2216 uint16_t size_of_entry; /* Size of each entry in num bytes */
2217 uint8_t attributes; /* enable/disable, persistence */
2218 #define FCP_PRIO_ATTR_DISABLE 0x0
2219 #define FCP_PRIO_ATTR_ENABLE 0x1
2220 #define FCP_PRIO_ATTR_PERSIST 0x2
2221 uint8_t reserved; /* Reserved for future use */
2222 #define FCP_PRIO_CFG_HDR_SIZE offsetof(struct qla_fcp_prio_cfg, entry)
2223 struct qla_fcp_prio_entry entry[1023]; /* fcp priority entries */
2224 uint8_t reserved2[16];
2225 };
2226
2227 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
2228
2229 /* 25XX Support ****************************************************/
2230 #define FA_FCP_PRIO0_ADDR_25 0x3C000
2231 #define FA_FCP_PRIO1_ADDR_25 0x3E000
2232
2233 /* 81XX Flash locations -- occupies second 2MB region. */
2234 #define FA_BOOT_CODE_ADDR_81 0x80000
2235 #define FA_RISC_CODE_ADDR_81 0xA0000
2236 #define FA_FW_AREA_ADDR_81 0xC0000
2237 #define FA_VPD_NVRAM_ADDR_81 0xD0000
2238 #define FA_VPD0_ADDR_81 0xD0000
2239 #define FA_VPD1_ADDR_81 0xD0400
2240 #define FA_NVRAM0_ADDR_81 0xD0080
2241 #define FA_NVRAM1_ADDR_81 0xD0180
2242 #define FA_FEATURE_ADDR_81 0xD4000
2243 #define FA_FLASH_DESCR_ADDR_81 0xD8000
2244 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2245 #define FA_HW_EVENT0_ADDR_81 0xDC000
2246 #define FA_HW_EVENT1_ADDR_81 0xDC400
2247 #define FA_NPIV_CONF0_ADDR_81 0xD1000
2248 #define FA_NPIV_CONF1_ADDR_81 0xD2000
2249
2250 /* 83XX Flash locations -- occupies second 8MB region. */
2251 #define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2252 #define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2253
2254 #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196
2255
2256 #endif
Linux with added FPC-III support