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WIP FPC-III support
[linux/fpc-iii.git] / drivers / scsi / ufs / ufs-qcom.c
blob2206b1e4b7740d209dfa31206f387521d86ddc39
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/time.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/reset-controller.h>
13 #include <linux/devfreq.h>
14
15 #include "ufshcd.h"
16 #include "ufshcd-pltfrm.h"
17 #include "unipro.h"
18 #include "ufs-qcom.h"
19 #include "ufshci.h"
20 #include "ufs_quirks.h"
21 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
22 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
23
24 enum {
25 TSTBUS_UAWM,
26 TSTBUS_UARM,
27 TSTBUS_TXUC,
28 TSTBUS_RXUC,
29 TSTBUS_DFC,
30 TSTBUS_TRLUT,
31 TSTBUS_TMRLUT,
32 TSTBUS_OCSC,
33 TSTBUS_UTP_HCI,
34 TSTBUS_COMBINED,
35 TSTBUS_WRAPPER,
36 TSTBUS_UNIPRO,
37 TSTBUS_MAX,
38 };
39
40 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
41
42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
44 u32 clk_cycles);
45
46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
47 {
48 return container_of(rcd, struct ufs_qcom_host, rcdev);
49 }
50
51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
52 const char *prefix, void *priv)
53 {
54 ufshcd_dump_regs(hba, offset, len * 4, prefix);
55 }
56
57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
58 {
59 int err = 0;
60
61 err = ufshcd_dme_get(hba,
62 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
63 if (err)
64 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
65 __func__, err);
66
67 return err;
68 }
69
70 static int ufs_qcom_host_clk_get(struct device *dev,
71 const char *name, struct clk **clk_out, bool optional)
72 {
73 struct clk *clk;
74 int err = 0;
75
76 clk = devm_clk_get(dev, name);
77 if (!IS_ERR(clk)) {
78 *clk_out = clk;
79 return 0;
80 }
81
82 err = PTR_ERR(clk);
83
84 if (optional && err == -ENOENT) {
85 *clk_out = NULL;
86 return 0;
87 }
88
89 if (err != -EPROBE_DEFER)
90 dev_err(dev, "failed to get %s err %d\n", name, err);
91
92 return err;
93 }
94
95 static int ufs_qcom_host_clk_enable(struct device *dev,
96 const char *name, struct clk *clk)
97 {
98 int err = 0;
99
100 err = clk_prepare_enable(clk);
101 if (err)
102 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
103
104 return err;
105 }
106
107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
108 {
109 if (!host->is_lane_clks_enabled)
110 return;
111
112 clk_disable_unprepare(host->tx_l1_sync_clk);
113 clk_disable_unprepare(host->tx_l0_sync_clk);
114 clk_disable_unprepare(host->rx_l1_sync_clk);
115 clk_disable_unprepare(host->rx_l0_sync_clk);
116
117 host->is_lane_clks_enabled = false;
118 }
119
120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
121 {
122 int err = 0;
123 struct device *dev = host->hba->dev;
124
125 if (host->is_lane_clks_enabled)
126 return 0;
127
128 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
129 host->rx_l0_sync_clk);
130 if (err)
131 goto out;
132
133 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
134 host->tx_l0_sync_clk);
135 if (err)
136 goto disable_rx_l0;
137
138 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
139 host->rx_l1_sync_clk);
140 if (err)
141 goto disable_tx_l0;
142
143 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
144 host->tx_l1_sync_clk);
145 if (err)
146 goto disable_rx_l1;
147
148 host->is_lane_clks_enabled = true;
149 goto out;
150
151 disable_rx_l1:
152 clk_disable_unprepare(host->rx_l1_sync_clk);
153 disable_tx_l0:
154 clk_disable_unprepare(host->tx_l0_sync_clk);
155 disable_rx_l0:
156 clk_disable_unprepare(host->rx_l0_sync_clk);
157 out:
158 return err;
159 }
160
161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
162 {
163 int err = 0;
164 struct device *dev = host->hba->dev;
165
166 if (has_acpi_companion(dev))
167 return 0;
168
169 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
170 &host->rx_l0_sync_clk, false);
171 if (err)
172 goto out;
173
174 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
175 &host->tx_l0_sync_clk, false);
176 if (err)
177 goto out;
178
179 /* In case of single lane per direction, don't read lane1 clocks */
180 if (host->hba->lanes_per_direction > 1) {
181 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
182 &host->rx_l1_sync_clk, false);
183 if (err)
184 goto out;
185
186 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
187 &host->tx_l1_sync_clk, true);
188 }
189 out:
190 return err;
191 }
192
193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
194 {
195 u32 tx_lanes;
196
197 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
198 }
199
200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
201 {
202 int err;
203 u32 tx_fsm_val = 0;
204 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
205
206 do {
207 err = ufshcd_dme_get(hba,
208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
209 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
210 &tx_fsm_val);
211 if (err || tx_fsm_val == TX_FSM_HIBERN8)
212 break;
213
214 /* sleep for max. 200us */
215 usleep_range(100, 200);
216 } while (time_before(jiffies, timeout));
217
218 /*
219 * we might have scheduled out for long during polling so
220 * check the state again.
221 */
222 if (time_after(jiffies, timeout))
223 err = ufshcd_dme_get(hba,
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
225 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
226 &tx_fsm_val);
227
228 if (err) {
229 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
230 __func__, err);
231 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
232 err = tx_fsm_val;
233 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
234 __func__, err);
235 }
236
237 return err;
238 }
239
240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
241 {
242 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
243 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
244 REG_UFS_CFG1);
245 /* make sure above configuration is applied before we return */
246 mb();
247 }
248
249 /*
250 * ufs_qcom_host_reset - reset host controller and PHY
251 */
252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
253 {
254 int ret = 0;
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
256
257 if (!host->core_reset) {
258 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
259 goto out;
260 }
261
262 ret = reset_control_assert(host->core_reset);
263 if (ret) {
264 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
265 __func__, ret);
266 goto out;
267 }
268
269 /*
270 * The hardware requirement for delay between assert/deassert
271 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
272 * ~125us (4/32768). To be on the safe side add 200us delay.
273 */
274 usleep_range(200, 210);
275
276 ret = reset_control_deassert(host->core_reset);
277 if (ret)
278 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
279 __func__, ret);
280
281 usleep_range(1000, 1100);
282
283 out:
284 return ret;
285 }
286
287 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
288 {
289 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
290 struct phy *phy = host->generic_phy;
291 int ret = 0;
292 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
293 ? true : false;
294
295 /* Reset UFS Host Controller and PHY */
296 ret = ufs_qcom_host_reset(hba);
297 if (ret)
298 dev_warn(hba->dev, "%s: host reset returned %d\n",
299 __func__, ret);
300
301 if (is_rate_B)
302 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
303
304 /* phy initialization - calibrate the phy */
305 ret = phy_init(phy);
306 if (ret) {
307 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
308 __func__, ret);
309 goto out;
310 }
311
312 /* power on phy - start serdes and phy's power and clocks */
313 ret = phy_power_on(phy);
314 if (ret) {
315 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
316 __func__, ret);
317 goto out_disable_phy;
318 }
319
320 ufs_qcom_select_unipro_mode(host);
321
322 return 0;
323
324 out_disable_phy:
325 phy_exit(phy);
326 out:
327 return ret;
328 }
329
330 /*
331 * The UTP controller has a number of internal clock gating cells (CGCs).
332 * Internal hardware sub-modules within the UTP controller control the CGCs.
333 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
334 * in a specific operation, UTP controller CGCs are by default disabled and
335 * this function enables them (after every UFS link startup) to save some power
336 * leakage.
337 */
338 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
339 {
340 ufshcd_writel(hba,
341 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
342 REG_UFS_CFG2);
343
344 /* Ensure that HW clock gating is enabled before next operations */
345 mb();
346 }
347
348 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
349 enum ufs_notify_change_status status)
350 {
351 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
352 int err = 0;
353
354 switch (status) {
355 case PRE_CHANGE:
356 ufs_qcom_power_up_sequence(hba);
357 /*
358 * The PHY PLL output is the source of tx/rx lane symbol
359 * clocks, hence, enable the lane clocks only after PHY
360 * is initialized.
361 */
362 err = ufs_qcom_enable_lane_clks(host);
363 break;
364 case POST_CHANGE:
365 /* check if UFS PHY moved from DISABLED to HIBERN8 */
366 err = ufs_qcom_check_hibern8(hba);
367 ufs_qcom_enable_hw_clk_gating(hba);
368 ufs_qcom_ice_enable(host);
369 break;
370 default:
371 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
372 err = -EINVAL;
373 break;
374 }
375 return err;
376 }
377
378 /*
379 * Returns zero for success and non-zero in case of a failure
380 */
381 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
382 u32 hs, u32 rate, bool update_link_startup_timer)
383 {
384 int ret = 0;
385 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
386 struct ufs_clk_info *clki;
387 u32 core_clk_period_in_ns;
388 u32 tx_clk_cycles_per_us = 0;
389 unsigned long core_clk_rate = 0;
390 u32 core_clk_cycles_per_us = 0;
391
392 static u32 pwm_fr_table[][2] = {
393 {UFS_PWM_G1, 0x1},
394 {UFS_PWM_G2, 0x1},
395 {UFS_PWM_G3, 0x1},
396 {UFS_PWM_G4, 0x1},
397 };
398
399 static u32 hs_fr_table_rA[][2] = {
400 {UFS_HS_G1, 0x1F},
401 {UFS_HS_G2, 0x3e},
402 {UFS_HS_G3, 0x7D},
403 };
404
405 static u32 hs_fr_table_rB[][2] = {
406 {UFS_HS_G1, 0x24},
407 {UFS_HS_G2, 0x49},
408 {UFS_HS_G3, 0x92},
409 };
410
411 /*
412 * The Qunipro controller does not use following registers:
413 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
414 * UFS_REG_PA_LINK_STARTUP_TIMER
415 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
416 * Aggregation logic.
417 */
418 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
419 goto out;
420
421 if (gear == 0) {
422 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
423 goto out_error;
424 }
425
426 list_for_each_entry(clki, &hba->clk_list_head, list) {
427 if (!strcmp(clki->name, "core_clk"))
428 core_clk_rate = clk_get_rate(clki->clk);
429 }
430
431 /* If frequency is smaller than 1MHz, set to 1MHz */
432 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
433 core_clk_rate = DEFAULT_CLK_RATE_HZ;
434
435 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
436 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
437 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
438 /*
439 * make sure above write gets applied before we return from
440 * this function.
441 */
442 mb();
443 }
444
445 if (ufs_qcom_cap_qunipro(host))
446 goto out;
447
448 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
449 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
450 core_clk_period_in_ns &= MASK_CLK_NS_REG;
451
452 switch (hs) {
453 case FASTAUTO_MODE:
454 case FAST_MODE:
455 if (rate == PA_HS_MODE_A) {
456 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
457 dev_err(hba->dev,
458 "%s: index %d exceeds table size %zu\n",
459 __func__, gear,
460 ARRAY_SIZE(hs_fr_table_rA));
461 goto out_error;
462 }
463 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
464 } else if (rate == PA_HS_MODE_B) {
465 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
466 dev_err(hba->dev,
467 "%s: index %d exceeds table size %zu\n",
468 __func__, gear,
469 ARRAY_SIZE(hs_fr_table_rB));
470 goto out_error;
471 }
472 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
473 } else {
474 dev_err(hba->dev, "%s: invalid rate = %d\n",
475 __func__, rate);
476 goto out_error;
477 }
478 break;
479 case SLOWAUTO_MODE:
480 case SLOW_MODE:
481 if (gear > ARRAY_SIZE(pwm_fr_table)) {
482 dev_err(hba->dev,
483 "%s: index %d exceeds table size %zu\n",
484 __func__, gear,
485 ARRAY_SIZE(pwm_fr_table));
486 goto out_error;
487 }
488 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
489 break;
490 case UNCHANGED:
491 default:
492 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
493 goto out_error;
494 }
495
496 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
497 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
498 /* this register 2 fields shall be written at once */
499 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
500 REG_UFS_TX_SYMBOL_CLK_NS_US);
501 /*
502 * make sure above write gets applied before we return from
503 * this function.
504 */
505 mb();
506 }
507
508 if (update_link_startup_timer) {
509 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
510 REG_UFS_PA_LINK_STARTUP_TIMER);
511 /*
512 * make sure that this configuration is applied before
513 * we return
514 */
515 mb();
516 }
517 goto out;
518
519 out_error:
520 ret = -EINVAL;
521 out:
522 return ret;
523 }
524
525 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
526 enum ufs_notify_change_status status)
527 {
528 int err = 0;
529 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
530
531 switch (status) {
532 case PRE_CHANGE:
533 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
534 0, true)) {
535 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
536 __func__);
537 err = -EINVAL;
538 goto out;
539 }
540
541 if (ufs_qcom_cap_qunipro(host))
542 /*
543 * set unipro core clock cycles to 150 & clear clock
544 * divider
545 */
546 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
547 150);
548
549 /*
550 * Some UFS devices (and may be host) have issues if LCC is
551 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
552 * before link startup which will make sure that both host
553 * and device TX LCC are disabled once link startup is
554 * completed.
555 */
556 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
557 err = ufshcd_disable_host_tx_lcc(hba);
558
559 break;
560 case POST_CHANGE:
561 ufs_qcom_link_startup_post_change(hba);
562 break;
563 default:
564 break;
565 }
566
567 out:
568 return err;
569 }
570
571 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
572 {
573 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
574 struct phy *phy = host->generic_phy;
575
576 if (ufs_qcom_is_link_off(hba)) {
577 /*
578 * Disable the tx/rx lane symbol clocks before PHY is
579 * powered down as the PLL source should be disabled
580 * after downstream clocks are disabled.
581 */
582 ufs_qcom_disable_lane_clks(host);
583 phy_power_off(phy);
584
585 } else if (!ufs_qcom_is_link_active(hba)) {
586 ufs_qcom_disable_lane_clks(host);
587 }
588
589 return 0;
590 }
591
592 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
593 {
594 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
595 struct phy *phy = host->generic_phy;
596 int err;
597
598 if (ufs_qcom_is_link_off(hba)) {
599 err = phy_power_on(phy);
600 if (err) {
601 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
602 __func__, err);
603 return err;
604 }
605
606 err = ufs_qcom_enable_lane_clks(host);
607 if (err)
608 return err;
609
610 } else if (!ufs_qcom_is_link_active(hba)) {
611 err = ufs_qcom_enable_lane_clks(host);
612 if (err)
613 return err;
614 }
615
616 err = ufs_qcom_ice_resume(host);
617 if (err)
618 return err;
619
620 hba->is_sys_suspended = false;
621 return 0;
622 }
623
624 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
625 {
626 if (host->dev_ref_clk_ctrl_mmio &&
627 (enable ^ host->is_dev_ref_clk_enabled)) {
628 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
629
630 if (enable)
631 temp |= host->dev_ref_clk_en_mask;
632 else
633 temp &= ~host->dev_ref_clk_en_mask;
634
635 /*
636 * If we are here to disable this clock it might be immediately
637 * after entering into hibern8 in which case we need to make
638 * sure that device ref_clk is active for specific time after
639 * hibern8 enter.
640 */
641 if (!enable) {
642 unsigned long gating_wait;
643
644 gating_wait = host->hba->dev_info.clk_gating_wait_us;
645 if (!gating_wait) {
646 udelay(1);
647 } else {
648 /*
649 * bRefClkGatingWaitTime defines the minimum
650 * time for which the reference clock is
651 * required by device during transition from
652 * HS-MODE to LS-MODE or HIBERN8 state. Give it
653 * more delay to be on the safe side.
654 */
655 gating_wait += 10;
656 usleep_range(gating_wait, gating_wait + 10);
657 }
658 }
659
660 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
661
662 /* ensure that ref_clk is enabled/disabled before we return */
663 wmb();
664
665 /*
666 * If we call hibern8 exit after this, we need to make sure that
667 * device ref_clk is stable for at least 1us before the hibern8
668 * exit command.
669 */
670 if (enable)
671 udelay(1);
672
673 host->is_dev_ref_clk_enabled = enable;
674 }
675 }
676
677 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
678 enum ufs_notify_change_status status,
679 struct ufs_pa_layer_attr *dev_max_params,
680 struct ufs_pa_layer_attr *dev_req_params)
681 {
682 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
683 struct ufs_dev_params ufs_qcom_cap;
684 int ret = 0;
685
686 if (!dev_req_params) {
687 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
688 ret = -EINVAL;
689 goto out;
690 }
691
692 switch (status) {
693 case PRE_CHANGE:
694 ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
695 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
696
697 if (host->hw_ver.major == 0x1) {
698 /*
699 * HS-G3 operations may not reliably work on legacy QCOM
700 * UFS host controller hardware even though capability
701 * exchange during link startup phase may end up
702 * negotiating maximum supported gear as G3.
703 * Hence downgrade the maximum supported gear to HS-G2.
704 */
705 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
706 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
707 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
708 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
709 }
710
711 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
712 dev_max_params,
713 dev_req_params);
714 if (ret) {
715 pr_err("%s: failed to determine capabilities\n",
716 __func__);
717 goto out;
718 }
719
720 /* enable the device ref clock before changing to HS mode */
721 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
722 ufshcd_is_hs_mode(dev_req_params))
723 ufs_qcom_dev_ref_clk_ctrl(host, true);
724
725 if (host->hw_ver.major >= 0x4) {
726 ufshcd_dme_configure_adapt(hba,
727 dev_req_params->gear_tx,
728 PA_INITIAL_ADAPT);
729 }
730 break;
731 case POST_CHANGE:
732 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
733 dev_req_params->pwr_rx,
734 dev_req_params->hs_rate, false)) {
735 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
736 __func__);
737 /*
738 * we return error code at the end of the routine,
739 * but continue to configure UFS_PHY_TX_LANE_ENABLE
740 * and bus voting as usual
741 */
742 ret = -EINVAL;
743 }
744
745 /* cache the power mode parameters to use internally */
746 memcpy(&host->dev_req_params,
747 dev_req_params, sizeof(*dev_req_params));
748
749 /* disable the device ref clock if entered PWM mode */
750 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
751 !ufshcd_is_hs_mode(dev_req_params))
752 ufs_qcom_dev_ref_clk_ctrl(host, false);
753 break;
754 default:
755 ret = -EINVAL;
756 break;
757 }
758 out:
759 return ret;
760 }
761
762 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
763 {
764 int err;
765 u32 pa_vs_config_reg1;
766
767 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
768 &pa_vs_config_reg1);
769 if (err)
770 goto out;
771
772 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
773 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
774 (pa_vs_config_reg1 | (1 << 12)));
775
776 out:
777 return err;
778 }
779
780 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
781 {
782 int err = 0;
783
784 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
785 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
786
787 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
788 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
789
790 return err;
791 }
792
793 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
794 {
795 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
796
797 if (host->hw_ver.major == 0x1)
798 return UFSHCI_VERSION_11;
799 else
800 return UFSHCI_VERSION_20;
801 }
802
803 /**
804 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
805 * @hba: host controller instance
806 *
807 * QCOM UFS host controller might have some non standard behaviours (quirks)
808 * than what is specified by UFSHCI specification. Advertise all such
809 * quirks to standard UFS host controller driver so standard takes them into
810 * account.
811 */
812 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
813 {
814 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
815
816 if (host->hw_ver.major == 0x01) {
817 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
818 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
819 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
820
821 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
822 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
823
824 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
825 }
826
827 if (host->hw_ver.major == 0x2) {
828 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
829
830 if (!ufs_qcom_cap_qunipro(host))
831 /* Legacy UniPro mode still need following quirks */
832 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
833 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
834 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
835 }
836 }
837
838 static void ufs_qcom_set_caps(struct ufs_hba *hba)
839 {
840 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
841
842 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
843 hba->caps |= UFSHCD_CAP_CLK_SCALING;
844 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
845 hba->caps |= UFSHCD_CAP_WB_EN;
846 hba->caps |= UFSHCD_CAP_CRYPTO;
847 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
848
849 if (host->hw_ver.major >= 0x2) {
850 host->caps = UFS_QCOM_CAP_QUNIPRO |
851 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
852 }
853 }
854
855 /**
856 * ufs_qcom_setup_clocks - enables/disable clocks
857 * @hba: host controller instance
858 * @on: If true, enable clocks else disable them.
859 * @status: PRE_CHANGE or POST_CHANGE notify
860 *
861 * Returns 0 on success, non-zero on failure.
862 */
863 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
864 enum ufs_notify_change_status status)
865 {
866 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
867 int err = 0;
868
869 /*
870 * In case ufs_qcom_init() is not yet done, simply ignore.
871 * This ufs_qcom_setup_clocks() shall be called from
872 * ufs_qcom_init() after init is done.
873 */
874 if (!host)
875 return 0;
876
877 switch (status) {
878 case PRE_CHANGE:
879 if (!on) {
880 if (!ufs_qcom_is_link_active(hba)) {
881 /* disable device ref_clk */
882 ufs_qcom_dev_ref_clk_ctrl(host, false);
883 }
884 }
885 break;
886 case POST_CHANGE:
887 if (on) {
888 /* enable the device ref clock for HS mode*/
889 if (ufshcd_is_hs_mode(&hba->pwr_info))
890 ufs_qcom_dev_ref_clk_ctrl(host, true);
891 }
892 break;
893 }
894
895 return err;
896 }
897
898 static int
899 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
900 {
901 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
902
903 /* Currently this code only knows about a single reset. */
904 WARN_ON(id);
905 ufs_qcom_assert_reset(host->hba);
906 /* provide 1ms delay to let the reset pulse propagate. */
907 usleep_range(1000, 1100);
908 return 0;
909 }
910
911 static int
912 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
913 {
914 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
915
916 /* Currently this code only knows about a single reset. */
917 WARN_ON(id);
918 ufs_qcom_deassert_reset(host->hba);
919
920 /*
921 * after reset deassertion, phy will need all ref clocks,
922 * voltage, current to settle down before starting serdes.
923 */
924 usleep_range(1000, 1100);
925 return 0;
926 }
927
928 static const struct reset_control_ops ufs_qcom_reset_ops = {
929 .assert = ufs_qcom_reset_assert,
930 .deassert = ufs_qcom_reset_deassert,
931 };
932
933 #define ANDROID_BOOT_DEV_MAX 30
934 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
935
936 #ifndef MODULE
937 static int __init get_android_boot_dev(char *str)
938 {
939 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
940 return 1;
941 }
942 __setup("androidboot.bootdevice=", get_android_boot_dev);
943 #endif
944
945 /**
946 * ufs_qcom_init - bind phy with controller
947 * @hba: host controller instance
948 *
949 * Binds PHY with controller and powers up PHY enabling clocks
950 * and regulators.
951 *
952 * Returns -EPROBE_DEFER if binding fails, returns negative error
953 * on phy power up failure and returns zero on success.
954 */
955 static int ufs_qcom_init(struct ufs_hba *hba)
956 {
957 int err;
958 struct device *dev = hba->dev;
959 struct platform_device *pdev = to_platform_device(dev);
960 struct ufs_qcom_host *host;
961 struct resource *res;
962 struct ufs_clk_info *clki;
963
964 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
965 return -ENODEV;
966
967 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
968 if (!host) {
969 err = -ENOMEM;
970 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
971 goto out;
972 }
973
974 /* Make a two way bind between the qcom host and the hba */
975 host->hba = hba;
976 ufshcd_set_variant(hba, host);
977
978 /* Setup the reset control of HCI */
979 host->core_reset = devm_reset_control_get(hba->dev, "rst");
980 if (IS_ERR(host->core_reset)) {
981 err = PTR_ERR(host->core_reset);
982 dev_warn(dev, "Failed to get reset control %d\n", err);
983 host->core_reset = NULL;
984 err = 0;
985 }
986
987 /* Fire up the reset controller. Failure here is non-fatal. */
988 host->rcdev.of_node = dev->of_node;
989 host->rcdev.ops = &ufs_qcom_reset_ops;
990 host->rcdev.owner = dev->driver->owner;
991 host->rcdev.nr_resets = 1;
992 err = devm_reset_controller_register(dev, &host->rcdev);
993 if (err) {
994 dev_warn(dev, "Failed to register reset controller\n");
995 err = 0;
996 }
997
998 /*
999 * voting/devoting device ref_clk source is time consuming hence
1000 * skip devoting it during aggressive clock gating. This clock
1001 * will still be gated off during runtime suspend.
1002 */
1003 host->generic_phy = devm_phy_get(dev, "ufsphy");
1004
1005 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1006 /*
1007 * UFS driver might be probed before the phy driver does.
1008 * In that case we would like to return EPROBE_DEFER code.
1009 */
1010 err = -EPROBE_DEFER;
1011 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1012 __func__, err);
1013 goto out_variant_clear;
1014 } else if (IS_ERR(host->generic_phy)) {
1015 if (has_acpi_companion(dev)) {
1016 host->generic_phy = NULL;
1017 } else {
1018 err = PTR_ERR(host->generic_phy);
1019 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1020 goto out_variant_clear;
1021 }
1022 }
1023
1024 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1025 GPIOD_OUT_HIGH);
1026 if (IS_ERR(host->device_reset)) {
1027 err = PTR_ERR(host->device_reset);
1028 if (err != -EPROBE_DEFER)
1029 dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1030 goto out_variant_clear;
1031 }
1032
1033 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1034 &host->hw_ver.minor, &host->hw_ver.step);
1035
1036 /*
1037 * for newer controllers, device reference clock control bit has
1038 * moved inside UFS controller register address space itself.
1039 */
1040 if (host->hw_ver.major >= 0x02) {
1041 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1042 host->dev_ref_clk_en_mask = BIT(26);
1043 } else {
1044 /* "dev_ref_clk_ctrl_mem" is optional resource */
1045 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1046 "dev_ref_clk_ctrl_mem");
1047 if (res) {
1048 host->dev_ref_clk_ctrl_mmio =
1049 devm_ioremap_resource(dev, res);
1050 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1051 dev_warn(dev,
1052 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1053 __func__,
1054 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1055 host->dev_ref_clk_ctrl_mmio = NULL;
1056 }
1057 host->dev_ref_clk_en_mask = BIT(5);
1058 }
1059 }
1060
1061 list_for_each_entry(clki, &hba->clk_list_head, list) {
1062 if (!strcmp(clki->name, "core_clk_unipro"))
1063 clki->keep_link_active = true;
1064 }
1065
1066 err = ufs_qcom_init_lane_clks(host);
1067 if (err)
1068 goto out_variant_clear;
1069
1070 ufs_qcom_set_caps(hba);
1071 ufs_qcom_advertise_quirks(hba);
1072
1073 err = ufs_qcom_ice_init(host);
1074 if (err)
1075 goto out_variant_clear;
1076
1077 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1078
1079 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1080 ufs_qcom_hosts[hba->dev->id] = host;
1081
1082 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1083 ufs_qcom_get_default_testbus_cfg(host);
1084 err = ufs_qcom_testbus_config(host);
1085 if (err) {
1086 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1087 __func__, err);
1088 err = 0;
1089 }
1090
1091 goto out;
1092
1093 out_variant_clear:
1094 ufshcd_set_variant(hba, NULL);
1095 out:
1096 return err;
1097 }
1098
1099 static void ufs_qcom_exit(struct ufs_hba *hba)
1100 {
1101 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1102
1103 ufs_qcom_disable_lane_clks(host);
1104 phy_power_off(host->generic_phy);
1105 phy_exit(host->generic_phy);
1106 }
1107
1108 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1109 u32 clk_cycles)
1110 {
1111 int err;
1112 u32 core_clk_ctrl_reg;
1113
1114 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1115 return -EINVAL;
1116
1117 err = ufshcd_dme_get(hba,
1118 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1119 &core_clk_ctrl_reg);
1120 if (err)
1121 goto out;
1122
1123 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1124 core_clk_ctrl_reg |= clk_cycles;
1125
1126 /* Clear CORE_CLK_DIV_EN */
1127 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1128
1129 err = ufshcd_dme_set(hba,
1130 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1131 core_clk_ctrl_reg);
1132 out:
1133 return err;
1134 }
1135
1136 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1137 {
1138 /* nothing to do as of now */
1139 return 0;
1140 }
1141
1142 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1143 {
1144 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1145
1146 if (!ufs_qcom_cap_qunipro(host))
1147 return 0;
1148
1149 /* set unipro core clock cycles to 150 and clear clock divider */
1150 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1151 }
1152
1153 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1154 {
1155 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1156 int err;
1157 u32 core_clk_ctrl_reg;
1158
1159 if (!ufs_qcom_cap_qunipro(host))
1160 return 0;
1161
1162 err = ufshcd_dme_get(hba,
1163 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1164 &core_clk_ctrl_reg);
1165
1166 /* make sure CORE_CLK_DIV_EN is cleared */
1167 if (!err &&
1168 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1169 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1170 err = ufshcd_dme_set(hba,
1171 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1172 core_clk_ctrl_reg);
1173 }
1174
1175 return err;
1176 }
1177
1178 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1179 {
1180 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1181
1182 if (!ufs_qcom_cap_qunipro(host))
1183 return 0;
1184
1185 /* set unipro core clock cycles to 75 and clear clock divider */
1186 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1187 }
1188
1189 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1190 bool scale_up, enum ufs_notify_change_status status)
1191 {
1192 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1193 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1194 int err = 0;
1195
1196 if (status == PRE_CHANGE) {
1197 if (scale_up)
1198 err = ufs_qcom_clk_scale_up_pre_change(hba);
1199 else
1200 err = ufs_qcom_clk_scale_down_pre_change(hba);
1201 } else {
1202 if (scale_up)
1203 err = ufs_qcom_clk_scale_up_post_change(hba);
1204 else
1205 err = ufs_qcom_clk_scale_down_post_change(hba);
1206
1207 if (err || !dev_req_params)
1208 goto out;
1209
1210 ufs_qcom_cfg_timers(hba,
1211 dev_req_params->gear_rx,
1212 dev_req_params->pwr_rx,
1213 dev_req_params->hs_rate,
1214 false);
1215 }
1216
1217 out:
1218 return err;
1219 }
1220
1221 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1222 void *priv, void (*print_fn)(struct ufs_hba *hba,
1223 int offset, int num_regs, const char *str, void *priv))
1224 {
1225 u32 reg;
1226 struct ufs_qcom_host *host;
1227
1228 if (unlikely(!hba)) {
1229 pr_err("%s: hba is NULL\n", __func__);
1230 return;
1231 }
1232 if (unlikely(!print_fn)) {
1233 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1234 return;
1235 }
1236
1237 host = ufshcd_get_variant(hba);
1238 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1239 return;
1240
1241 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1242 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1243
1244 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1245 reg |= UTP_DBG_RAMS_EN;
1246 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1247
1248 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1249 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1250
1251 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1252 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1253
1254 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1255 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1256
1257 /* clear bit 17 - UTP_DBG_RAMS_EN */
1258 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1259
1260 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1261 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1262
1263 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1264 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1265
1266 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1267 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1268
1269 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1270 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1271
1272 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1273 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1274
1275 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1276 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1277
1278 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1279 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1280 }
1281
1282 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1283 {
1284 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1285 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1286 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1287 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1288 } else {
1289 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1290 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1291 }
1292 }
1293
1294 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1295 {
1296 /* provide a legal default configuration */
1297 host->testbus.select_major = TSTBUS_UNIPRO;
1298 host->testbus.select_minor = 37;
1299 }
1300
1301 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1302 {
1303 if (host->testbus.select_major >= TSTBUS_MAX) {
1304 dev_err(host->hba->dev,
1305 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1306 __func__, host->testbus.select_major);
1307 return false;
1308 }
1309
1310 return true;
1311 }
1312
1313 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1314 {
1315 int reg;
1316 int offset;
1317 u32 mask = TEST_BUS_SUB_SEL_MASK;
1318
1319 if (!host)
1320 return -EINVAL;
1321
1322 if (!ufs_qcom_testbus_cfg_is_ok(host))
1323 return -EPERM;
1324
1325 switch (host->testbus.select_major) {
1326 case TSTBUS_UAWM:
1327 reg = UFS_TEST_BUS_CTRL_0;
1328 offset = 24;
1329 break;
1330 case TSTBUS_UARM:
1331 reg = UFS_TEST_BUS_CTRL_0;
1332 offset = 16;
1333 break;
1334 case TSTBUS_TXUC:
1335 reg = UFS_TEST_BUS_CTRL_0;
1336 offset = 8;
1337 break;
1338 case TSTBUS_RXUC:
1339 reg = UFS_TEST_BUS_CTRL_0;
1340 offset = 0;
1341 break;
1342 case TSTBUS_DFC:
1343 reg = UFS_TEST_BUS_CTRL_1;
1344 offset = 24;
1345 break;
1346 case TSTBUS_TRLUT:
1347 reg = UFS_TEST_BUS_CTRL_1;
1348 offset = 16;
1349 break;
1350 case TSTBUS_TMRLUT:
1351 reg = UFS_TEST_BUS_CTRL_1;
1352 offset = 8;
1353 break;
1354 case TSTBUS_OCSC:
1355 reg = UFS_TEST_BUS_CTRL_1;
1356 offset = 0;
1357 break;
1358 case TSTBUS_WRAPPER:
1359 reg = UFS_TEST_BUS_CTRL_2;
1360 offset = 16;
1361 break;
1362 case TSTBUS_COMBINED:
1363 reg = UFS_TEST_BUS_CTRL_2;
1364 offset = 8;
1365 break;
1366 case TSTBUS_UTP_HCI:
1367 reg = UFS_TEST_BUS_CTRL_2;
1368 offset = 0;
1369 break;
1370 case TSTBUS_UNIPRO:
1371 reg = UFS_UNIPRO_CFG;
1372 offset = 20;
1373 mask = 0xFFF;
1374 break;
1375 /*
1376 * No need for a default case, since
1377 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1378 * is legal
1379 */
1380 }
1381 mask <<= offset;
1382 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1383 (u32)host->testbus.select_major << 19,
1384 REG_UFS_CFG1);
1385 ufshcd_rmwl(host->hba, mask,
1386 (u32)host->testbus.select_minor << offset,
1387 reg);
1388 ufs_qcom_enable_test_bus(host);
1389 /*
1390 * Make sure the test bus configuration is
1391 * committed before returning.
1392 */
1393 mb();
1394
1395 return 0;
1396 }
1397
1398 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1399 {
1400 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1401 "HCI Vendor Specific Registers ");
1402
1403 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1404 }
1405
1406 /**
1407 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1408 * @hba: per-adapter instance
1409 *
1410 * Toggles the (optional) reset line to reset the attached device.
1411 */
1412 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1413 {
1414 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1415
1416 /* reset gpio is optional */
1417 if (!host->device_reset)
1418 return -EOPNOTSUPP;
1419
1420 /*
1421 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1422 * be on the safe side.
1423 */
1424 gpiod_set_value_cansleep(host->device_reset, 1);
1425 usleep_range(10, 15);
1426
1427 gpiod_set_value_cansleep(host->device_reset, 0);
1428 usleep_range(10, 15);
1429
1430 return 0;
1431 }
1432
1433 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1434 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1435 struct devfreq_dev_profile *p,
1436 void *data)
1437 {
1438 static struct devfreq_simple_ondemand_data *d;
1439
1440 if (!data)
1441 return;
1442
1443 d = (struct devfreq_simple_ondemand_data *)data;
1444 p->polling_ms = 60;
1445 d->upthreshold = 70;
1446 d->downdifferential = 5;
1447 }
1448 #else
1449 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1450 struct devfreq_dev_profile *p,
1451 void *data)
1452 {
1453 }
1454 #endif
1455
1456 /*
1457 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1458 *
1459 * The variant operations configure the necessary controller and PHY
1460 * handshake during initialization.
1461 */
1462 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1463 .name = "qcom",
1464 .init = ufs_qcom_init,
1465 .exit = ufs_qcom_exit,
1466 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1467 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1468 .setup_clocks = ufs_qcom_setup_clocks,
1469 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1470 .link_startup_notify = ufs_qcom_link_startup_notify,
1471 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1472 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1473 .suspend = ufs_qcom_suspend,
1474 .resume = ufs_qcom_resume,
1475 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1476 .device_reset = ufs_qcom_device_reset,
1477 .config_scaling_param = ufs_qcom_config_scaling_param,
1478 .program_key = ufs_qcom_ice_program_key,
1479 };
1480
1481 /**
1482 * ufs_qcom_probe - probe routine of the driver
1483 * @pdev: pointer to Platform device handle
1484 *
1485 * Return zero for success and non-zero for failure
1486 */
1487 static int ufs_qcom_probe(struct platform_device *pdev)
1488 {
1489 int err;
1490 struct device *dev = &pdev->dev;
1491
1492 /* Perform generic probe */
1493 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1494 if (err)
1495 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1496
1497 return err;
1498 }
1499
1500 /**
1501 * ufs_qcom_remove - set driver_data of the device to NULL
1502 * @pdev: pointer to platform device handle
1503 *
1504 * Always returns 0
1505 */
1506 static int ufs_qcom_remove(struct platform_device *pdev)
1507 {
1508 struct ufs_hba *hba = platform_get_drvdata(pdev);
1509
1510 pm_runtime_get_sync(&(pdev)->dev);
1511 ufshcd_remove(hba);
1512 return 0;
1513 }
1514
1515 static const struct of_device_id ufs_qcom_of_match[] = {
1516 { .compatible = "qcom,ufshc"},
1517 {},
1518 };
1519 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1520
1521 #ifdef CONFIG_ACPI
1522 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1523 { "QCOM24A5" },
1524 { },
1525 };
1526 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1527 #endif
1528
1529 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1530 .suspend = ufshcd_pltfrm_suspend,
1531 .resume = ufshcd_pltfrm_resume,
1532 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1533 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1534 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1535 };
1536
1537 static struct platform_driver ufs_qcom_pltform = {
1538 .probe = ufs_qcom_probe,
1539 .remove = ufs_qcom_remove,
1540 .shutdown = ufshcd_pltfrm_shutdown,
1541 .driver = {
1542 .name = "ufshcd-qcom",
1543 .pm = &ufs_qcom_pm_ops,
1544 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1545 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1546 },
1547 };
1548 module_platform_driver(ufs_qcom_pltform);
1549
1550 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support