drivers/staging/mt7621-dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/gpio/gpio.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mediatek,mt7621-soc";
   8
   9         cpus {
  10                 cpu@0 {
  11                         compatible = "mips,mips1004Kc";
  12                 };
  13
  14                 cpu@1 {
  15                         compatible = "mips,mips1004Kc";
  16                 };
  17         };
  18
  19         cpuintc: cpuintc@0 {
  20                 #address-cells = <0>;
  21                 #interrupt-cells = <1>;
  22                 interrupt-controller;
  23                 compatible = "mti,cpu-interrupt-controller";
  24         };
  25
  26         aliases {
  27                 serial0 = &uartlite;
  28         };
  29
  30         cpuclock: cpuclock@0 {
  31                 #clock-cells = <0>;
  32                 compatible = "fixed-clock";
  33
  34                 /* FIXME: there should be way to detect this */
  35                 clock-frequency = <880000000>;
  36         };
  37
  38         sysclock: sysclock@0 {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41
  42                 /* This is normally 1/4 of cpuclock */
  43                 clock-frequency = <220000000>;
  44         };
  45
  46         mmc_clock: mmc_clock@0 {
  47                 #clock-cells = <0>;
  48                 compatible = "fixed-clock";
  49                 clock-frequency = <48000000>;
  50         };
  51
  52         mmc_fixed_3v3: fixedregulator@0 {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "mmc_power";
  55                 regulator-min-microvolt = <3300000>;
  56                 regulator-max-microvolt = <3300000>;
  57                 enable-active-high;
  58                 regulator-always-on;
  59           };
  60
  61           mmc_fixed_1v8_io: fixedregulator@1 {
  62                 compatible = "regulator-fixed";
  63                 regulator-name = "mmc_io";
  64                 regulator-min-microvolt = <1800000>;
  65                 regulator-max-microvolt = <1800000>;
  66                 enable-active-high;
  67                 regulator-always-on;
  68         };
  69
  70         palmbus: palmbus@1E000000 {
  71                 compatible = "palmbus";
  72                 reg = <0x1E000000 0x100000>;
  73                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  74
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77
  78                 sysc: sysc@0 {
  79                         compatible = "mtk,mt7621-sysc";
  80                         reg = <0x0 0x100>;
  81                 };
  82
  83                 wdt: wdt@100 {
  84                         compatible = "mtk,mt7621-wdt";
  85                         reg = <0x100 0x100>;
  86                 };
  87
  88                 gpio: gpio@600 {
  89                         #gpio-cells = <2>;
  90                         #interrupt-cells = <2>;
  91                         compatible = "mediatek,mt7621-gpio";
  92                         gpio-controller;
  93                         gpio-ranges = <&pinctrl 0 0 95>;
  94                         interrupt-controller;
  95                         reg = <0x600 0x100>;
  96                         interrupt-parent = <&gic>;
  97                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  98                 };
  99
 100                 i2c: i2c@900 {
 101                         compatible = "mediatek,mt7621-i2c";
 102                         reg = <0x900 0x100>;
 103
 104                         clocks = <&sysclock>;
 105
 106                         resets = <&rstctrl 16>;
 107                         reset-names = "i2c";
 108
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111
 112                         status = "disabled";
 113
 114                         pinctrl-names = "default";
 115                         pinctrl-0 = <&i2c_pins>;
 116                 };
 117
 118                 i2s: i2s@a00 {
 119                         compatible = "mediatek,mt7621-i2s";
 120                         reg = <0xa00 0x100>;
 121
 122                         clocks = <&sysclock>;
 123
 124                         resets = <&rstctrl 17>;
 125                         reset-names = "i2s";
 126
 127                         interrupt-parent = <&gic>;
 128                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 129
 130                         txdma-req = <2>;
 131                         rxdma-req = <3>;
 132
 133                         dmas = <&gdma 4>,
 134                                 <&gdma 6>;
 135                         dma-names = "tx", "rx";
 136
 137                         status = "disabled";
 138                 };
 139
 140                 memc: memc@5000 {
 141                         compatible = "mtk,mt7621-memc";
 142                         reg = <0x5000 0x1000>;
 143                 };
 144
 145                 cpc: cpc@1fbf0000 {
 146                              compatible = "mtk,mt7621-cpc";
 147                              reg = <0x1fbf0000 0x8000>;
 148                 };
 149
 150                 mc: mc@1fbf8000 {
 151                             compatible = "mtk,mt7621-mc";
 152                             reg = <0x1fbf8000 0x8000>;
 153                 };
 154
 155                 uartlite: uartlite@c00 {
 156                         compatible = "ns16550a";
 157                         reg = <0xc00 0x100>;
 158
 159                         clocks = <&sysclock>;
 160                         clock-frequency = <50000000>;
 161
 162                         interrupt-parent = <&gic>;
 163                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 164
 165                         reg-shift = <2>;
 166                         reg-io-width = <4>;
 167                         no-loopback-test;
 168                 };
 169
 170                 spi0: spi@b00 {
 171                         status = "disabled";
 172
 173                         compatible = "ralink,mt7621-spi";
 174                         reg = <0xb00 0x100>;
 175
 176                         clocks = <&sysclock>;
 177
 178                         resets = <&rstctrl 18>;
 179                         reset-names = "spi";
 180
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183
 184                         pinctrl-names = "default";
 185                         pinctrl-0 = <&spi_pins>;
 186                 };
 187
 188                 gdma: gdma@2800 {
 189                         compatible = "ralink,rt3883-gdma";
 190                         reg = <0x2800 0x800>;
 191
 192                         resets = <&rstctrl 14>;
 193                         reset-names = "dma";
 194
 195                         interrupt-parent = <&gic>;
 196                         interrupts = <0 13 4>;
 197
 198                         #dma-cells = <1>;
 199                         #dma-channels = <16>;
 200                         #dma-requests = <16>;
 201
 202                         status = "disabled";
 203                 };
 204
 205                 hsdma: hsdma@7000 {
 206                         compatible = "mediatek,mt7621-hsdma";
 207                         reg = <0x7000 0x1000>;
 208
 209                         resets = <&rstctrl 5>;
 210                         reset-names = "hsdma";
 211
 212                         interrupt-parent = <&gic>;
 213                         interrupts = <0 11 4>;
 214
 215                         #dma-cells = <1>;
 216                         #dma-channels = <1>;
 217                         #dma-requests = <1>;
 218
 219                         status = "disabled";
 220                 };
 221         };
 222
 223         pinctrl: pinctrl {
 224                 compatible = "ralink,rt2880-pinmux";
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&state_default>;
 227
 228                 state_default: pinctrl0 {
 229                 };
 230
 231                 i2c_pins: i2c0 {
 232                         i2c0 {
 233                                 groups = "i2c";
 234                                 function = "i2c";
 235                         };
 236                 };
 237
 238                 spi_pins: spi0 {
 239                         spi0 {
 240                                 groups = "spi";
 241                                 function = "spi";
 242                         };
 243                 };
 244
 245                 uart1_pins: uart1 {
 246                         uart1 {
 247                                 groups = "uart1";
 248                                 function = "uart1";
 249                         };
 250                 };
 251
 252                 uart2_pins: uart2 {
 253                         uart2 {
 254                                 groups = "uart2";
 255                                 function = "uart2";
 256                         };
 257                 };
 258
 259                 uart3_pins: uart3 {
 260                         uart3 {
 261                                 groups = "uart3";
 262                                 function = "uart3";
 263                         };
 264                 };
 265
 266                 rgmii1_pins: rgmii1 {
 267                         rgmii1 {
 268                                 groups = "rgmii1";
 269                                 function = "rgmii1";
 270                         };
 271                 };
 272
 273                 rgmii2_pins: rgmii2 {
 274                         rgmii2 {
 275                                 groups = "rgmii2";
 276                                 function = "rgmii2";
 277                         };
 278                 };
 279
 280                 mdio_pins: mdio0 {
 281                         mdio0 {
 282                                 groups = "mdio";
 283                                 function = "mdio";
 284                         };
 285                 };
 286
 287                 pcie_pins: pcie0 {
 288                         pcie0 {
 289                                 groups = "pcie";
 290                                 function = "gpio";
 291                         };
 292                 };
 293
 294                 nand_pins: nand0 {
 295                         spi-nand {
 296                                 groups = "spi";
 297                                 function = "nand1";
 298                         };
 299
 300                         sdhci-nand {
 301                                 groups = "sdhci";
 302                                 function = "nand2";
 303                         };
 304                 };
 305
 306                 sdhci_pins: sdhci0 {
 307                         sdhci0 {
 308                                 groups = "sdhci";
 309                                 function = "sdhci";
 310                         };
 311                 };
 312         };
 313
 314         rstctrl: rstctrl {
 315                 compatible = "ralink,rt2880-reset";
 316                 #reset-cells = <1>;
 317         };
 318
 319         clkctrl: clkctrl {
 320                 compatible = "ralink,rt2880-clock";
 321                 #clock-cells = <1>;
 322         };
 323
 324         sdhci: sdhci@1E130000 {
 325                 status = "disabled";
 326
 327                 compatible = "mediatek,mt7620-mmc";
 328                 reg = <0x1E130000 0x4000>;
 329
 330                 bus-width = <4>;
 331                 max-frequency = <48000000>;
 332                 cap-sd-highspeed;
 333                 cap-mmc-highspeed;
 334                 vmmc-supply = <&mmc_fixed_3v3>;
 335                 vqmmc-supply = <&mmc_fixed_1v8_io>;
 336                 disable-wp;
 337
 338                 pinctrl-names = "default", "state_uhs";
 339                 pinctrl-0 = <&sdhci_pins>;
 340                 pinctrl-1 = <&sdhci_pins>;
 341
 342                 clocks = <&mmc_clock &mmc_clock>;
 343                 clock-names = "source", "hclk";
 344
 345                 interrupt-parent = <&gic>;
 346                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 347         };
 348
 349         xhci: xhci@1E1C0000 {
 350                 status = "okay";
 351
 352                 compatible = "mediatek,mt8173-xhci";
 353                 reg = <0x1e1c0000 0x1000
 354                        0x1e1d0700 0x0100>;
 355                 reg-names = "mac", "ippc";
 356
 357                 clocks = <&sysclock>;
 358                 clock-names = "sys_ck";
 359
 360                 interrupt-parent = <&gic>;
 361                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 362         };
 363
 364         gic: interrupt-controller@1fbc0000 {
 365                 compatible = "mti,gic";
 366                 reg = <0x1fbc0000 0x2000>;
 367
 368                 interrupt-controller;
 369                 #interrupt-cells = <3>;
 370
 371                 mti,reserved-cpu-vectors = <7>;
 372
 373                 timer {
 374                         compatible = "mti,gic-timer";
 375                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 376                         clocks = <&cpuclock>;
 377                 };
 378         };
 379
 380         nand: nand@1e003000 {
 381                 status = "disabled";
 382
 383                 compatible = "mtk,mt7621-nand";
 384                 bank-width = <2>;
 385                 reg = <0x1e003000 0x800
 386                         0x1e003800 0x800>;
 387                 #address-cells = <1>;
 388                 #size-cells = <1>;
 389         };
 390
 391         ethsys: syscon@1e000000 {
 392                 compatible = "mediatek,mt7621-ethsys",
 393                              "syscon";
 394                 reg = <0x1e000000 0x1000>;
 395                 #clock-cells = <1>;
 396         };
 397
 398         ethernet: ethernet@1e100000 {
 399                 compatible = "mediatek,mt7621-eth";
 400                 reg = <0x1e100000 0x10000>;
 401
 402                 clocks = <&sysclock>;
 403                 clock-names = "ethif";
 404
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407
 408                 resets = <&rstctrl 6 &rstctrl 23>;
 409                 reset-names = "fe", "eth";
 410
 411                 interrupt-parent = <&gic>;
 412                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 413
 414                 mediatek,ethsys = <&ethsys>;
 415
 416
 417                 gmac0: mac@0 {
 418                         compatible = "mediatek,eth-mac";
 419                         reg = <0>;
 420                         phy-mode = "rgmii";
 421                         fixed-link {
 422                                 speed = <1000>;
 423                                 full-duplex;
 424                                 pause;
 425                         };
 426                 };
 427                 gmac1: mac@1 {
 428                         compatible = "mediatek,eth-mac";
 429                         reg = <1>;
 430                         status = "off";
 431                         phy-mode = "rgmii-rxid";
 432                         phy-handle = <&phy_external>;
 433                 };
 434                 mdio-bus {
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437
 438                         phy_external: ethernet-phy@5 {
 439                                 status = "off";
 440                                 reg = <5>;
 441                                 phy-mode = "rgmii-rxid";
 442
 443                                 pinctrl-names = "default";
 444                                 pinctrl-0 = <&rgmii2_pins>;
 445                         };
 446
 447                         switch0: switch0@0 {
 448                                 compatible = "mediatek,mt7621";
 449                                 #address-cells = <1>;
 450                                 #size-cells = <0>;
 451                                 reg = <0>;
 452                                 mediatek,mcm;
 453                                 resets = <&rstctrl 2>;
 454                                 reset-names = "mcm";
 455
 456                                 ports {
 457                                         #address-cells = <1>;
 458                                         #size-cells = <0>;
 459                                         reg = <0>;
 460                                         port@0 {
 461                                                 status = "off";
 462                                                 reg = <0>;
 463                                                 label = "lan0";
 464                                         };
 465                                         port@1 {
 466                                                 status = "off";
 467                                                 reg = <1>;
 468                                                 label = "lan1";
 469                                         };
 470                                         port@2 {
 471                                                 status = "off";
 472                                                 reg = <2>;
 473                                                 label = "lan2";
 474                                         };
 475                                         port@3 {
 476                                                 status = "off";
 477                                                 reg = <3>;
 478                                                 label = "lan3";
 479                                         };
 480                                         port@4 {
 481                                                 status = "off";
 482                                                 reg = <4>;
 483                                                 label = "lan4";
 484                                         };
 485                                         port@6 {
 486                                                 reg = <6>;
 487                                                 label = "cpu";
 488                                                 ethernet = <&gmac0>;
 489                                                 phy-mode = "trgmii";
 490                                                 fixed-link {
 491                                                         speed = <1000>;
 492                                                         full-duplex;
 493                                                 };
 494                                         };
 495                                 };
 496                         };
 497                 };
 498         };
 499
 500         gsw: gsw@1e110000 {
 501                 compatible = "mediatek,mt7621-gsw";
 502                 reg = <0x1e110000 0x8000>;
 503                 interrupt-parent = <&gic>;
 504                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 505         };
 506
 507         pcie: pcie@1e140000 {
 508                 compatible = "mediatek,mt7621-pci";
 509                 reg = <0x1e140000 0x100     /* host-pci bridge registers */
 510                         0x1e142000 0x100    /* pcie port 0 RC control registers */
 511                         0x1e143000 0x100    /* pcie port 1 RC control registers */
 512                         0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 513                 #address-cells = <3>;
 514                 #size-cells = <2>;
 515
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&pcie_pins>;
 518
 519                 device_type = "pci";
 520
 521                 bus-range = <0 255>;
 522                 ranges = <
 523                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 524                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 525                 >;
 526
 527                 interrupt-parent = <&gic>;
 528                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 529                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 530                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 531
 532                 status = "disabled";
 533
 534                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 535                 reset-names = "pcie0", "pcie1", "pcie2";
 536                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 537                 clock-names = "pcie0", "pcie1", "pcie2";
 538                 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 539                 phy-names = "pcie-phy0", "pcie-phy2";
 540
 541                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 542
 543                 pcie@0,0 {
 544                         reg = <0x0000 0 0 0 0>;
 545                         #address-cells = <3>;
 546                         #size-cells = <2>;
 547                         ranges;
 548                         bus-range = <0x00 0xff>;
 549                 };
 550
 551                 pcie@1,0 {
 552                         reg = <0x0800 0 0 0 0>;
 553                         #address-cells = <3>;
 554                         #size-cells = <2>;
 555                         ranges;
 556                         bus-range = <0x00 0xff>;
 557                 };
 558
 559                 pcie@2,0 {
 560                         reg = <0x1000 0 0 0 0>;
 561                         #address-cells = <3>;
 562                         #size-cells = <2>;
 563                         ranges;
 564                         bus-range = <0x00 0xff>;
 565                 };
 566         };
 567
 568         pcie0_phy: pcie-phy@1e149000 {
 569                 compatible = "mediatek,mt7621-pci-phy";
 570                 reg = <0x1e149000 0x0700>;
 571                 #phy-cells = <1>;
 572         };
 573
 574         pcie2_phy: pcie-phy@1e14a000 {
 575                 compatible = "mediatek,mt7621-pci-phy";
 576                 reg = <0x1e14a000 0x0700>;
 577                 #phy-cells = <1>;
 578         };
 579 };