1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Linaro Limited
7 #include <linux/bitops.h>
8 #include <linux/regmap.h>
11 /* ----- SROT ------ */
12 #define SROT_HW_VER_OFF 0x0000
13 #define SROT_CTRL_OFF 0x0004
16 #define TM_INT_EN_OFF 0x0004
17 #define TM_UPPER_LOWER_INT_STATUS_OFF 0x0008
18 #define TM_UPPER_LOWER_INT_CLEAR_OFF 0x000c
19 #define TM_UPPER_LOWER_INT_MASK_OFF 0x0010
20 #define TM_CRITICAL_INT_STATUS_OFF 0x0014
21 #define TM_CRITICAL_INT_CLEAR_OFF 0x0018
22 #define TM_CRITICAL_INT_MASK_OFF 0x001c
23 #define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
24 #define TM_Sn_CRITICAL_THRESHOLD_OFF 0x0060
25 #define TM_Sn_STATUS_OFF 0x00a0
26 #define TM_TRDY_OFF 0x00e4
27 #define TM_WDOG_LOG_OFF 0x013c
29 /* v2.x: 8996, 8998, sdm845 */
31 static struct tsens_features tsens_v2_feat
= {
39 static const struct reg_field tsens_v2_regfields
[MAX_REGFIELDS
] = {
40 /* ----- SROT ------ */
42 [VER_MAJOR
] = REG_FIELD(SROT_HW_VER_OFF
, 28, 31),
43 [VER_MINOR
] = REG_FIELD(SROT_HW_VER_OFF
, 16, 27),
44 [VER_STEP
] = REG_FIELD(SROT_HW_VER_OFF
, 0, 15),
46 [TSENS_EN
] = REG_FIELD(SROT_CTRL_OFF
, 0, 0),
47 [TSENS_SW_RST
] = REG_FIELD(SROT_CTRL_OFF
, 1, 1),
50 /* INTERRUPT ENABLE */
51 /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */
52 [INT_EN
] = REG_FIELD(TM_INT_EN_OFF
, 0, 2),
54 /* TEMPERATURE THRESHOLDS */
55 REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH
, TM_Sn_UPPER_LOWER_THRESHOLD_OFF
, 0, 11),
56 REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH
, TM_Sn_UPPER_LOWER_THRESHOLD_OFF
, 12, 23),
57 REG_FIELD_FOR_EACH_SENSOR16(CRIT_THRESH
, TM_Sn_CRITICAL_THRESHOLD_OFF
, 0, 11),
59 /* INTERRUPTS [CLEAR/STATUS/MASK] */
60 REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS
, TM_UPPER_LOWER_INT_STATUS_OFF
),
61 REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR
, TM_UPPER_LOWER_INT_CLEAR_OFF
),
62 REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK
, TM_UPPER_LOWER_INT_MASK_OFF
),
63 REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS
, TM_UPPER_LOWER_INT_STATUS_OFF
),
64 REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR
, TM_UPPER_LOWER_INT_CLEAR_OFF
),
65 REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK
, TM_UPPER_LOWER_INT_MASK_OFF
),
66 REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_STATUS
, TM_CRITICAL_INT_STATUS_OFF
),
67 REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_CLEAR
, TM_CRITICAL_INT_CLEAR_OFF
),
68 REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_MASK
, TM_CRITICAL_INT_MASK_OFF
),
70 /* WATCHDOG on v2.3 or later */
71 [WDOG_BARK_STATUS
] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF
, 31, 31),
72 [WDOG_BARK_CLEAR
] = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF
, 31, 31),
73 [WDOG_BARK_MASK
] = REG_FIELD(TM_CRITICAL_INT_MASK_OFF
, 31, 31),
74 [CC_MON_STATUS
] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF
, 30, 30),
75 [CC_MON_CLEAR
] = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF
, 30, 30),
76 [CC_MON_MASK
] = REG_FIELD(TM_CRITICAL_INT_MASK_OFF
, 30, 30),
77 [WDOG_BARK_COUNT
] = REG_FIELD(TM_WDOG_LOG_OFF
, 0, 7),
80 REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP
, TM_Sn_STATUS_OFF
, 0, 11),
81 REG_FIELD_FOR_EACH_SENSOR16(VALID
, TM_Sn_STATUS_OFF
, 21, 21),
82 /* xxx_STATUS bits: 1 == threshold violated */
83 REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS
, TM_Sn_STATUS_OFF
, 16, 16),
84 REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS
, TM_Sn_STATUS_OFF
, 17, 17),
85 REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS
, TM_Sn_STATUS_OFF
, 18, 18),
86 REG_FIELD_FOR_EACH_SENSOR16(CRITICAL_STATUS
, TM_Sn_STATUS_OFF
, 19, 19),
87 REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS
, TM_Sn_STATUS_OFF
, 20, 20),
89 /* TRDY: 1=ready, 0=in progress */
90 [TRDY
] = REG_FIELD(TM_TRDY_OFF
, 0, 0),
93 static const struct tsens_ops ops_generic_v2
= {
95 .get_temp
= get_temp_tsens_valid
,
98 struct tsens_plat_data data_tsens_v2
= {
99 .ops
= &ops_generic_v2
,
100 .feat
= &tsens_v2_feat
,
101 .fields
= tsens_v2_regfields
,
104 /* Kept around for backward compatibility with old msm8996.dtsi */
105 struct tsens_plat_data data_8996
= {
107 .ops
= &ops_generic_v2
,
108 .feat
= &tsens_v2_feat
,
109 .fields
= tsens_v2_regfields
,