drivers/tty/serial/8250/8250_ingenic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
   4  * Copyright (C) 2015 Imagination Technologies
   5  *
   6  * Ingenic SoC UART support
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/console.h>
  11 #include <linux/io.h>
  12 #include <linux/libfdt.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_fdt.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/serial_8250.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/serial_reg.h>
  21
  22 #include "8250.h"
  23
  24 /** ingenic_uart_config: SOC specific config data. */
  25 struct ingenic_uart_config {
  26         int tx_loadsz;
  27         int fifosize;
  28 };
  29
  30 struct ingenic_uart_data {
  31         struct clk      *clk_module;
  32         struct clk      *clk_baud;
  33         int             line;
  34 };
  35
  36 static const struct of_device_id of_match[];
  37
  38 #define UART_FCR_UME    BIT(4)
  39
  40 #define UART_MCR_MDCE   BIT(7)
  41 #define UART_MCR_FCM    BIT(6)
  42
  43 static struct earlycon_device *early_device;
  44
  45 static uint8_t early_in(struct uart_port *port, int offset)
  46 {
  47         return readl(port->membase + (offset << 2));
  48 }
  49
  50 static void early_out(struct uart_port *port, int offset, uint8_t value)
  51 {
  52         writel(value, port->membase + (offset << 2));
  53 }
  54
  55 static void ingenic_early_console_putc(struct uart_port *port, int c)
  56 {
  57         uint8_t lsr;
  58
  59         do {
  60                 lsr = early_in(port, UART_LSR);
  61         } while ((lsr & UART_LSR_TEMT) == 0);
  62
  63         early_out(port, UART_TX, c);
  64 }
  65
  66 static void ingenic_early_console_write(struct console *console,
  67                                               const char *s, unsigned int count)
  68 {
  69         uart_console_write(&early_device->port, s, count,
  70                            ingenic_early_console_putc);
  71 }
  72
  73 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
  74 {
  75         void *fdt = initial_boot_params;
  76         const __be32 *prop;
  77         int offset;
  78
  79         offset = fdt_path_offset(fdt, "/ext");
  80         if (offset < 0)
  81                 return;
  82
  83         prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
  84         if (!prop)
  85                 return;
  86
  87         dev->port.uartclk = be32_to_cpup(prop);
  88 }
  89
  90 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
  91                                               const char *opt)
  92 {
  93         struct uart_port *port = &dev->port;
  94         unsigned int divisor;
  95         int baud = 115200;
  96
  97         if (!dev->port.membase)
  98                 return -ENODEV;
  99
 100         if (opt) {
 101                 unsigned int parity, bits, flow; /* unused for now */
 102
 103                 uart_parse_options(opt, &baud, &parity, &bits, &flow);
 104         }
 105
 106         ingenic_early_console_setup_clock(dev);
 107
 108         if (dev->baud)
 109                 baud = dev->baud;
 110         divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
 111
 112         early_out(port, UART_IER, 0);
 113         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 114         early_out(port, UART_DLL, 0);
 115         early_out(port, UART_DLM, 0);
 116         early_out(port, UART_LCR, UART_LCR_WLEN8);
 117         early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
 118                         UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
 119         early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
 120
 121         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 122         early_out(port, UART_DLL, divisor & 0xff);
 123         early_out(port, UART_DLM, (divisor >> 8) & 0xff);
 124         early_out(port, UART_LCR, UART_LCR_WLEN8);
 125
 126         early_device = dev;
 127         dev->con->write = ingenic_early_console_write;
 128
 129         return 0;
 130 }
 131
 132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
 133                     ingenic_early_console_setup);
 134
 135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
 136                     ingenic_early_console_setup);
 137
 138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
 139                     ingenic_early_console_setup);
 140
 141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
 142                     ingenic_early_console_setup);
 143
 144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
 145                     ingenic_early_console_setup);
 146
 147 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 148 {
 149         int ier;
 150
 151         switch (offset) {
 152         case UART_FCR:
 153                 /* UART module enable */
 154                 value |= UART_FCR_UME;
 155                 break;
 156
 157         case UART_IER:
 158                 /*
 159                  * Enable receive timeout interrupt with the receive line
 160                  * status interrupt.
 161                  */
 162                 value |= (value & 0x4) << 2;
 163                 break;
 164
 165         case UART_MCR:
 166                 /*
 167                  * If we have enabled modem status IRQs we should enable
 168                  * modem mode.
 169                  */
 170                 ier = p->serial_in(p, UART_IER);
 171
 172                 if (ier & UART_IER_MSI)
 173                         value |= UART_MCR_MDCE | UART_MCR_FCM;
 174                 else
 175                         value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 176                 break;
 177
 178         default:
 179                 break;
 180         }
 181
 182         writeb(value, p->membase + (offset << p->regshift));
 183 }
 184
 185 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
 186 {
 187         unsigned int value;
 188
 189         value = readb(p->membase + (offset << p->regshift));
 190
 191         /* Hide non-16550 compliant bits from higher levels */
 192         switch (offset) {
 193         case UART_FCR:
 194                 value &= ~UART_FCR_UME;
 195                 break;
 196
 197         case UART_MCR:
 198                 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 199                 break;
 200
 201         default:
 202                 break;
 203         }
 204         return value;
 205 }
 206
 207 static int ingenic_uart_probe(struct platform_device *pdev)
 208 {
 209         struct uart_8250_port uart = {};
 210         struct ingenic_uart_data *data;
 211         const struct ingenic_uart_config *cdata;
 212         const struct of_device_id *match;
 213         struct resource *regs;
 214         int irq, err, line;
 215
 216         match = of_match_device(of_match, &pdev->dev);
 217         if (!match) {
 218                 dev_err(&pdev->dev, "Error: No device match found\n");
 219                 return -ENODEV;
 220         }
 221         cdata = match->data;
 222
 223         irq = platform_get_irq(pdev, 0);
 224         if (irq < 0)
 225                 return irq;
 226
 227         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 228         if (!regs) {
 229                 dev_err(&pdev->dev, "no registers defined\n");
 230                 return -EINVAL;
 231         }
 232
 233         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 234         if (!data)
 235                 return -ENOMEM;
 236
 237         spin_lock_init(&uart.port.lock);
 238         uart.port.type = PORT_16550A;
 239         uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
 240         uart.port.iotype = UPIO_MEM;
 241         uart.port.mapbase = regs->start;
 242         uart.port.regshift = 2;
 243         uart.port.serial_out = ingenic_uart_serial_out;
 244         uart.port.serial_in = ingenic_uart_serial_in;
 245         uart.port.irq = irq;
 246         uart.port.dev = &pdev->dev;
 247         uart.port.fifosize = cdata->fifosize;
 248         uart.tx_loadsz = cdata->tx_loadsz;
 249         uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
 250
 251         /* Check for a fixed line number */
 252         line = of_alias_get_id(pdev->dev.of_node, "serial");
 253         if (line >= 0)
 254                 uart.port.line = line;
 255
 256         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 257                                          resource_size(regs));
 258         if (!uart.port.membase)
 259                 return -ENOMEM;
 260
 261         data->clk_module = devm_clk_get(&pdev->dev, "module");
 262         if (IS_ERR(data->clk_module))
 263                 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
 264                                      "unable to get module clock\n");
 265
 266         data->clk_baud = devm_clk_get(&pdev->dev, "baud");
 267         if (IS_ERR(data->clk_baud))
 268                 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
 269                                      "unable to get baud clock\n");
 270
 271         err = clk_prepare_enable(data->clk_module);
 272         if (err) {
 273                 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
 274                 goto out;
 275         }
 276
 277         err = clk_prepare_enable(data->clk_baud);
 278         if (err) {
 279                 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
 280                 goto out_disable_moduleclk;
 281         }
 282         uart.port.uartclk = clk_get_rate(data->clk_baud);
 283
 284         data->line = serial8250_register_8250_port(&uart);
 285         if (data->line < 0) {
 286                 err = data->line;
 287                 goto out_disable_baudclk;
 288         }
 289
 290         platform_set_drvdata(pdev, data);
 291         return 0;
 292
 293 out_disable_baudclk:
 294         clk_disable_unprepare(data->clk_baud);
 295 out_disable_moduleclk:
 296         clk_disable_unprepare(data->clk_module);
 297 out:
 298         return err;
 299 }
 300
 301 static int ingenic_uart_remove(struct platform_device *pdev)
 302 {
 303         struct ingenic_uart_data *data = platform_get_drvdata(pdev);
 304
 305         serial8250_unregister_port(data->line);
 306         clk_disable_unprepare(data->clk_module);
 307         clk_disable_unprepare(data->clk_baud);
 308         return 0;
 309 }
 310
 311 static const struct ingenic_uart_config jz4740_uart_config = {
 312         .tx_loadsz = 8,
 313         .fifosize = 16,
 314 };
 315
 316 static const struct ingenic_uart_config jz4760_uart_config = {
 317         .tx_loadsz = 16,
 318         .fifosize = 32,
 319 };
 320
 321 static const struct ingenic_uart_config jz4780_uart_config = {
 322         .tx_loadsz = 32,
 323         .fifosize = 64,
 324 };
 325
 326 static const struct ingenic_uart_config x1000_uart_config = {
 327         .tx_loadsz = 32,
 328         .fifosize = 64,
 329 };
 330
 331 static const struct of_device_id of_match[] = {
 332         { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
 333         { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
 334         { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
 335         { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
 336         { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
 337         { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
 338         { /* sentinel */ }
 339 };
 340 MODULE_DEVICE_TABLE(of, of_match);
 341
 342 static struct platform_driver ingenic_uart_platform_driver = {
 343         .driver = {
 344                 .name           = "ingenic-uart",
 345                 .of_match_table = of_match,
 346         },
 347         .probe                  = ingenic_uart_probe,
 348         .remove                 = ingenic_uart_remove,
 349 };
 350
 351 module_platform_driver(ingenic_uart_platform_driver);
 352
 353 MODULE_AUTHOR("Paul Burton");
 354 MODULE_LICENSE("GPL");
 355 MODULE_DESCRIPTION("Ingenic SoC UART driver");