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WIP FPC-III support
[linux/fpc-iii.git] / drivers / tty / serial / bcm63xx_uart.c
blob5674da2b76f0f23b4681f181aed82aab347abc98
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Derived from many drivers using generic_serial interface.
4 *
5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6 *
7 * Serial driver for BCM63xx integrated UART.
8 *
9 * Hardware flow control was _not_ tested since I only have RX/TX on
10 * my board.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/console.h>
19 #include <linux/clk.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/sysrq.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial_bcm63xx.h>
26 #include <linux/io.h>
27 #include <linux/of.h>
28
29 #define BCM63XX_NR_UARTS 2
30
31 static struct uart_port ports[BCM63XX_NR_UARTS];
32
33 /*
34 * rx interrupt mask / stat
35 *
36 * mask:
37 * - rx fifo full
38 * - rx fifo above threshold
39 * - rx fifo not empty for too long
40 */
41 #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
42 UART_IR_MASK(UART_IR_RXTHRESH) | \
43 UART_IR_MASK(UART_IR_RXTIMEOUT))
44
45 #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
46 UART_IR_STAT(UART_IR_RXTHRESH) | \
47 UART_IR_STAT(UART_IR_RXTIMEOUT))
48
49 /*
50 * tx interrupt mask / stat
51 *
52 * mask:
53 * - tx fifo empty
54 * - tx fifo below threshold
55 */
56 #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
57 UART_IR_MASK(UART_IR_TXTRESH))
58
59 #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
60 UART_IR_STAT(UART_IR_TXTRESH))
61
62 /*
63 * external input interrupt
64 *
65 * mask: any edge on CTS, DCD
66 */
67 #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
68 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
69
70 /*
71 * handy uart register accessor
72 */
73 static inline unsigned int bcm_uart_readl(struct uart_port *port,
74 unsigned int offset)
75 {
76 return __raw_readl(port->membase + offset);
77 }
78
79 static inline void bcm_uart_writel(struct uart_port *port,
80 unsigned int value, unsigned int offset)
81 {
82 __raw_writel(value, port->membase + offset);
83 }
84
85 /*
86 * serial core request to check if uart tx fifo is empty
87 */
88 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
89 {
90 unsigned int val;
91
92 val = bcm_uart_readl(port, UART_IR_REG);
93 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
94 }
95
96 /*
97 * serial core request to set RTS and DTR pin state and loopback mode
98 */
99 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
100 {
101 unsigned int val;
102
103 val = bcm_uart_readl(port, UART_MCTL_REG);
104 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
105 /* invert of written value is reflected on the pin */
106 if (!(mctrl & TIOCM_DTR))
107 val |= UART_MCTL_DTR_MASK;
108 if (!(mctrl & TIOCM_RTS))
109 val |= UART_MCTL_RTS_MASK;
110 bcm_uart_writel(port, val, UART_MCTL_REG);
111
112 val = bcm_uart_readl(port, UART_CTL_REG);
113 if (mctrl & TIOCM_LOOP)
114 val |= UART_CTL_LOOPBACK_MASK;
115 else
116 val &= ~UART_CTL_LOOPBACK_MASK;
117 bcm_uart_writel(port, val, UART_CTL_REG);
118 }
119
120 /*
121 * serial core request to return RI, CTS, DCD and DSR pin state
122 */
123 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
124 {
125 unsigned int val, mctrl;
126
127 mctrl = 0;
128 val = bcm_uart_readl(port, UART_EXTINP_REG);
129 if (val & UART_EXTINP_RI_MASK)
130 mctrl |= TIOCM_RI;
131 if (val & UART_EXTINP_CTS_MASK)
132 mctrl |= TIOCM_CTS;
133 if (val & UART_EXTINP_DCD_MASK)
134 mctrl |= TIOCM_CD;
135 if (val & UART_EXTINP_DSR_MASK)
136 mctrl |= TIOCM_DSR;
137 return mctrl;
138 }
139
140 /*
141 * serial core request to disable tx ASAP (used for flow control)
142 */
143 static void bcm_uart_stop_tx(struct uart_port *port)
144 {
145 unsigned int val;
146
147 val = bcm_uart_readl(port, UART_CTL_REG);
148 val &= ~(UART_CTL_TXEN_MASK);
149 bcm_uart_writel(port, val, UART_CTL_REG);
150
151 val = bcm_uart_readl(port, UART_IR_REG);
152 val &= ~UART_TX_INT_MASK;
153 bcm_uart_writel(port, val, UART_IR_REG);
154 }
155
156 /*
157 * serial core request to (re)enable tx
158 */
159 static void bcm_uart_start_tx(struct uart_port *port)
160 {
161 unsigned int val;
162
163 val = bcm_uart_readl(port, UART_IR_REG);
164 val |= UART_TX_INT_MASK;
165 bcm_uart_writel(port, val, UART_IR_REG);
166
167 val = bcm_uart_readl(port, UART_CTL_REG);
168 val |= UART_CTL_TXEN_MASK;
169 bcm_uart_writel(port, val, UART_CTL_REG);
170 }
171
172 /*
173 * serial core request to stop rx, called before port shutdown
174 */
175 static void bcm_uart_stop_rx(struct uart_port *port)
176 {
177 unsigned int val;
178
179 val = bcm_uart_readl(port, UART_IR_REG);
180 val &= ~UART_RX_INT_MASK;
181 bcm_uart_writel(port, val, UART_IR_REG);
182 }
183
184 /*
185 * serial core request to enable modem status interrupt reporting
186 */
187 static void bcm_uart_enable_ms(struct uart_port *port)
188 {
189 unsigned int val;
190
191 val = bcm_uart_readl(port, UART_IR_REG);
192 val |= UART_IR_MASK(UART_IR_EXTIP);
193 bcm_uart_writel(port, val, UART_IR_REG);
194 }
195
196 /*
197 * serial core request to start/stop emitting break char
198 */
199 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
200 {
201 unsigned long flags;
202 unsigned int val;
203
204 spin_lock_irqsave(&port->lock, flags);
205
206 val = bcm_uart_readl(port, UART_CTL_REG);
207 if (ctl)
208 val |= UART_CTL_XMITBRK_MASK;
209 else
210 val &= ~UART_CTL_XMITBRK_MASK;
211 bcm_uart_writel(port, val, UART_CTL_REG);
212
213 spin_unlock_irqrestore(&port->lock, flags);
214 }
215
216 /*
217 * return port type in string format
218 */
219 static const char *bcm_uart_type(struct uart_port *port)
220 {
221 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
222 }
223
224 /*
225 * read all chars in rx fifo and send them to core
226 */
227 static void bcm_uart_do_rx(struct uart_port *port)
228 {
229 struct tty_port *tty_port = &port->state->port;
230 unsigned int max_count;
231
232 /* limit number of char read in interrupt, should not be
233 * higher than fifo size anyway since we're much faster than
234 * serial port */
235 max_count = 32;
236 do {
237 unsigned int iestat, c, cstat;
238 char flag;
239
240 /* get overrun/fifo empty information from ier
241 * register */
242 iestat = bcm_uart_readl(port, UART_IR_REG);
243
244 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
245 unsigned int val;
246
247 /* fifo reset is required to clear
248 * interrupt */
249 val = bcm_uart_readl(port, UART_CTL_REG);
250 val |= UART_CTL_RSTRXFIFO_MASK;
251 bcm_uart_writel(port, val, UART_CTL_REG);
252
253 port->icount.overrun++;
254 tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
255 }
256
257 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
258 break;
259
260 cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
261 port->icount.rx++;
262 flag = TTY_NORMAL;
263 c &= 0xff;
264
265 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
266 /* do stats first */
267 if (cstat & UART_FIFO_BRKDET_MASK) {
268 port->icount.brk++;
269 if (uart_handle_break(port))
270 continue;
271 }
272
273 if (cstat & UART_FIFO_PARERR_MASK)
274 port->icount.parity++;
275 if (cstat & UART_FIFO_FRAMEERR_MASK)
276 port->icount.frame++;
277
278 /* update flag wrt read_status_mask */
279 cstat &= port->read_status_mask;
280 if (cstat & UART_FIFO_BRKDET_MASK)
281 flag = TTY_BREAK;
282 if (cstat & UART_FIFO_FRAMEERR_MASK)
283 flag = TTY_FRAME;
284 if (cstat & UART_FIFO_PARERR_MASK)
285 flag = TTY_PARITY;
286 }
287
288 if (uart_handle_sysrq_char(port, c))
289 continue;
290
291
292 if ((cstat & port->ignore_status_mask) == 0)
293 tty_insert_flip_char(tty_port, c, flag);
294
295 } while (--max_count);
296
297 spin_unlock(&port->lock);
298 tty_flip_buffer_push(tty_port);
299 spin_lock(&port->lock);
300 }
301
302 /*
303 * fill tx fifo with chars to send, stop when fifo is about to be full
304 * or when all chars have been sent.
305 */
306 static void bcm_uart_do_tx(struct uart_port *port)
307 {
308 struct circ_buf *xmit;
309 unsigned int val, max_count;
310
311 if (port->x_char) {
312 bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
313 port->icount.tx++;
314 port->x_char = 0;
315 return;
316 }
317
318 if (uart_tx_stopped(port)) {
319 bcm_uart_stop_tx(port);
320 return;
321 }
322
323 xmit = &port->state->xmit;
324 if (uart_circ_empty(xmit))
325 goto txq_empty;
326
327 val = bcm_uart_readl(port, UART_MCTL_REG);
328 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
329 max_count = port->fifosize - val;
330
331 while (max_count--) {
332 unsigned int c;
333
334 c = xmit->buf[xmit->tail];
335 bcm_uart_writel(port, c, UART_FIFO_REG);
336 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
337 port->icount.tx++;
338 if (uart_circ_empty(xmit))
339 break;
340 }
341
342 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
344
345 if (uart_circ_empty(xmit))
346 goto txq_empty;
347 return;
348
349 txq_empty:
350 /* nothing to send, disable transmit interrupt */
351 val = bcm_uart_readl(port, UART_IR_REG);
352 val &= ~UART_TX_INT_MASK;
353 bcm_uart_writel(port, val, UART_IR_REG);
354 return;
355 }
356
357 /*
358 * process uart interrupt
359 */
360 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
361 {
362 struct uart_port *port;
363 unsigned int irqstat;
364
365 port = dev_id;
366 spin_lock(&port->lock);
367
368 irqstat = bcm_uart_readl(port, UART_IR_REG);
369 if (irqstat & UART_RX_INT_STAT)
370 bcm_uart_do_rx(port);
371
372 if (irqstat & UART_TX_INT_STAT)
373 bcm_uart_do_tx(port);
374
375 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
376 unsigned int estat;
377
378 estat = bcm_uart_readl(port, UART_EXTINP_REG);
379 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
380 uart_handle_cts_change(port,
381 estat & UART_EXTINP_CTS_MASK);
382 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
383 uart_handle_dcd_change(port,
384 estat & UART_EXTINP_DCD_MASK);
385 }
386
387 spin_unlock(&port->lock);
388 return IRQ_HANDLED;
389 }
390
391 /*
392 * enable rx & tx operation on uart
393 */
394 static void bcm_uart_enable(struct uart_port *port)
395 {
396 unsigned int val;
397
398 val = bcm_uart_readl(port, UART_CTL_REG);
399 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
400 bcm_uart_writel(port, val, UART_CTL_REG);
401 }
402
403 /*
404 * disable rx & tx operation on uart
405 */
406 static void bcm_uart_disable(struct uart_port *port)
407 {
408 unsigned int val;
409
410 val = bcm_uart_readl(port, UART_CTL_REG);
411 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
412 UART_CTL_RXEN_MASK);
413 bcm_uart_writel(port, val, UART_CTL_REG);
414 }
415
416 /*
417 * clear all unread data in rx fifo and unsent data in tx fifo
418 */
419 static void bcm_uart_flush(struct uart_port *port)
420 {
421 unsigned int val;
422
423 /* empty rx and tx fifo */
424 val = bcm_uart_readl(port, UART_CTL_REG);
425 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
426 bcm_uart_writel(port, val, UART_CTL_REG);
427
428 /* read any pending char to make sure all irq status are
429 * cleared */
430 (void)bcm_uart_readl(port, UART_FIFO_REG);
431 }
432
433 /*
434 * serial core request to initialize uart and start rx operation
435 */
436 static int bcm_uart_startup(struct uart_port *port)
437 {
438 unsigned int val;
439 int ret;
440
441 /* mask all irq and flush port */
442 bcm_uart_disable(port);
443 bcm_uart_writel(port, 0, UART_IR_REG);
444 bcm_uart_flush(port);
445
446 /* clear any pending external input interrupt */
447 (void)bcm_uart_readl(port, UART_EXTINP_REG);
448
449 /* set rx/tx fifo thresh to fifo half size */
450 val = bcm_uart_readl(port, UART_MCTL_REG);
451 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
452 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
453 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
454 bcm_uart_writel(port, val, UART_MCTL_REG);
455
456 /* set rx fifo timeout to 1 char time */
457 val = bcm_uart_readl(port, UART_CTL_REG);
458 val &= ~UART_CTL_RXTMOUTCNT_MASK;
459 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
460 bcm_uart_writel(port, val, UART_CTL_REG);
461
462 /* report any edge on dcd and cts */
463 val = UART_EXTINP_INT_MASK;
464 val |= UART_EXTINP_DCD_NOSENSE_MASK;
465 val |= UART_EXTINP_CTS_NOSENSE_MASK;
466 bcm_uart_writel(port, val, UART_EXTINP_REG);
467
468 /* register irq and enable rx interrupts */
469 ret = request_irq(port->irq, bcm_uart_interrupt, 0,
470 dev_name(port->dev), port);
471 if (ret)
472 return ret;
473 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
474 bcm_uart_enable(port);
475 return 0;
476 }
477
478 /*
479 * serial core request to flush & disable uart
480 */
481 static void bcm_uart_shutdown(struct uart_port *port)
482 {
483 unsigned long flags;
484
485 spin_lock_irqsave(&port->lock, flags);
486 bcm_uart_writel(port, 0, UART_IR_REG);
487 spin_unlock_irqrestore(&port->lock, flags);
488
489 bcm_uart_disable(port);
490 bcm_uart_flush(port);
491 free_irq(port->irq, port);
492 }
493
494 /*
495 * serial core request to change current uart setting
496 */
497 static void bcm_uart_set_termios(struct uart_port *port,
498 struct ktermios *new,
499 struct ktermios *old)
500 {
501 unsigned int ctl, baud, quot, ier;
502 unsigned long flags;
503 int tries;
504
505 spin_lock_irqsave(&port->lock, flags);
506
507 /* Drain the hot tub fully before we power it off for the winter. */
508 for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
509 mdelay(10);
510
511 /* disable uart while changing speed */
512 bcm_uart_disable(port);
513 bcm_uart_flush(port);
514
515 /* update Control register */
516 ctl = bcm_uart_readl(port, UART_CTL_REG);
517 ctl &= ~UART_CTL_BITSPERSYM_MASK;
518
519 switch (new->c_cflag & CSIZE) {
520 case CS5:
521 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
522 break;
523 case CS6:
524 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
525 break;
526 case CS7:
527 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
528 break;
529 default:
530 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
531 break;
532 }
533
534 ctl &= ~UART_CTL_STOPBITS_MASK;
535 if (new->c_cflag & CSTOPB)
536 ctl |= UART_CTL_STOPBITS_2;
537 else
538 ctl |= UART_CTL_STOPBITS_1;
539
540 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
541 if (new->c_cflag & PARENB)
542 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
543 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
544 if (new->c_cflag & PARODD)
545 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
546 bcm_uart_writel(port, ctl, UART_CTL_REG);
547
548 /* update Baudword register */
549 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
550 quot = uart_get_divisor(port, baud) - 1;
551 bcm_uart_writel(port, quot, UART_BAUD_REG);
552
553 /* update Interrupt register */
554 ier = bcm_uart_readl(port, UART_IR_REG);
555
556 ier &= ~UART_IR_MASK(UART_IR_EXTIP);
557 if (UART_ENABLE_MS(port, new->c_cflag))
558 ier |= UART_IR_MASK(UART_IR_EXTIP);
559
560 bcm_uart_writel(port, ier, UART_IR_REG);
561
562 /* update read/ignore mask */
563 port->read_status_mask = UART_FIFO_VALID_MASK;
564 if (new->c_iflag & INPCK) {
565 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
566 port->read_status_mask |= UART_FIFO_PARERR_MASK;
567 }
568 if (new->c_iflag & (IGNBRK | BRKINT))
569 port->read_status_mask |= UART_FIFO_BRKDET_MASK;
570
571 port->ignore_status_mask = 0;
572 if (new->c_iflag & IGNPAR)
573 port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
574 if (new->c_iflag & IGNBRK)
575 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
576 if (!(new->c_cflag & CREAD))
577 port->ignore_status_mask |= UART_FIFO_VALID_MASK;
578
579 uart_update_timeout(port, new->c_cflag, baud);
580 bcm_uart_enable(port);
581 spin_unlock_irqrestore(&port->lock, flags);
582 }
583
584 /*
585 * serial core request to claim uart iomem
586 */
587 static int bcm_uart_request_port(struct uart_port *port)
588 {
589 /* UARTs always present */
590 return 0;
591 }
592
593 /*
594 * serial core request to release uart iomem
595 */
596 static void bcm_uart_release_port(struct uart_port *port)
597 {
598 /* Nothing to release ... */
599 }
600
601 /*
602 * serial core request to do any port required autoconfiguration
603 */
604 static void bcm_uart_config_port(struct uart_port *port, int flags)
605 {
606 if (flags & UART_CONFIG_TYPE) {
607 if (bcm_uart_request_port(port))
608 return;
609 port->type = PORT_BCM63XX;
610 }
611 }
612
613 /*
614 * serial core request to check that port information in serinfo are
615 * suitable
616 */
617 static int bcm_uart_verify_port(struct uart_port *port,
618 struct serial_struct *serinfo)
619 {
620 if (port->type != PORT_BCM63XX)
621 return -EINVAL;
622 if (port->irq != serinfo->irq)
623 return -EINVAL;
624 if (port->iotype != serinfo->io_type)
625 return -EINVAL;
626 if (port->mapbase != (unsigned long)serinfo->iomem_base)
627 return -EINVAL;
628 return 0;
629 }
630
631 /* serial core callbacks */
632 static const struct uart_ops bcm_uart_ops = {
633 .tx_empty = bcm_uart_tx_empty,
634 .get_mctrl = bcm_uart_get_mctrl,
635 .set_mctrl = bcm_uart_set_mctrl,
636 .start_tx = bcm_uart_start_tx,
637 .stop_tx = bcm_uart_stop_tx,
638 .stop_rx = bcm_uart_stop_rx,
639 .enable_ms = bcm_uart_enable_ms,
640 .break_ctl = bcm_uart_break_ctl,
641 .startup = bcm_uart_startup,
642 .shutdown = bcm_uart_shutdown,
643 .set_termios = bcm_uart_set_termios,
644 .type = bcm_uart_type,
645 .release_port = bcm_uart_release_port,
646 .request_port = bcm_uart_request_port,
647 .config_port = bcm_uart_config_port,
648 .verify_port = bcm_uart_verify_port,
649 };
650
651
652
653 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
654 static void wait_for_xmitr(struct uart_port *port)
655 {
656 unsigned int tmout;
657
658 /* Wait up to 10ms for the character(s) to be sent. */
659 tmout = 10000;
660 while (--tmout) {
661 unsigned int val;
662
663 val = bcm_uart_readl(port, UART_IR_REG);
664 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
665 break;
666 udelay(1);
667 }
668
669 /* Wait up to 1s for flow control if necessary */
670 if (port->flags & UPF_CONS_FLOW) {
671 tmout = 1000000;
672 while (--tmout) {
673 unsigned int val;
674
675 val = bcm_uart_readl(port, UART_EXTINP_REG);
676 if (val & UART_EXTINP_CTS_MASK)
677 break;
678 udelay(1);
679 }
680 }
681 }
682
683 /*
684 * output given char
685 */
686 static void bcm_console_putchar(struct uart_port *port, int ch)
687 {
688 wait_for_xmitr(port);
689 bcm_uart_writel(port, ch, UART_FIFO_REG);
690 }
691
692 /*
693 * console core request to output given string
694 */
695 static void bcm_console_write(struct console *co, const char *s,
696 unsigned int count)
697 {
698 struct uart_port *port;
699 unsigned long flags;
700 int locked;
701
702 port = &ports[co->index];
703
704 local_irq_save(flags);
705 if (port->sysrq) {
706 /* bcm_uart_interrupt() already took the lock */
707 locked = 0;
708 } else if (oops_in_progress) {
709 locked = spin_trylock(&port->lock);
710 } else {
711 spin_lock(&port->lock);
712 locked = 1;
713 }
714
715 /* call helper to deal with \r\n */
716 uart_console_write(port, s, count, bcm_console_putchar);
717
718 /* and wait for char to be transmitted */
719 wait_for_xmitr(port);
720
721 if (locked)
722 spin_unlock(&port->lock);
723 local_irq_restore(flags);
724 }
725
726 /*
727 * console core request to setup given console, find matching uart
728 * port and setup it.
729 */
730 static int bcm_console_setup(struct console *co, char *options)
731 {
732 struct uart_port *port;
733 int baud = 9600;
734 int bits = 8;
735 int parity = 'n';
736 int flow = 'n';
737
738 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
739 return -EINVAL;
740 port = &ports[co->index];
741 if (!port->membase)
742 return -ENODEV;
743 if (options)
744 uart_parse_options(options, &baud, &parity, &bits, &flow);
745
746 return uart_set_options(port, co, baud, parity, bits, flow);
747 }
748
749 static struct uart_driver bcm_uart_driver;
750
751 static struct console bcm63xx_console = {
752 .name = "ttyS",
753 .write = bcm_console_write,
754 .device = uart_console_device,
755 .setup = bcm_console_setup,
756 .flags = CON_PRINTBUFFER,
757 .index = -1,
758 .data = &bcm_uart_driver,
759 };
760
761 static int __init bcm63xx_console_init(void)
762 {
763 register_console(&bcm63xx_console);
764 return 0;
765 }
766
767 console_initcall(bcm63xx_console_init);
768
769 static void bcm_early_write(struct console *con, const char *s, unsigned n)
770 {
771 struct earlycon_device *dev = con->data;
772
773 uart_console_write(&dev->port, s, n, bcm_console_putchar);
774 wait_for_xmitr(&dev->port);
775 }
776
777 static int __init bcm_early_console_setup(struct earlycon_device *device,
778 const char *opt)
779 {
780 if (!device->port.membase)
781 return -ENODEV;
782
783 device->con->write = bcm_early_write;
784 return 0;
785 }
786
787 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
788
789 #define BCM63XX_CONSOLE (&bcm63xx_console)
790 #else
791 #define BCM63XX_CONSOLE NULL
792 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
793
794 static struct uart_driver bcm_uart_driver = {
795 .owner = THIS_MODULE,
796 .driver_name = "bcm63xx_uart",
797 .dev_name = "ttyS",
798 .major = TTY_MAJOR,
799 .minor = 64,
800 .nr = BCM63XX_NR_UARTS,
801 .cons = BCM63XX_CONSOLE,
802 };
803
804 /*
805 * platform driver probe/remove callback
806 */
807 static int bcm_uart_probe(struct platform_device *pdev)
808 {
809 struct resource *res_mem, *res_irq;
810 struct uart_port *port;
811 struct clk *clk;
812 int ret;
813
814 if (pdev->dev.of_node) {
815 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
816
817 if (pdev->id < 0)
818 pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
819 }
820
821 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
822 return -EINVAL;
823
824 port = &ports[pdev->id];
825 if (port->membase)
826 return -EBUSY;
827 memset(port, 0, sizeof(*port));
828
829 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 if (!res_mem)
831 return -ENODEV;
832
833 port->mapbase = res_mem->start;
834 port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
835 if (IS_ERR(port->membase))
836 return PTR_ERR(port->membase);
837
838 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
839 if (!res_irq)
840 return -ENODEV;
841
842 clk = clk_get(&pdev->dev, "refclk");
843 if (IS_ERR(clk) && pdev->dev.of_node)
844 clk = of_clk_get(pdev->dev.of_node, 0);
845
846 if (IS_ERR(clk))
847 return -ENODEV;
848
849 port->iotype = UPIO_MEM;
850 port->irq = res_irq->start;
851 port->ops = &bcm_uart_ops;
852 port->flags = UPF_BOOT_AUTOCONF;
853 port->dev = &pdev->dev;
854 port->fifosize = 16;
855 port->uartclk = clk_get_rate(clk) / 2;
856 port->line = pdev->id;
857 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
858 clk_put(clk);
859
860 ret = uart_add_one_port(&bcm_uart_driver, port);
861 if (ret) {
862 ports[pdev->id].membase = NULL;
863 return ret;
864 }
865 platform_set_drvdata(pdev, port);
866 return 0;
867 }
868
869 static int bcm_uart_remove(struct platform_device *pdev)
870 {
871 struct uart_port *port;
872
873 port = platform_get_drvdata(pdev);
874 uart_remove_one_port(&bcm_uart_driver, port);
875 /* mark port as free */
876 ports[pdev->id].membase = NULL;
877 return 0;
878 }
879
880 static const struct of_device_id bcm63xx_of_match[] = {
881 { .compatible = "brcm,bcm6345-uart" },
882 { /* sentinel */ }
883 };
884 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
885
886 /*
887 * platform driver stuff
888 */
889 static struct platform_driver bcm_uart_platform_driver = {
890 .probe = bcm_uart_probe,
891 .remove = bcm_uart_remove,
892 .driver = {
893 .name = "bcm63xx_uart",
894 .of_match_table = bcm63xx_of_match,
895 },
896 };
897
898 static int __init bcm_uart_init(void)
899 {
900 int ret;
901
902 ret = uart_register_driver(&bcm_uart_driver);
903 if (ret)
904 return ret;
905
906 ret = platform_driver_register(&bcm_uart_platform_driver);
907 if (ret)
908 uart_unregister_driver(&bcm_uart_driver);
909
910 return ret;
911 }
912
913 static void __exit bcm_uart_exit(void)
914 {
915 platform_driver_unregister(&bcm_uart_platform_driver);
916 uart_unregister_driver(&bcm_uart_driver);
917 }
918
919 module_init(bcm_uart_init);
920 module_exit(bcm_uart_exit);
921
922 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
923 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
924 MODULE_LICENSE("GPL");
Linux with added FPC-III support