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WIP FPC-III support
[linux/fpc-iii.git] / drivers / usb / gadget / udc / lpc32xx_udc.c
blob3f1c62adce4b67912b870e302f28aeb0abbe7998
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * USB Gadget driver for LPC32xx
4 *
5 * Authors:
6 * Kevin Wells <kevin.wells@nxp.com>
7 * Mike James
8 * Roland Stigge <stigge@antcom.de>
9 *
10 * Copyright (C) 2006 Philips Semiconductors
11 * Copyright (C) 2009 NXP Semiconductors
12 * Copyright (C) 2012 Roland Stigge
13 *
14 * Note: This driver is based on original work done by Mike James for
15 * the LPC3180.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/i2c.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/platform_device.h>
27 #include <linux/prefetch.h>
28 #include <linux/proc_fs.h>
29 #include <linux/slab.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/isp1301.h>
33
34 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif
38
39 /*
40 * USB device configuration structure
41 */
42 typedef void (*usc_chg_event)(int);
43 struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
45 usc_chg_event conn_chgb; /* Connection change event (optional) */
46 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
47 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
48 };
49
50 /*
51 * controller driver data structures
52 */
53
54 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
55 #define NUM_ENDPOINTS 16
56
57 /*
58 * IRQ indices make reading the code a little easier
59 */
60 #define IRQ_USB_LP 0
61 #define IRQ_USB_HP 1
62 #define IRQ_USB_DEVDMA 2
63 #define IRQ_USB_ATX 3
64
65 #define EP_OUT 0 /* RX (from host) */
66 #define EP_IN 1 /* TX (to host) */
67
68 /* Returns the interrupt mask for the selected hardware endpoint */
69 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71 #define EP_INT_TYPE 0
72 #define EP_ISO_TYPE 1
73 #define EP_BLK_TYPE 2
74 #define EP_CTL_TYPE 3
75
76 /* EP0 states */
77 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
78 #define DATA_IN 1 /* Expect dev->host transfer */
79 #define DATA_OUT 2 /* Expect host->dev transfer */
80
81 /* DD (DMA Descriptor) structure, requires word alignment, this is already
82 * defined in the LPC32XX USB device header file, but this version is slightly
83 * modified to tag some work data with each DMA descriptor. */
84 struct lpc32xx_usbd_dd_gad {
85 u32 dd_next_phy;
86 u32 dd_setup;
87 u32 dd_buffer_addr;
88 u32 dd_status;
89 u32 dd_iso_ps_mem_addr;
90 u32 this_dma;
91 u32 iso_status[6]; /* 5 spare */
92 u32 dd_next_v;
93 };
94
95 /*
96 * Logical endpoint structure
97 */
98 struct lpc32xx_ep {
99 struct usb_ep ep;
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
102
103 u32 hwep_num_base; /* Physical hardware EP */
104 u32 hwep_num; /* Maps to hardware endpoint */
105 u32 maxpacket;
106 u32 lep;
107
108 bool is_in;
109 bool req_pending;
110 u32 eptype;
111
112 u32 totalints;
113
114 bool wedge;
115 };
116
117 enum atx_type {
118 ISP1301,
119 STOTG04,
120 };
121
122 /*
123 * Common UDC structure
124 */
125 struct lpc32xx_udc {
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
129 struct device *dev;
130 struct dentry *pde;
131 spinlock_t lock;
132 struct i2c_client *isp1301_i2c_client;
133
134 /* Board and device specific */
135 struct lpc32xx_usbd_cfg *board;
136 void __iomem *udp_baseaddr;
137 int udp_irq[4];
138 struct clk *usb_slv_clk;
139
140 /* DMA support */
141 u32 *udca_v_base;
142 u32 udca_p_base;
143 struct dma_pool *dd_cache;
144
145 /* Common EP and control data */
146 u32 enabled_devints;
147 u32 enabled_hwepints;
148 u32 dev_status;
149 u32 realized_eps;
150
151 /* VBUS detection, pullup, and power flags */
152 u8 vbus;
153 u8 last_vbus;
154 int pullup;
155 int poweron;
156 enum atx_type atx;
157
158 /* Work queues related to I2C support */
159 struct work_struct pullup_job;
160 struct work_struct power_job;
161
162 /* USB device peripheral - various */
163 struct lpc32xx_ep ep[NUM_ENDPOINTS];
164 bool enabled;
165 bool clocked;
166 bool suspended;
167 int ep0state;
168 atomic_t enabled_ep_cnt;
169 wait_queue_head_t ep_disable_wait_queue;
170 };
171
172 /*
173 * Endpoint request
174 */
175 struct lpc32xx_request {
176 struct usb_request req;
177 struct list_head queue;
178 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
179 bool mapped;
180 bool send_zlp;
181 };
182
183 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
184 {
185 return container_of(g, struct lpc32xx_udc, gadget);
186 }
187
188 #define ep_dbg(epp, fmt, arg...) \
189 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
190 #define ep_err(epp, fmt, arg...) \
191 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
192 #define ep_info(epp, fmt, arg...) \
193 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
194 #define ep_warn(epp, fmt, arg...) \
195 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
196
197 #define UDCA_BUFF_SIZE (128)
198
199 /**********************************************************************
200 * USB device controller register offsets
201 **********************************************************************/
202
203 #define USBD_DEVINTST(x) ((x) + 0x200)
204 #define USBD_DEVINTEN(x) ((x) + 0x204)
205 #define USBD_DEVINTCLR(x) ((x) + 0x208)
206 #define USBD_DEVINTSET(x) ((x) + 0x20C)
207 #define USBD_CMDCODE(x) ((x) + 0x210)
208 #define USBD_CMDDATA(x) ((x) + 0x214)
209 #define USBD_RXDATA(x) ((x) + 0x218)
210 #define USBD_TXDATA(x) ((x) + 0x21C)
211 #define USBD_RXPLEN(x) ((x) + 0x220)
212 #define USBD_TXPLEN(x) ((x) + 0x224)
213 #define USBD_CTRL(x) ((x) + 0x228)
214 #define USBD_DEVINTPRI(x) ((x) + 0x22C)
215 #define USBD_EPINTST(x) ((x) + 0x230)
216 #define USBD_EPINTEN(x) ((x) + 0x234)
217 #define USBD_EPINTCLR(x) ((x) + 0x238)
218 #define USBD_EPINTSET(x) ((x) + 0x23C)
219 #define USBD_EPINTPRI(x) ((x) + 0x240)
220 #define USBD_REEP(x) ((x) + 0x244)
221 #define USBD_EPIND(x) ((x) + 0x248)
222 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
223 /* DMA support registers only below */
224 /* Set, clear, or get enabled state of the DMA request status. If
225 * enabled, an IN or OUT token will start a DMA transfer for the EP */
226 #define USBD_DMARST(x) ((x) + 0x250)
227 #define USBD_DMARCLR(x) ((x) + 0x254)
228 #define USBD_DMARSET(x) ((x) + 0x258)
229 /* DMA UDCA head pointer */
230 #define USBD_UDCAH(x) ((x) + 0x280)
231 /* EP DMA status, enable, and disable. This is used to specifically
232 * enabled or disable DMA for a specific EP */
233 #define USBD_EPDMAST(x) ((x) + 0x284)
234 #define USBD_EPDMAEN(x) ((x) + 0x288)
235 #define USBD_EPDMADIS(x) ((x) + 0x28C)
236 /* DMA master interrupts enable and pending interrupts */
237 #define USBD_DMAINTST(x) ((x) + 0x290)
238 #define USBD_DMAINTEN(x) ((x) + 0x294)
239 /* DMA end of transfer interrupt enable, disable, status */
240 #define USBD_EOTINTST(x) ((x) + 0x2A0)
241 #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
242 #define USBD_EOTINTSET(x) ((x) + 0x2A8)
243 /* New DD request interrupt enable, disable, status */
244 #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
245 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
246 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
247 /* DMA error interrupt enable, disable, status */
248 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
249 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
250 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
251
252 /**********************************************************************
253 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
254 * USBD_DEVINTPRI register definitions
255 **********************************************************************/
256 #define USBD_ERR_INT (1 << 9)
257 #define USBD_EP_RLZED (1 << 8)
258 #define USBD_TXENDPKT (1 << 7)
259 #define USBD_RXENDPKT (1 << 6)
260 #define USBD_CDFULL (1 << 5)
261 #define USBD_CCEMPTY (1 << 4)
262 #define USBD_DEV_STAT (1 << 3)
263 #define USBD_EP_SLOW (1 << 2)
264 #define USBD_EP_FAST (1 << 1)
265 #define USBD_FRAME (1 << 0)
266
267 /**********************************************************************
268 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
269 * USBD_EPINTPRI register definitions
270 **********************************************************************/
271 /* End point selection macro (RX) */
272 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
273
274 /* End point selection macro (TX) */
275 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
276
277 /**********************************************************************
278 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
279 * USBD_EPDMAEN/USBD_EPDMADIS/
280 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
281 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
282 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
283 * register definitions
284 **********************************************************************/
285 /* Endpoint selection macro */
286 #define USBD_EP_SEL(e) (1 << (e))
287
288 /**********************************************************************
289 * SBD_DMAINTST/USBD_DMAINTEN
290 **********************************************************************/
291 #define USBD_SYS_ERR_INT (1 << 2)
292 #define USBD_NEW_DD_INT (1 << 1)
293 #define USBD_EOT_INT (1 << 0)
294
295 /**********************************************************************
296 * USBD_RXPLEN register definitions
297 **********************************************************************/
298 #define USBD_PKT_RDY (1 << 11)
299 #define USBD_DV (1 << 10)
300 #define USBD_PK_LEN_MASK 0x3FF
301
302 /**********************************************************************
303 * USBD_CTRL register definitions
304 **********************************************************************/
305 #define USBD_LOG_ENDPOINT(e) ((e) << 2)
306 #define USBD_WR_EN (1 << 1)
307 #define USBD_RD_EN (1 << 0)
308
309 /**********************************************************************
310 * USBD_CMDCODE register definitions
311 **********************************************************************/
312 #define USBD_CMD_CODE(c) ((c) << 16)
313 #define USBD_CMD_PHASE(p) ((p) << 8)
314
315 /**********************************************************************
316 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
317 **********************************************************************/
318 #define USBD_DMAEP(e) (1 << (e))
319
320 /* DD (DMA Descriptor) structure, requires word alignment */
321 struct lpc32xx_usbd_dd {
322 u32 *dd_next;
323 u32 dd_setup;
324 u32 dd_buffer_addr;
325 u32 dd_status;
326 u32 dd_iso_ps_mem_addr;
327 };
328
329 /* dd_setup bit defines */
330 #define DD_SETUP_ATLE_DMA_MODE 0x01
331 #define DD_SETUP_NEXT_DD_VALID 0x04
332 #define DD_SETUP_ISO_EP 0x10
333 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
334 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
335
336 /* dd_status bit defines */
337 #define DD_STATUS_DD_RETIRED 0x01
338 #define DD_STATUS_STS_MASK 0x1E
339 #define DD_STATUS_STS_NS 0x00 /* Not serviced */
340 #define DD_STATUS_STS_BS 0x02 /* Being serviced */
341 #define DD_STATUS_STS_NC 0x04 /* Normal completion */
342 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
343 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
344 #define DD_STATUS_STS_SE 0x12 /* System error */
345 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
346 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
347 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
348 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
349 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
350
351 /*
352 *
353 * Protocol engine bits below
354 *
355 */
356 /* Device Interrupt Bit Definitions */
357 #define FRAME_INT 0x00000001
358 #define EP_FAST_INT 0x00000002
359 #define EP_SLOW_INT 0x00000004
360 #define DEV_STAT_INT 0x00000008
361 #define CCEMTY_INT 0x00000010
362 #define CDFULL_INT 0x00000020
363 #define RxENDPKT_INT 0x00000040
364 #define TxENDPKT_INT 0x00000080
365 #define EP_RLZED_INT 0x00000100
366 #define ERR_INT 0x00000200
367
368 /* Rx & Tx Packet Length Definitions */
369 #define PKT_LNGTH_MASK 0x000003FF
370 #define PKT_DV 0x00000400
371 #define PKT_RDY 0x00000800
372
373 /* USB Control Definitions */
374 #define CTRL_RD_EN 0x00000001
375 #define CTRL_WR_EN 0x00000002
376
377 /* Command Codes */
378 #define CMD_SET_ADDR 0x00D00500
379 #define CMD_CFG_DEV 0x00D80500
380 #define CMD_SET_MODE 0x00F30500
381 #define CMD_RD_FRAME 0x00F50500
382 #define DAT_RD_FRAME 0x00F50200
383 #define CMD_RD_TEST 0x00FD0500
384 #define DAT_RD_TEST 0x00FD0200
385 #define CMD_SET_DEV_STAT 0x00FE0500
386 #define CMD_GET_DEV_STAT 0x00FE0500
387 #define DAT_GET_DEV_STAT 0x00FE0200
388 #define CMD_GET_ERR_CODE 0x00FF0500
389 #define DAT_GET_ERR_CODE 0x00FF0200
390 #define CMD_RD_ERR_STAT 0x00FB0500
391 #define DAT_RD_ERR_STAT 0x00FB0200
392 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
393 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
394 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
395 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
396 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
397 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
398 #define CMD_CLR_BUF 0x00F20500
399 #define DAT_CLR_BUF 0x00F20200
400 #define CMD_VALID_BUF 0x00FA0500
401
402 /* Device Address Register Definitions */
403 #define DEV_ADDR_MASK 0x7F
404 #define DEV_EN 0x80
405
406 /* Device Configure Register Definitions */
407 #define CONF_DVICE 0x01
408
409 /* Device Mode Register Definitions */
410 #define AP_CLK 0x01
411 #define INAK_CI 0x02
412 #define INAK_CO 0x04
413 #define INAK_II 0x08
414 #define INAK_IO 0x10
415 #define INAK_BI 0x20
416 #define INAK_BO 0x40
417
418 /* Device Status Register Definitions */
419 #define DEV_CON 0x01
420 #define DEV_CON_CH 0x02
421 #define DEV_SUS 0x04
422 #define DEV_SUS_CH 0x08
423 #define DEV_RST 0x10
424
425 /* Error Code Register Definitions */
426 #define ERR_EC_MASK 0x0F
427 #define ERR_EA 0x10
428
429 /* Error Status Register Definitions */
430 #define ERR_PID 0x01
431 #define ERR_UEPKT 0x02
432 #define ERR_DCRC 0x04
433 #define ERR_TIMOUT 0x08
434 #define ERR_EOP 0x10
435 #define ERR_B_OVRN 0x20
436 #define ERR_BTSTF 0x40
437 #define ERR_TGL 0x80
438
439 /* Endpoint Select Register Definitions */
440 #define EP_SEL_F 0x01
441 #define EP_SEL_ST 0x02
442 #define EP_SEL_STP 0x04
443 #define EP_SEL_PO 0x08
444 #define EP_SEL_EPN 0x10
445 #define EP_SEL_B_1_FULL 0x20
446 #define EP_SEL_B_2_FULL 0x40
447
448 /* Endpoint Status Register Definitions */
449 #define EP_STAT_ST 0x01
450 #define EP_STAT_DA 0x20
451 #define EP_STAT_RF_MO 0x40
452 #define EP_STAT_CND_ST 0x80
453
454 /* Clear Buffer Register Definitions */
455 #define CLR_BUF_PO 0x01
456
457 /* DMA Interrupt Bit Definitions */
458 #define EOT_INT 0x01
459 #define NDD_REQ_INT 0x02
460 #define SYS_ERR_INT 0x04
461
462 #define DRIVER_VERSION "1.03"
463 static const char driver_name[] = "lpc32xx_udc";
464
465 /*
466 *
467 * proc interface support
468 *
469 */
470 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
471 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
472 static const char debug_filename[] = "driver/udc";
473
474 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
475 {
476 struct lpc32xx_request *req;
477
478 seq_printf(s, "\n");
479 seq_printf(s, "%12s, maxpacket %4d %3s",
480 ep->ep.name, ep->ep.maxpacket,
481 ep->is_in ? "in" : "out");
482 seq_printf(s, " type %4s", epnames[ep->eptype]);
483 seq_printf(s, " ints: %12d", ep->totalints);
484
485 if (list_empty(&ep->queue))
486 seq_printf(s, "\t(queue empty)\n");
487 else {
488 list_for_each_entry(req, &ep->queue, queue) {
489 u32 length = req->req.actual;
490
491 seq_printf(s, "\treq %p len %d/%d buf %p\n",
492 &req->req, length,
493 req->req.length, req->req.buf);
494 }
495 }
496 }
497
498 static int udc_show(struct seq_file *s, void *unused)
499 {
500 struct lpc32xx_udc *udc = s->private;
501 struct lpc32xx_ep *ep;
502 unsigned long flags;
503
504 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
505
506 spin_lock_irqsave(&udc->lock, flags);
507
508 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
509 udc->vbus ? "present" : "off",
510 udc->enabled ? (udc->vbus ? "active" : "enabled") :
511 "disabled",
512 udc->gadget.is_selfpowered ? "self" : "VBUS",
513 udc->suspended ? ", suspended" : "",
514 udc->driver ? udc->driver->driver.name : "(none)");
515
516 if (udc->enabled && udc->vbus) {
517 proc_ep_show(s, &udc->ep[0]);
518 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
519 proc_ep_show(s, ep);
520 }
521
522 spin_unlock_irqrestore(&udc->lock, flags);
523
524 return 0;
525 }
526
527 DEFINE_SHOW_ATTRIBUTE(udc);
528
529 static void create_debug_file(struct lpc32xx_udc *udc)
530 {
531 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &udc_fops);
532 }
533
534 static void remove_debug_file(struct lpc32xx_udc *udc)
535 {
536 debugfs_remove(udc->pde);
537 }
538
539 #else
540 static inline void create_debug_file(struct lpc32xx_udc *udc) {}
541 static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
542 #endif
543
544 /* Primary initialization sequence for the ISP1301 transceiver */
545 static void isp1301_udc_configure(struct lpc32xx_udc *udc)
546 {
547 u8 value;
548 s32 vendor, product;
549
550 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
551 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
552
553 if (vendor == 0x0483 && product == 0xa0c4)
554 udc->atx = STOTG04;
555
556 /* LPC32XX only supports DAT_SE0 USB mode */
557 /* This sequence is important */
558
559 /* Disable transparent UART mode first */
560 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
561 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
562 MC1_UART_EN);
563
564 /* Set full speed and SE0 mode */
565 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
566 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
567 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
568 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
569
570 /*
571 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
572 */
573 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
574 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
575
576 value = MC2_BI_DI;
577 if (udc->atx != STOTG04)
578 value |= MC2_SPD_SUSP_CTRL;
579 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
580 ISP1301_I2C_MODE_CONTROL_2, value);
581
582 /* Driver VBUS_DRV high or low depending on board setup */
583 if (udc->board->vbus_drv_pol != 0)
584 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
585 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
586 else
587 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
588 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
589 OTG1_VBUS_DRV);
590
591 /* Bi-directional mode with suspend control
592 * Enable both pulldowns for now - the pullup will be enable when VBUS
593 * is detected */
594 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
595 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
596 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
597 ISP1301_I2C_OTG_CONTROL_1,
598 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
599
600 /* Discharge VBUS (just in case) */
601 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
602 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
603 msleep(1);
604 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
605 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
606 OTG1_VBUS_DISCHRG);
607
608 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
609 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
610
611 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
612 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
613 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
614 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
615
616 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
617 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
618 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
619 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
620
621 }
622
623 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
624 static void isp1301_pullup_set(struct lpc32xx_udc *udc)
625 {
626 if (udc->pullup)
627 /* Enable pullup for bus signalling */
628 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
629 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
630 else
631 /* Enable pullup for bus signalling */
632 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
633 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
634 OTG1_DP_PULLUP);
635 }
636
637 static void pullup_work(struct work_struct *work)
638 {
639 struct lpc32xx_udc *udc =
640 container_of(work, struct lpc32xx_udc, pullup_job);
641
642 isp1301_pullup_set(udc);
643 }
644
645 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
646 int block)
647 {
648 if (en_pullup == udc->pullup)
649 return;
650
651 udc->pullup = en_pullup;
652 if (block)
653 isp1301_pullup_set(udc);
654 else
655 /* defer slow i2c pull up setting */
656 schedule_work(&udc->pullup_job);
657 }
658
659 #ifdef CONFIG_PM
660 /* Powers up or down the ISP1301 transceiver */
661 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
662 {
663 /* There is no "global power down" register for stotg04 */
664 if (udc->atx == STOTG04)
665 return;
666
667 if (enable != 0)
668 /* Power up ISP1301 - this ISP1301 will automatically wakeup
669 when VBUS is detected */
670 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
671 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
672 MC2_GLOBAL_PWR_DN);
673 else
674 /* Power down ISP1301 */
675 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
676 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
677 }
678
679 static void power_work(struct work_struct *work)
680 {
681 struct lpc32xx_udc *udc =
682 container_of(work, struct lpc32xx_udc, power_job);
683
684 isp1301_set_powerstate(udc, udc->poweron);
685 }
686 #endif
687
688 /*
689 *
690 * USB protocol engine command/data read/write helper functions
691 *
692 */
693 /* Issues a single command to the USB device state machine */
694 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
695 {
696 u32 pass = 0;
697 int to;
698
699 /* EP may lock on CLRI if this read isn't done */
700 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
701 (void) tmp;
702
703 while (pass == 0) {
704 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
705
706 /* Write command code */
707 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
708 to = 10000;
709 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
710 USBD_CCEMPTY) == 0) && (to > 0)) {
711 to--;
712 }
713
714 if (to > 0)
715 pass = 1;
716
717 cpu_relax();
718 }
719 }
720
721 /* Issues 2 commands (or command and data) to the USB device state machine */
722 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
723 u32 data)
724 {
725 udc_protocol_cmd_w(udc, cmd);
726 udc_protocol_cmd_w(udc, data);
727 }
728
729 /* Issues a single command to the USB device state machine and reads
730 * response data */
731 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
732 {
733 int to = 1000;
734
735 /* Write a command and read data from the protocol engine */
736 writel((USBD_CDFULL | USBD_CCEMPTY),
737 USBD_DEVINTCLR(udc->udp_baseaddr));
738
739 /* Write command code */
740 udc_protocol_cmd_w(udc, cmd);
741
742 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
743 && (to > 0))
744 to--;
745 if (!to)
746 dev_dbg(udc->dev,
747 "Protocol engine didn't receive response (CDFULL)\n");
748
749 return readl(USBD_CMDDATA(udc->udp_baseaddr));
750 }
751
752 /*
753 *
754 * USB device interrupt mask support functions
755 *
756 */
757 /* Enable one or more USB device interrupts */
758 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
759 {
760 udc->enabled_devints |= devmask;
761 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
762 }
763
764 /* Disable one or more USB device interrupts */
765 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
766 {
767 udc->enabled_devints &= ~mask;
768 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
769 }
770
771 /* Clear one or more USB device interrupts */
772 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
773 {
774 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
775 }
776
777 /*
778 *
779 * Endpoint interrupt disable/enable functions
780 *
781 */
782 /* Enable one or more USB endpoint interrupts */
783 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
784 {
785 udc->enabled_hwepints |= (1 << hwep);
786 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
787 }
788
789 /* Disable one or more USB endpoint interrupts */
790 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
791 {
792 udc->enabled_hwepints &= ~(1 << hwep);
793 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
794 }
795
796 /* Clear one or more USB endpoint interrupts */
797 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
798 {
799 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
800 }
801
802 /* Enable DMA for the HW channel */
803 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
804 {
805 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
806 }
807
808 /* Disable DMA for the HW channel */
809 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
810 {
811 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
812 }
813
814 /*
815 *
816 * Endpoint realize/unrealize functions
817 *
818 */
819 /* Before an endpoint can be used, it needs to be realized
820 * in the USB protocol engine - this realizes the endpoint.
821 * The interrupt (FIFO or DMA) is not enabled with this function */
822 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
823 u32 maxpacket)
824 {
825 int to = 1000;
826
827 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
828 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
829 udc->realized_eps |= (1 << hwep);
830 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
831 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
832
833 /* Wait until endpoint is realized in hardware */
834 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
835 USBD_EP_RLZED)) && (to > 0))
836 to--;
837 if (!to)
838 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
839
840 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
841 }
842
843 /* Unrealize an EP */
844 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
845 {
846 udc->realized_eps &= ~(1 << hwep);
847 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
848 }
849
850 /*
851 *
852 * Endpoint support functions
853 *
854 */
855 /* Select and clear endpoint interrupt */
856 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
857 {
858 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
859 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
860 }
861
862 /* Disables the endpoint in the USB protocol engine */
863 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
864 {
865 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
866 DAT_WR_BYTE(EP_STAT_DA));
867 }
868
869 /* Stalls the endpoint - endpoint will return STALL */
870 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
871 {
872 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
873 DAT_WR_BYTE(EP_STAT_ST));
874 }
875
876 /* Clear stall or reset endpoint */
877 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
878 {
879 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
880 DAT_WR_BYTE(0));
881 }
882
883 /* Select an endpoint for endpoint status, clear, validate */
884 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
885 {
886 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
887 }
888
889 /*
890 *
891 * Endpoint buffer management functions
892 *
893 */
894 /* Clear the current endpoint's buffer */
895 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
896 {
897 udc_select_hwep(udc, hwep);
898 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
899 }
900
901 /* Validate the current endpoint's buffer */
902 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
903 {
904 udc_select_hwep(udc, hwep);
905 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
906 }
907
908 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
909 {
910 /* Clear EP interrupt */
911 uda_clear_hwepint(udc, hwep);
912 return udc_selep_clrint(udc, hwep);
913 }
914
915 /*
916 *
917 * USB EP DMA support
918 *
919 */
920 /* Allocate a DMA Descriptor */
921 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
922 {
923 dma_addr_t dma;
924 struct lpc32xx_usbd_dd_gad *dd;
925
926 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
927 if (dd)
928 dd->this_dma = dma;
929
930 return dd;
931 }
932
933 /* Free a DMA Descriptor */
934 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
935 {
936 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
937 }
938
939 /*
940 *
941 * USB setup and shutdown functions
942 *
943 */
944 /* Enables or disables most of the USB system clocks when low power mode is
945 * needed. Clocks are typically started on a connection event, and disabled
946 * when a cable is disconnected */
947 static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
948 {
949 if (enable != 0) {
950 if (udc->clocked)
951 return;
952
953 udc->clocked = 1;
954 clk_prepare_enable(udc->usb_slv_clk);
955 } else {
956 if (!udc->clocked)
957 return;
958
959 udc->clocked = 0;
960 clk_disable_unprepare(udc->usb_slv_clk);
961 }
962 }
963
964 /* Set/reset USB device address */
965 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
966 {
967 /* Address will be latched at the end of the status phase, or
968 latched immediately if function is called twice */
969 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
970 DAT_WR_BYTE(DEV_EN | addr));
971 }
972
973 /* Setup up a IN request for DMA transfer - this consists of determining the
974 * list of DMA addresses for the transfer, allocating DMA Descriptors,
975 * installing the DD into the UDCA, and then enabling the DMA for that EP */
976 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
977 {
978 struct lpc32xx_request *req;
979 u32 hwep = ep->hwep_num;
980
981 ep->req_pending = 1;
982
983 /* There will always be a request waiting here */
984 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
985
986 /* Place the DD Descriptor into the UDCA */
987 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
988
989 /* Enable DMA and interrupt for the HW EP */
990 udc_ep_dma_enable(udc, hwep);
991
992 /* Clear ZLP if last packet is not of MAXP size */
993 if (req->req.length % ep->ep.maxpacket)
994 req->send_zlp = 0;
995
996 return 0;
997 }
998
999 /* Setup up a OUT request for DMA transfer - this consists of determining the
1000 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1001 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1002 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1003 {
1004 struct lpc32xx_request *req;
1005 u32 hwep = ep->hwep_num;
1006
1007 ep->req_pending = 1;
1008
1009 /* There will always be a request waiting here */
1010 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1011
1012 /* Place the DD Descriptor into the UDCA */
1013 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1014
1015 /* Enable DMA and interrupt for the HW EP */
1016 udc_ep_dma_enable(udc, hwep);
1017 return 0;
1018 }
1019
1020 static void udc_disable(struct lpc32xx_udc *udc)
1021 {
1022 u32 i;
1023
1024 /* Disable device */
1025 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1026 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1027
1028 /* Disable all device interrupts (including EP0) */
1029 uda_disable_devint(udc, 0x3FF);
1030
1031 /* Disable and reset all endpoint interrupts */
1032 for (i = 0; i < 32; i++) {
1033 uda_disable_hwepint(udc, i);
1034 uda_clear_hwepint(udc, i);
1035 udc_disable_hwep(udc, i);
1036 udc_unrealize_hwep(udc, i);
1037 udc->udca_v_base[i] = 0;
1038
1039 /* Disable and clear all interrupts and DMA */
1040 udc_ep_dma_disable(udc, i);
1041 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1042 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1043 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1044 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1045 }
1046
1047 /* Disable DMA interrupts */
1048 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1049
1050 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1051 }
1052
1053 static void udc_enable(struct lpc32xx_udc *udc)
1054 {
1055 u32 i;
1056 struct lpc32xx_ep *ep = &udc->ep[0];
1057
1058 /* Start with known state */
1059 udc_disable(udc);
1060
1061 /* Enable device */
1062 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1063
1064 /* EP interrupts on high priority, FRAME interrupt on low priority */
1065 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1066 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1067
1068 /* Clear any pending device interrupts */
1069 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1070
1071 /* Setup UDCA - not yet used (DMA) */
1072 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1073
1074 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1075 for (i = 0; i <= 1; i++) {
1076 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1077 uda_enable_hwepint(udc, i);
1078 udc_select_hwep(udc, i);
1079 udc_clrstall_hwep(udc, i);
1080 udc_clr_buffer_hwep(udc, i);
1081 }
1082
1083 /* Device interrupt setup */
1084 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1085 USBD_EP_FAST));
1086 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1087 USBD_EP_FAST));
1088
1089 /* Set device address to 0 - called twice to force a latch in the USB
1090 engine without the need of a setup packet status closure */
1091 udc_set_address(udc, 0);
1092 udc_set_address(udc, 0);
1093
1094 /* Enable master DMA interrupts */
1095 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1096 USBD_DMAINTEN(udc->udp_baseaddr));
1097
1098 udc->dev_status = 0;
1099 }
1100
1101 /*
1102 *
1103 * USB device board specific events handled via callbacks
1104 *
1105 */
1106 /* Connection change event - notify board function of change */
1107 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1108 {
1109 /* Just notify of a connection change event (optional) */
1110 if (udc->board->conn_chgb != NULL)
1111 udc->board->conn_chgb(conn);
1112 }
1113
1114 /* Suspend/resume event - notify board function of change */
1115 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1116 {
1117 /* Just notify of a Suspend/resume change event (optional) */
1118 if (udc->board->susp_chgb != NULL)
1119 udc->board->susp_chgb(conn);
1120
1121 if (conn)
1122 udc->suspended = 0;
1123 else
1124 udc->suspended = 1;
1125 }
1126
1127 /* Remote wakeup enable/disable - notify board function of change */
1128 static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1129 {
1130 if (udc->board->rmwk_chgb != NULL)
1131 udc->board->rmwk_chgb(udc->dev_status &
1132 (1 << USB_DEVICE_REMOTE_WAKEUP));
1133 }
1134
1135 /* Reads data from FIFO, adjusts for alignment and data size */
1136 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1137 {
1138 int n, i, bl;
1139 u16 *p16;
1140 u32 *p32, tmp, cbytes;
1141
1142 /* Use optimal data transfer method based on source address and size */
1143 switch (((uintptr_t) data) & 0x3) {
1144 case 0: /* 32-bit aligned */
1145 p32 = (u32 *) data;
1146 cbytes = (bytes & ~0x3);
1147
1148 /* Copy 32-bit aligned data first */
1149 for (n = 0; n < cbytes; n += 4)
1150 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1151
1152 /* Handle any remaining bytes */
1153 bl = bytes - cbytes;
1154 if (bl) {
1155 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1156 for (n = 0; n < bl; n++)
1157 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1158
1159 }
1160 break;
1161
1162 case 1: /* 8-bit aligned */
1163 case 3:
1164 /* Each byte has to be handled independently */
1165 for (n = 0; n < bytes; n += 4) {
1166 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1167
1168 bl = bytes - n;
1169 if (bl > 4)
1170 bl = 4;
1171
1172 for (i = 0; i < bl; i++)
1173 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1174 }
1175 break;
1176
1177 case 2: /* 16-bit aligned */
1178 p16 = (u16 *) data;
1179 cbytes = (bytes & ~0x3);
1180
1181 /* Copy 32-bit sized objects first with 16-bit alignment */
1182 for (n = 0; n < cbytes; n += 4) {
1183 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1184 *p16++ = (u16)(tmp & 0xFFFF);
1185 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1186 }
1187
1188 /* Handle any remaining bytes */
1189 bl = bytes - cbytes;
1190 if (bl) {
1191 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1192 for (n = 0; n < bl; n++)
1193 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1194 }
1195 break;
1196 }
1197 }
1198
1199 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1200 * as EP0) that don't use DMA. This function should only be called if a packet
1201 * is known to be ready to read for the endpoint. Note that the endpoint must
1202 * be selected in the protocol engine prior to this call. */
1203 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1204 u32 bytes)
1205 {
1206 u32 tmpv;
1207 int to = 1000;
1208 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1209
1210 /* Setup read of endpoint */
1211 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1212
1213 /* Wait until packet is ready */
1214 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1215 PKT_RDY) == 0) && (to > 0))
1216 to--;
1217 if (!to)
1218 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1219
1220 /* Mask out count */
1221 tmp = tmpv & PKT_LNGTH_MASK;
1222 if (bytes < tmp)
1223 tmp = bytes;
1224
1225 if ((tmp > 0) && (data != NULL))
1226 udc_pop_fifo(udc, (u8 *) data, tmp);
1227
1228 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1229
1230 /* Clear the buffer */
1231 udc_clr_buffer_hwep(udc, hwep);
1232
1233 return tmp;
1234 }
1235
1236 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1237 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1238 {
1239 int n, i, bl;
1240 u16 *p16;
1241 u32 *p32, tmp, cbytes;
1242
1243 /* Use optimal data transfer method based on source address and size */
1244 switch (((uintptr_t) data) & 0x3) {
1245 case 0: /* 32-bit aligned */
1246 p32 = (u32 *) data;
1247 cbytes = (bytes & ~0x3);
1248
1249 /* Copy 32-bit aligned data first */
1250 for (n = 0; n < cbytes; n += 4)
1251 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1252
1253 /* Handle any remaining bytes */
1254 bl = bytes - cbytes;
1255 if (bl) {
1256 tmp = 0;
1257 for (n = 0; n < bl; n++)
1258 tmp |= data[cbytes + n] << (n * 8);
1259
1260 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1261 }
1262 break;
1263
1264 case 1: /* 8-bit aligned */
1265 case 3:
1266 /* Each byte has to be handled independently */
1267 for (n = 0; n < bytes; n += 4) {
1268 bl = bytes - n;
1269 if (bl > 4)
1270 bl = 4;
1271
1272 tmp = 0;
1273 for (i = 0; i < bl; i++)
1274 tmp |= data[n + i] << (i * 8);
1275
1276 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1277 }
1278 break;
1279
1280 case 2: /* 16-bit aligned */
1281 p16 = (u16 *) data;
1282 cbytes = (bytes & ~0x3);
1283
1284 /* Copy 32-bit aligned data first */
1285 for (n = 0; n < cbytes; n += 4) {
1286 tmp = *p16++ & 0xFFFF;
1287 tmp |= (*p16++ & 0xFFFF) << 16;
1288 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1289 }
1290
1291 /* Handle any remaining bytes */
1292 bl = bytes - cbytes;
1293 if (bl) {
1294 tmp = 0;
1295 for (n = 0; n < bl; n++)
1296 tmp |= data[cbytes + n] << (n * 8);
1297
1298 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1299 }
1300 break;
1301 }
1302 }
1303
1304 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1305 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1306 * protocol engine prior to this call. */
1307 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1308 u32 bytes)
1309 {
1310 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1311
1312 if ((bytes > 0) && (data == NULL))
1313 return;
1314
1315 /* Setup write of endpoint */
1316 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1317
1318 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1319
1320 /* Need at least 1 byte to trigger TX */
1321 if (bytes == 0)
1322 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1323 else
1324 udc_stuff_fifo(udc, (u8 *) data, bytes);
1325
1326 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1327
1328 udc_val_buffer_hwep(udc, hwep);
1329 }
1330
1331 /* USB device reset - resets USB to a default state with just EP0
1332 enabled */
1333 static void uda_usb_reset(struct lpc32xx_udc *udc)
1334 {
1335 u32 i = 0;
1336 /* Re-init device controller and EP0 */
1337 udc_enable(udc);
1338 udc->gadget.speed = USB_SPEED_FULL;
1339
1340 for (i = 1; i < NUM_ENDPOINTS; i++) {
1341 struct lpc32xx_ep *ep = &udc->ep[i];
1342 ep->req_pending = 0;
1343 }
1344 }
1345
1346 /* Send a ZLP on EP0 */
1347 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1348 {
1349 udc_write_hwep(udc, EP_IN, NULL, 0);
1350 }
1351
1352 /* Get current frame number */
1353 static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1354 {
1355 u16 flo, fhi;
1356
1357 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1358 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1359 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1360
1361 return (fhi << 8) | flo;
1362 }
1363
1364 /* Set the device as configured - enables all endpoints */
1365 static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1366 {
1367 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1368 }
1369
1370 /* Set the device as unconfigured - disables all endpoints */
1371 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1372 {
1373 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1374 }
1375
1376 /* reinit == restore initial software state */
1377 static void udc_reinit(struct lpc32xx_udc *udc)
1378 {
1379 u32 i;
1380
1381 INIT_LIST_HEAD(&udc->gadget.ep_list);
1382 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1383
1384 for (i = 0; i < NUM_ENDPOINTS; i++) {
1385 struct lpc32xx_ep *ep = &udc->ep[i];
1386
1387 if (i != 0)
1388 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1389 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1390 INIT_LIST_HEAD(&ep->queue);
1391 ep->req_pending = 0;
1392 }
1393
1394 udc->ep0state = WAIT_FOR_SETUP;
1395 }
1396
1397 /* Must be called with lock */
1398 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1399 {
1400 struct lpc32xx_udc *udc = ep->udc;
1401
1402 list_del_init(&req->queue);
1403 if (req->req.status == -EINPROGRESS)
1404 req->req.status = status;
1405 else
1406 status = req->req.status;
1407
1408 if (ep->lep) {
1409 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1410
1411 /* Free DDs */
1412 udc_dd_free(udc, req->dd_desc_ptr);
1413 }
1414
1415 if (status && status != -ESHUTDOWN)
1416 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1417
1418 ep->req_pending = 0;
1419 spin_unlock(&udc->lock);
1420 usb_gadget_giveback_request(&ep->ep, &req->req);
1421 spin_lock(&udc->lock);
1422 }
1423
1424 /* Must be called with lock */
1425 static void nuke(struct lpc32xx_ep *ep, int status)
1426 {
1427 struct lpc32xx_request *req;
1428
1429 while (!list_empty(&ep->queue)) {
1430 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1431 done(ep, req, status);
1432 }
1433
1434 if (status == -ESHUTDOWN) {
1435 uda_disable_hwepint(ep->udc, ep->hwep_num);
1436 udc_disable_hwep(ep->udc, ep->hwep_num);
1437 }
1438 }
1439
1440 /* IN endpoint 0 transfer */
1441 static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1442 {
1443 struct lpc32xx_request *req;
1444 struct lpc32xx_ep *ep0 = &udc->ep[0];
1445 u32 tsend, ts = 0;
1446
1447 if (list_empty(&ep0->queue))
1448 /* Nothing to send */
1449 return 0;
1450 else
1451 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1452 queue);
1453
1454 tsend = ts = req->req.length - req->req.actual;
1455 if (ts == 0) {
1456 /* Send a ZLP */
1457 udc_ep0_send_zlp(udc);
1458 done(ep0, req, 0);
1459 return 1;
1460 } else if (ts > ep0->ep.maxpacket)
1461 ts = ep0->ep.maxpacket; /* Just send what we can */
1462
1463 /* Write data to the EP0 FIFO and start transfer */
1464 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1465
1466 /* Increment data pointer */
1467 req->req.actual += ts;
1468
1469 if (tsend >= ep0->ep.maxpacket)
1470 return 0; /* Stay in data transfer state */
1471
1472 /* Transfer request is complete */
1473 udc->ep0state = WAIT_FOR_SETUP;
1474 done(ep0, req, 0);
1475 return 1;
1476 }
1477
1478 /* OUT endpoint 0 transfer */
1479 static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1480 {
1481 struct lpc32xx_request *req;
1482 struct lpc32xx_ep *ep0 = &udc->ep[0];
1483 u32 tr, bufferspace;
1484
1485 if (list_empty(&ep0->queue))
1486 return 0;
1487 else
1488 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1489 queue);
1490
1491 if (req) {
1492 if (req->req.length == 0) {
1493 /* Just dequeue request */
1494 done(ep0, req, 0);
1495 udc->ep0state = WAIT_FOR_SETUP;
1496 return 1;
1497 }
1498
1499 /* Get data from FIFO */
1500 bufferspace = req->req.length - req->req.actual;
1501 if (bufferspace > ep0->ep.maxpacket)
1502 bufferspace = ep0->ep.maxpacket;
1503
1504 /* Copy data to buffer */
1505 prefetchw(req->req.buf + req->req.actual);
1506 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1507 bufferspace);
1508 req->req.actual += bufferspace;
1509
1510 if (tr < ep0->ep.maxpacket) {
1511 /* This is the last packet */
1512 done(ep0, req, 0);
1513 udc->ep0state = WAIT_FOR_SETUP;
1514 return 1;
1515 }
1516 }
1517
1518 return 0;
1519 }
1520
1521 /* Must be called with lock */
1522 static void stop_activity(struct lpc32xx_udc *udc)
1523 {
1524 struct usb_gadget_driver *driver = udc->driver;
1525 int i;
1526
1527 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1528 driver = NULL;
1529
1530 udc->gadget.speed = USB_SPEED_UNKNOWN;
1531 udc->suspended = 0;
1532
1533 for (i = 0; i < NUM_ENDPOINTS; i++) {
1534 struct lpc32xx_ep *ep = &udc->ep[i];
1535 nuke(ep, -ESHUTDOWN);
1536 }
1537 if (driver) {
1538 spin_unlock(&udc->lock);
1539 driver->disconnect(&udc->gadget);
1540 spin_lock(&udc->lock);
1541 }
1542
1543 isp1301_pullup_enable(udc, 0, 0);
1544 udc_disable(udc);
1545 udc_reinit(udc);
1546 }
1547
1548 /*
1549 * Activate or kill host pullup
1550 * Can be called with or without lock
1551 */
1552 static void pullup(struct lpc32xx_udc *udc, int is_on)
1553 {
1554 if (!udc->clocked)
1555 return;
1556
1557 if (!udc->enabled || !udc->vbus)
1558 is_on = 0;
1559
1560 if (is_on != udc->pullup)
1561 isp1301_pullup_enable(udc, is_on, 0);
1562 }
1563
1564 /* Must be called without lock */
1565 static int lpc32xx_ep_disable(struct usb_ep *_ep)
1566 {
1567 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1568 struct lpc32xx_udc *udc = ep->udc;
1569 unsigned long flags;
1570
1571 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1572 return -EINVAL;
1573 spin_lock_irqsave(&udc->lock, flags);
1574
1575 nuke(ep, -ESHUTDOWN);
1576
1577 /* Clear all DMA statuses for this EP */
1578 udc_ep_dma_disable(udc, ep->hwep_num);
1579 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1580 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1581 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1582 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1583
1584 /* Remove the DD pointer in the UDCA */
1585 udc->udca_v_base[ep->hwep_num] = 0;
1586
1587 /* Disable and reset endpoint and interrupt */
1588 uda_clear_hwepint(udc, ep->hwep_num);
1589 udc_unrealize_hwep(udc, ep->hwep_num);
1590
1591 ep->hwep_num = 0;
1592
1593 spin_unlock_irqrestore(&udc->lock, flags);
1594
1595 atomic_dec(&udc->enabled_ep_cnt);
1596 wake_up(&udc->ep_disable_wait_queue);
1597
1598 return 0;
1599 }
1600
1601 /* Must be called without lock */
1602 static int lpc32xx_ep_enable(struct usb_ep *_ep,
1603 const struct usb_endpoint_descriptor *desc)
1604 {
1605 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1606 struct lpc32xx_udc *udc;
1607 u16 maxpacket;
1608 u32 tmp;
1609 unsigned long flags;
1610
1611 /* Verify EP data */
1612 if ((!_ep) || (!ep) || (!desc) ||
1613 (desc->bDescriptorType != USB_DT_ENDPOINT))
1614 return -EINVAL;
1615
1616 udc = ep->udc;
1617 maxpacket = usb_endpoint_maxp(desc);
1618 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1619 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1620 return -EINVAL;
1621 }
1622
1623 /* Don't touch EP0 */
1624 if (ep->hwep_num_base == 0) {
1625 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1626 return -EINVAL;
1627 }
1628
1629 /* Is driver ready? */
1630 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1631 dev_dbg(udc->dev, "bogus device state\n");
1632 return -ESHUTDOWN;
1633 }
1634
1635 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1636 switch (tmp) {
1637 case USB_ENDPOINT_XFER_CONTROL:
1638 return -EINVAL;
1639
1640 case USB_ENDPOINT_XFER_INT:
1641 if (maxpacket > ep->maxpacket) {
1642 dev_dbg(udc->dev,
1643 "Bad INT endpoint maxpacket %d\n", maxpacket);
1644 return -EINVAL;
1645 }
1646 break;
1647
1648 case USB_ENDPOINT_XFER_BULK:
1649 switch (maxpacket) {
1650 case 8:
1651 case 16:
1652 case 32:
1653 case 64:
1654 break;
1655
1656 default:
1657 dev_dbg(udc->dev,
1658 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1659 return -EINVAL;
1660 }
1661 break;
1662
1663 case USB_ENDPOINT_XFER_ISOC:
1664 break;
1665 }
1666 spin_lock_irqsave(&udc->lock, flags);
1667
1668 /* Initialize endpoint to match the selected descriptor */
1669 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1670 ep->ep.maxpacket = maxpacket;
1671
1672 /* Map hardware endpoint from base and direction */
1673 if (ep->is_in)
1674 /* IN endpoints are offset 1 from the OUT endpoint */
1675 ep->hwep_num = ep->hwep_num_base + EP_IN;
1676 else
1677 ep->hwep_num = ep->hwep_num_base;
1678
1679 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1680 ep->hwep_num, maxpacket, (ep->is_in == 1));
1681
1682 /* Realize the endpoint, interrupt is enabled later when
1683 * buffers are queued, IN EPs will NAK until buffers are ready */
1684 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1685 udc_clr_buffer_hwep(udc, ep->hwep_num);
1686 uda_disable_hwepint(udc, ep->hwep_num);
1687 udc_clrstall_hwep(udc, ep->hwep_num);
1688
1689 /* Clear all DMA statuses for this EP */
1690 udc_ep_dma_disable(udc, ep->hwep_num);
1691 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1692 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1693 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1694 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1695
1696 spin_unlock_irqrestore(&udc->lock, flags);
1697
1698 atomic_inc(&udc->enabled_ep_cnt);
1699 return 0;
1700 }
1701
1702 /*
1703 * Allocate a USB request list
1704 * Can be called with or without lock
1705 */
1706 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1707 gfp_t gfp_flags)
1708 {
1709 struct lpc32xx_request *req;
1710
1711 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1712 if (!req)
1713 return NULL;
1714
1715 INIT_LIST_HEAD(&req->queue);
1716 return &req->req;
1717 }
1718
1719 /*
1720 * De-allocate a USB request list
1721 * Can be called with or without lock
1722 */
1723 static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1724 struct usb_request *_req)
1725 {
1726 struct lpc32xx_request *req;
1727
1728 req = container_of(_req, struct lpc32xx_request, req);
1729 BUG_ON(!list_empty(&req->queue));
1730 kfree(req);
1731 }
1732
1733 /* Must be called without lock */
1734 static int lpc32xx_ep_queue(struct usb_ep *_ep,
1735 struct usb_request *_req, gfp_t gfp_flags)
1736 {
1737 struct lpc32xx_request *req;
1738 struct lpc32xx_ep *ep;
1739 struct lpc32xx_udc *udc;
1740 unsigned long flags;
1741 int status = 0;
1742
1743 req = container_of(_req, struct lpc32xx_request, req);
1744 ep = container_of(_ep, struct lpc32xx_ep, ep);
1745
1746 if (!_ep || !_req || !_req->complete || !_req->buf ||
1747 !list_empty(&req->queue))
1748 return -EINVAL;
1749
1750 udc = ep->udc;
1751
1752 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1753 return -EPIPE;
1754
1755 if (ep->lep) {
1756 struct lpc32xx_usbd_dd_gad *dd;
1757
1758 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1759 if (status)
1760 return status;
1761
1762 /* For the request, build a list of DDs */
1763 dd = udc_dd_alloc(udc);
1764 if (!dd) {
1765 /* Error allocating DD */
1766 return -ENOMEM;
1767 }
1768 req->dd_desc_ptr = dd;
1769
1770 /* Setup the DMA descriptor */
1771 dd->dd_next_phy = dd->dd_next_v = 0;
1772 dd->dd_buffer_addr = req->req.dma;
1773 dd->dd_status = 0;
1774
1775 /* Special handling for ISO EPs */
1776 if (ep->eptype == EP_ISO_TYPE) {
1777 dd->dd_setup = DD_SETUP_ISO_EP |
1778 DD_SETUP_PACKETLEN(0) |
1779 DD_SETUP_DMALENBYTES(1);
1780 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1781 if (ep->is_in)
1782 dd->iso_status[0] = req->req.length;
1783 else
1784 dd->iso_status[0] = 0;
1785 } else
1786 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1787 DD_SETUP_DMALENBYTES(req->req.length);
1788 }
1789
1790 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1791 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1792
1793 spin_lock_irqsave(&udc->lock, flags);
1794
1795 _req->status = -EINPROGRESS;
1796 _req->actual = 0;
1797 req->send_zlp = _req->zero;
1798
1799 /* Kickstart empty queues */
1800 if (list_empty(&ep->queue)) {
1801 list_add_tail(&req->queue, &ep->queue);
1802
1803 if (ep->hwep_num_base == 0) {
1804 /* Handle expected data direction */
1805 if (ep->is_in) {
1806 /* IN packet to host */
1807 udc->ep0state = DATA_IN;
1808 status = udc_ep0_in_req(udc);
1809 } else {
1810 /* OUT packet from host */
1811 udc->ep0state = DATA_OUT;
1812 status = udc_ep0_out_req(udc);
1813 }
1814 } else if (ep->is_in) {
1815 /* IN packet to host and kick off transfer */
1816 if (!ep->req_pending)
1817 udc_ep_in_req_dma(udc, ep);
1818 } else
1819 /* OUT packet from host and kick off list */
1820 if (!ep->req_pending)
1821 udc_ep_out_req_dma(udc, ep);
1822 } else
1823 list_add_tail(&req->queue, &ep->queue);
1824
1825 spin_unlock_irqrestore(&udc->lock, flags);
1826
1827 return (status < 0) ? status : 0;
1828 }
1829
1830 /* Must be called without lock */
1831 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1832 {
1833 struct lpc32xx_ep *ep;
1834 struct lpc32xx_request *req;
1835 unsigned long flags;
1836
1837 ep = container_of(_ep, struct lpc32xx_ep, ep);
1838 if (!_ep || ep->hwep_num_base == 0)
1839 return -EINVAL;
1840
1841 spin_lock_irqsave(&ep->udc->lock, flags);
1842
1843 /* make sure it's actually queued on this endpoint */
1844 list_for_each_entry(req, &ep->queue, queue) {
1845 if (&req->req == _req)
1846 break;
1847 }
1848 if (&req->req != _req) {
1849 spin_unlock_irqrestore(&ep->udc->lock, flags);
1850 return -EINVAL;
1851 }
1852
1853 done(ep, req, -ECONNRESET);
1854
1855 spin_unlock_irqrestore(&ep->udc->lock, flags);
1856
1857 return 0;
1858 }
1859
1860 /* Must be called without lock */
1861 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1862 {
1863 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1864 struct lpc32xx_udc *udc;
1865 unsigned long flags;
1866
1867 if ((!ep) || (ep->hwep_num <= 1))
1868 return -EINVAL;
1869
1870 /* Don't halt an IN EP */
1871 if (ep->is_in)
1872 return -EAGAIN;
1873
1874 udc = ep->udc;
1875 spin_lock_irqsave(&udc->lock, flags);
1876
1877 if (value == 1) {
1878 /* stall */
1879 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1880 DAT_WR_BYTE(EP_STAT_ST));
1881 } else {
1882 /* End stall */
1883 ep->wedge = 0;
1884 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1885 DAT_WR_BYTE(0));
1886 }
1887
1888 spin_unlock_irqrestore(&udc->lock, flags);
1889
1890 return 0;
1891 }
1892
1893 /* set the halt feature and ignores clear requests */
1894 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1895 {
1896 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1897
1898 if (!_ep || !ep->udc)
1899 return -EINVAL;
1900
1901 ep->wedge = 1;
1902
1903 return usb_ep_set_halt(_ep);
1904 }
1905
1906 static const struct usb_ep_ops lpc32xx_ep_ops = {
1907 .enable = lpc32xx_ep_enable,
1908 .disable = lpc32xx_ep_disable,
1909 .alloc_request = lpc32xx_ep_alloc_request,
1910 .free_request = lpc32xx_ep_free_request,
1911 .queue = lpc32xx_ep_queue,
1912 .dequeue = lpc32xx_ep_dequeue,
1913 .set_halt = lpc32xx_ep_set_halt,
1914 .set_wedge = lpc32xx_ep_set_wedge,
1915 };
1916
1917 /* Send a ZLP on a non-0 IN EP */
1918 static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1919 {
1920 /* Clear EP status */
1921 udc_clearep_getsts(udc, ep->hwep_num);
1922
1923 /* Send ZLP via FIFO mechanism */
1924 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1925 }
1926
1927 /*
1928 * Handle EP completion for ZLP
1929 * This function will only be called when a delayed ZLP needs to be sent out
1930 * after a DMA transfer has filled both buffers.
1931 */
1932 static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1933 {
1934 u32 epstatus;
1935 struct lpc32xx_request *req;
1936
1937 if (ep->hwep_num <= 0)
1938 return;
1939
1940 uda_clear_hwepint(udc, ep->hwep_num);
1941
1942 /* If this interrupt isn't enabled, return now */
1943 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1944 return;
1945
1946 /* Get endpoint status */
1947 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1948
1949 /*
1950 * This should never happen, but protect against writing to the
1951 * buffer when full.
1952 */
1953 if (epstatus & EP_SEL_F)
1954 return;
1955
1956 if (ep->is_in) {
1957 udc_send_in_zlp(udc, ep);
1958 uda_disable_hwepint(udc, ep->hwep_num);
1959 } else
1960 return;
1961
1962 /* If there isn't a request waiting, something went wrong */
1963 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1964 if (req) {
1965 done(ep, req, 0);
1966
1967 /* Start another request if ready */
1968 if (!list_empty(&ep->queue)) {
1969 if (ep->is_in)
1970 udc_ep_in_req_dma(udc, ep);
1971 else
1972 udc_ep_out_req_dma(udc, ep);
1973 } else
1974 ep->req_pending = 0;
1975 }
1976 }
1977
1978
1979 /* DMA end of transfer completion */
1980 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1981 {
1982 u32 status;
1983 struct lpc32xx_request *req;
1984 struct lpc32xx_usbd_dd_gad *dd;
1985
1986 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1987 ep->totalints++;
1988 #endif
1989
1990 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1991 if (!req) {
1992 ep_err(ep, "DMA interrupt on no req!\n");
1993 return;
1994 }
1995 dd = req->dd_desc_ptr;
1996
1997 /* DMA descriptor should always be retired for this call */
1998 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
1999 ep_warn(ep, "DMA descriptor did not retire\n");
2000
2001 /* Disable DMA */
2002 udc_ep_dma_disable(udc, ep->hwep_num);
2003 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2004 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2005
2006 /* System error? */
2007 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2008 (1 << ep->hwep_num)) {
2009 writel((1 << ep->hwep_num),
2010 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2011 ep_err(ep, "AHB critical error!\n");
2012 ep->req_pending = 0;
2013
2014 /* The error could have occurred on a packet of a multipacket
2015 * transfer, so recovering the transfer is not possible. Close
2016 * the request with an error */
2017 done(ep, req, -ECONNABORTED);
2018 return;
2019 }
2020
2021 /* Handle the current DD's status */
2022 status = dd->dd_status;
2023 switch (status & DD_STATUS_STS_MASK) {
2024 case DD_STATUS_STS_NS:
2025 /* DD not serviced? This shouldn't happen! */
2026 ep->req_pending = 0;
2027 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2028 status);
2029
2030 done(ep, req, -ECONNABORTED);
2031 return;
2032
2033 case DD_STATUS_STS_BS:
2034 /* Interrupt only fires on EOT - This shouldn't happen! */
2035 ep->req_pending = 0;
2036 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2037 status);
2038 done(ep, req, -ECONNABORTED);
2039 return;
2040
2041 case DD_STATUS_STS_NC:
2042 case DD_STATUS_STS_DUR:
2043 /* Really just a short packet, not an underrun */
2044 /* This is a good status and what we expect */
2045 break;
2046
2047 default:
2048 /* Data overrun, system error, or unknown */
2049 ep->req_pending = 0;
2050 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2051 status);
2052 done(ep, req, -ECONNABORTED);
2053 return;
2054 }
2055
2056 /* ISO endpoints are handled differently */
2057 if (ep->eptype == EP_ISO_TYPE) {
2058 if (ep->is_in)
2059 req->req.actual = req->req.length;
2060 else
2061 req->req.actual = dd->iso_status[0] & 0xFFFF;
2062 } else
2063 req->req.actual += DD_STATUS_CURDMACNT(status);
2064
2065 /* Send a ZLP if necessary. This will be done for non-int
2066 * packets which have a size that is a divisor of MAXP */
2067 if (req->send_zlp) {
2068 /*
2069 * If at least 1 buffer is available, send the ZLP now.
2070 * Otherwise, the ZLP send needs to be deferred until a
2071 * buffer is available.
2072 */
2073 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2074 udc_clearep_getsts(udc, ep->hwep_num);
2075 uda_enable_hwepint(udc, ep->hwep_num);
2076 udc_clearep_getsts(udc, ep->hwep_num);
2077
2078 /* Let the EP interrupt handle the ZLP */
2079 return;
2080 } else
2081 udc_send_in_zlp(udc, ep);
2082 }
2083
2084 /* Transfer request is complete */
2085 done(ep, req, 0);
2086
2087 /* Start another request if ready */
2088 udc_clearep_getsts(udc, ep->hwep_num);
2089 if (!list_empty((&ep->queue))) {
2090 if (ep->is_in)
2091 udc_ep_in_req_dma(udc, ep);
2092 else
2093 udc_ep_out_req_dma(udc, ep);
2094 } else
2095 ep->req_pending = 0;
2096
2097 }
2098
2099 /*
2100 *
2101 * Endpoint 0 functions
2102 *
2103 */
2104 static void udc_handle_dev(struct lpc32xx_udc *udc)
2105 {
2106 u32 tmp;
2107
2108 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2109 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2110
2111 if (tmp & DEV_RST)
2112 uda_usb_reset(udc);
2113 else if (tmp & DEV_CON_CH)
2114 uda_power_event(udc, (tmp & DEV_CON));
2115 else if (tmp & DEV_SUS_CH) {
2116 if (tmp & DEV_SUS) {
2117 if (udc->vbus == 0)
2118 stop_activity(udc);
2119 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2120 udc->driver) {
2121 /* Power down transceiver */
2122 udc->poweron = 0;
2123 schedule_work(&udc->pullup_job);
2124 uda_resm_susp_event(udc, 1);
2125 }
2126 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2127 udc->driver && udc->vbus) {
2128 uda_resm_susp_event(udc, 0);
2129 /* Power up transceiver */
2130 udc->poweron = 1;
2131 schedule_work(&udc->pullup_job);
2132 }
2133 }
2134 }
2135
2136 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2137 {
2138 struct lpc32xx_ep *ep;
2139 u32 ep0buff = 0, tmp;
2140
2141 switch (reqtype & USB_RECIP_MASK) {
2142 case USB_RECIP_INTERFACE:
2143 break; /* Not supported */
2144
2145 case USB_RECIP_DEVICE:
2146 ep0buff = udc->gadget.is_selfpowered;
2147 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2148 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2149 break;
2150
2151 case USB_RECIP_ENDPOINT:
2152 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2153 ep = &udc->ep[tmp];
2154 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2155 return -EOPNOTSUPP;
2156
2157 if (wIndex & USB_DIR_IN) {
2158 if (!ep->is_in)
2159 return -EOPNOTSUPP; /* Something's wrong */
2160 } else if (ep->is_in)
2161 return -EOPNOTSUPP; /* Not an IN endpoint */
2162
2163 /* Get status of the endpoint */
2164 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2165 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2166
2167 if (tmp & EP_SEL_ST)
2168 ep0buff = (1 << USB_ENDPOINT_HALT);
2169 else
2170 ep0buff = 0;
2171 break;
2172
2173 default:
2174 break;
2175 }
2176
2177 /* Return data */
2178 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2179
2180 return 0;
2181 }
2182
2183 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2184 {
2185 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2186 struct usb_ctrlrequest ctrlpkt;
2187 int i, bytes;
2188 u16 wIndex, wValue, reqtype, req, tmp;
2189
2190 /* Nuke previous transfers */
2191 nuke(ep0, -EPROTO);
2192
2193 /* Get setup packet */
2194 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2195 if (bytes != 8) {
2196 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2197 bytes);
2198 return;
2199 }
2200
2201 /* Native endianness */
2202 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2203 wValue = le16_to_cpu(ctrlpkt.wValue);
2204 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2205
2206 /* Set direction of EP0 */
2207 if (likely(reqtype & USB_DIR_IN))
2208 ep0->is_in = 1;
2209 else
2210 ep0->is_in = 0;
2211
2212 /* Handle SETUP packet */
2213 req = le16_to_cpu(ctrlpkt.bRequest);
2214 switch (req) {
2215 case USB_REQ_CLEAR_FEATURE:
2216 case USB_REQ_SET_FEATURE:
2217 switch (reqtype) {
2218 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2219 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2220 goto stall; /* Nothing else handled */
2221
2222 /* Tell board about event */
2223 if (req == USB_REQ_CLEAR_FEATURE)
2224 udc->dev_status &=
2225 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2226 else
2227 udc->dev_status |=
2228 (1 << USB_DEVICE_REMOTE_WAKEUP);
2229 uda_remwkp_cgh(udc);
2230 goto zlp_send;
2231
2232 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2233 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2234 if ((wValue != USB_ENDPOINT_HALT) ||
2235 (tmp >= NUM_ENDPOINTS))
2236 break;
2237
2238 /* Find hardware endpoint from logical endpoint */
2239 ep = &udc->ep[tmp];
2240 tmp = ep->hwep_num;
2241 if (tmp == 0)
2242 break;
2243
2244 if (req == USB_REQ_SET_FEATURE)
2245 udc_stall_hwep(udc, tmp);
2246 else if (!ep->wedge)
2247 udc_clrstall_hwep(udc, tmp);
2248
2249 goto zlp_send;
2250
2251 default:
2252 break;
2253 }
2254 break;
2255
2256 case USB_REQ_SET_ADDRESS:
2257 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2258 udc_set_address(udc, wValue);
2259 goto zlp_send;
2260 }
2261 break;
2262
2263 case USB_REQ_GET_STATUS:
2264 udc_get_status(udc, reqtype, wIndex);
2265 return;
2266
2267 default:
2268 break; /* Let GadgetFS handle the descriptor instead */
2269 }
2270
2271 if (likely(udc->driver)) {
2272 /* device-2-host (IN) or no data setup command, process
2273 * immediately */
2274 spin_unlock(&udc->lock);
2275 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2276
2277 spin_lock(&udc->lock);
2278 if (req == USB_REQ_SET_CONFIGURATION) {
2279 /* Configuration is set after endpoints are realized */
2280 if (wValue) {
2281 /* Set configuration */
2282 udc_set_device_configured(udc);
2283
2284 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2285 DAT_WR_BYTE(AP_CLK |
2286 INAK_BI | INAK_II));
2287 } else {
2288 /* Clear configuration */
2289 udc_set_device_unconfigured(udc);
2290
2291 /* Disable NAK interrupts */
2292 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2293 DAT_WR_BYTE(AP_CLK));
2294 }
2295 }
2296
2297 if (i < 0) {
2298 /* setup processing failed, force stall */
2299 dev_dbg(udc->dev,
2300 "req %02x.%02x protocol STALL; stat %d\n",
2301 reqtype, req, i);
2302 udc->ep0state = WAIT_FOR_SETUP;
2303 goto stall;
2304 }
2305 }
2306
2307 if (!ep0->is_in)
2308 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2309
2310 return;
2311
2312 stall:
2313 udc_stall_hwep(udc, EP_IN);
2314 return;
2315
2316 zlp_send:
2317 udc_ep0_send_zlp(udc);
2318 return;
2319 }
2320
2321 /* IN endpoint 0 transfer */
2322 static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2323 {
2324 struct lpc32xx_ep *ep0 = &udc->ep[0];
2325 u32 epstatus;
2326
2327 /* Clear EP interrupt */
2328 epstatus = udc_clearep_getsts(udc, EP_IN);
2329
2330 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2331 ep0->totalints++;
2332 #endif
2333
2334 /* Stalled? Clear stall and reset buffers */
2335 if (epstatus & EP_SEL_ST) {
2336 udc_clrstall_hwep(udc, EP_IN);
2337 nuke(ep0, -ECONNABORTED);
2338 udc->ep0state = WAIT_FOR_SETUP;
2339 return;
2340 }
2341
2342 /* Is a buffer available? */
2343 if (!(epstatus & EP_SEL_F)) {
2344 /* Handle based on current state */
2345 if (udc->ep0state == DATA_IN)
2346 udc_ep0_in_req(udc);
2347 else {
2348 /* Unknown state for EP0 oe end of DATA IN phase */
2349 nuke(ep0, -ECONNABORTED);
2350 udc->ep0state = WAIT_FOR_SETUP;
2351 }
2352 }
2353 }
2354
2355 /* OUT endpoint 0 transfer */
2356 static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2357 {
2358 struct lpc32xx_ep *ep0 = &udc->ep[0];
2359 u32 epstatus;
2360
2361 /* Clear EP interrupt */
2362 epstatus = udc_clearep_getsts(udc, EP_OUT);
2363
2364
2365 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2366 ep0->totalints++;
2367 #endif
2368
2369 /* Stalled? */
2370 if (epstatus & EP_SEL_ST) {
2371 udc_clrstall_hwep(udc, EP_OUT);
2372 nuke(ep0, -ECONNABORTED);
2373 udc->ep0state = WAIT_FOR_SETUP;
2374 return;
2375 }
2376
2377 /* A NAK may occur if a packet couldn't be received yet */
2378 if (epstatus & EP_SEL_EPN)
2379 return;
2380 /* Setup packet incoming? */
2381 if (epstatus & EP_SEL_STP) {
2382 nuke(ep0, 0);
2383 udc->ep0state = WAIT_FOR_SETUP;
2384 }
2385
2386 /* Data available? */
2387 if (epstatus & EP_SEL_F)
2388 /* Handle based on current state */
2389 switch (udc->ep0state) {
2390 case WAIT_FOR_SETUP:
2391 udc_handle_ep0_setup(udc);
2392 break;
2393
2394 case DATA_OUT:
2395 udc_ep0_out_req(udc);
2396 break;
2397
2398 default:
2399 /* Unknown state for EP0 */
2400 nuke(ep0, -ECONNABORTED);
2401 udc->ep0state = WAIT_FOR_SETUP;
2402 }
2403 }
2404
2405 /* Must be called without lock */
2406 static int lpc32xx_get_frame(struct usb_gadget *gadget)
2407 {
2408 int frame;
2409 unsigned long flags;
2410 struct lpc32xx_udc *udc = to_udc(gadget);
2411
2412 if (!udc->clocked)
2413 return -EINVAL;
2414
2415 spin_lock_irqsave(&udc->lock, flags);
2416
2417 frame = (int) udc_get_current_frame(udc);
2418
2419 spin_unlock_irqrestore(&udc->lock, flags);
2420
2421 return frame;
2422 }
2423
2424 static int lpc32xx_wakeup(struct usb_gadget *gadget)
2425 {
2426 return -ENOTSUPP;
2427 }
2428
2429 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2430 {
2431 gadget->is_selfpowered = (is_on != 0);
2432
2433 return 0;
2434 }
2435
2436 /*
2437 * vbus is here! turn everything on that's ready
2438 * Must be called without lock
2439 */
2440 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2441 {
2442 unsigned long flags;
2443 struct lpc32xx_udc *udc = to_udc(gadget);
2444
2445 spin_lock_irqsave(&udc->lock, flags);
2446
2447 /* Doesn't need lock */
2448 if (udc->driver) {
2449 udc_clk_set(udc, 1);
2450 udc_enable(udc);
2451 pullup(udc, is_active);
2452 } else {
2453 stop_activity(udc);
2454 pullup(udc, 0);
2455
2456 spin_unlock_irqrestore(&udc->lock, flags);
2457 /*
2458 * Wait for all the endpoints to disable,
2459 * before disabling clocks. Don't wait if
2460 * endpoints are not enabled.
2461 */
2462 if (atomic_read(&udc->enabled_ep_cnt))
2463 wait_event_interruptible(udc->ep_disable_wait_queue,
2464 (atomic_read(&udc->enabled_ep_cnt) == 0));
2465
2466 spin_lock_irqsave(&udc->lock, flags);
2467
2468 udc_clk_set(udc, 0);
2469 }
2470
2471 spin_unlock_irqrestore(&udc->lock, flags);
2472
2473 return 0;
2474 }
2475
2476 /* Can be called with or without lock */
2477 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2478 {
2479 struct lpc32xx_udc *udc = to_udc(gadget);
2480
2481 /* Doesn't need lock */
2482 pullup(udc, is_on);
2483
2484 return 0;
2485 }
2486
2487 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2488 static int lpc32xx_stop(struct usb_gadget *);
2489
2490 static const struct usb_gadget_ops lpc32xx_udc_ops = {
2491 .get_frame = lpc32xx_get_frame,
2492 .wakeup = lpc32xx_wakeup,
2493 .set_selfpowered = lpc32xx_set_selfpowered,
2494 .vbus_session = lpc32xx_vbus_session,
2495 .pullup = lpc32xx_pullup,
2496 .udc_start = lpc32xx_start,
2497 .udc_stop = lpc32xx_stop,
2498 };
2499
2500 static void nop_release(struct device *dev)
2501 {
2502 /* nothing to free */
2503 }
2504
2505 static const struct lpc32xx_udc controller_template = {
2506 .gadget = {
2507 .ops = &lpc32xx_udc_ops,
2508 .name = driver_name,
2509 .dev = {
2510 .init_name = "gadget",
2511 .release = nop_release,
2512 }
2513 },
2514 .ep[0] = {
2515 .ep = {
2516 .name = "ep0",
2517 .ops = &lpc32xx_ep_ops,
2518 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2519 USB_EP_CAPS_DIR_ALL),
2520 },
2521 .maxpacket = 64,
2522 .hwep_num_base = 0,
2523 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2524 .lep = 0,
2525 .eptype = EP_CTL_TYPE,
2526 },
2527 .ep[1] = {
2528 .ep = {
2529 .name = "ep1-int",
2530 .ops = &lpc32xx_ep_ops,
2531 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2532 USB_EP_CAPS_DIR_ALL),
2533 },
2534 .maxpacket = 64,
2535 .hwep_num_base = 2,
2536 .hwep_num = 0, /* 2 or 3, will be set later */
2537 .lep = 1,
2538 .eptype = EP_INT_TYPE,
2539 },
2540 .ep[2] = {
2541 .ep = {
2542 .name = "ep2-bulk",
2543 .ops = &lpc32xx_ep_ops,
2544 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2545 USB_EP_CAPS_DIR_ALL),
2546 },
2547 .maxpacket = 64,
2548 .hwep_num_base = 4,
2549 .hwep_num = 0, /* 4 or 5, will be set later */
2550 .lep = 2,
2551 .eptype = EP_BLK_TYPE,
2552 },
2553 .ep[3] = {
2554 .ep = {
2555 .name = "ep3-iso",
2556 .ops = &lpc32xx_ep_ops,
2557 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2558 USB_EP_CAPS_DIR_ALL),
2559 },
2560 .maxpacket = 1023,
2561 .hwep_num_base = 6,
2562 .hwep_num = 0, /* 6 or 7, will be set later */
2563 .lep = 3,
2564 .eptype = EP_ISO_TYPE,
2565 },
2566 .ep[4] = {
2567 .ep = {
2568 .name = "ep4-int",
2569 .ops = &lpc32xx_ep_ops,
2570 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2571 USB_EP_CAPS_DIR_ALL),
2572 },
2573 .maxpacket = 64,
2574 .hwep_num_base = 8,
2575 .hwep_num = 0, /* 8 or 9, will be set later */
2576 .lep = 4,
2577 .eptype = EP_INT_TYPE,
2578 },
2579 .ep[5] = {
2580 .ep = {
2581 .name = "ep5-bulk",
2582 .ops = &lpc32xx_ep_ops,
2583 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2584 USB_EP_CAPS_DIR_ALL),
2585 },
2586 .maxpacket = 64,
2587 .hwep_num_base = 10,
2588 .hwep_num = 0, /* 10 or 11, will be set later */
2589 .lep = 5,
2590 .eptype = EP_BLK_TYPE,
2591 },
2592 .ep[6] = {
2593 .ep = {
2594 .name = "ep6-iso",
2595 .ops = &lpc32xx_ep_ops,
2596 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2597 USB_EP_CAPS_DIR_ALL),
2598 },
2599 .maxpacket = 1023,
2600 .hwep_num_base = 12,
2601 .hwep_num = 0, /* 12 or 13, will be set later */
2602 .lep = 6,
2603 .eptype = EP_ISO_TYPE,
2604 },
2605 .ep[7] = {
2606 .ep = {
2607 .name = "ep7-int",
2608 .ops = &lpc32xx_ep_ops,
2609 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2610 USB_EP_CAPS_DIR_ALL),
2611 },
2612 .maxpacket = 64,
2613 .hwep_num_base = 14,
2614 .hwep_num = 0,
2615 .lep = 7,
2616 .eptype = EP_INT_TYPE,
2617 },
2618 .ep[8] = {
2619 .ep = {
2620 .name = "ep8-bulk",
2621 .ops = &lpc32xx_ep_ops,
2622 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2623 USB_EP_CAPS_DIR_ALL),
2624 },
2625 .maxpacket = 64,
2626 .hwep_num_base = 16,
2627 .hwep_num = 0,
2628 .lep = 8,
2629 .eptype = EP_BLK_TYPE,
2630 },
2631 .ep[9] = {
2632 .ep = {
2633 .name = "ep9-iso",
2634 .ops = &lpc32xx_ep_ops,
2635 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2636 USB_EP_CAPS_DIR_ALL),
2637 },
2638 .maxpacket = 1023,
2639 .hwep_num_base = 18,
2640 .hwep_num = 0,
2641 .lep = 9,
2642 .eptype = EP_ISO_TYPE,
2643 },
2644 .ep[10] = {
2645 .ep = {
2646 .name = "ep10-int",
2647 .ops = &lpc32xx_ep_ops,
2648 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2649 USB_EP_CAPS_DIR_ALL),
2650 },
2651 .maxpacket = 64,
2652 .hwep_num_base = 20,
2653 .hwep_num = 0,
2654 .lep = 10,
2655 .eptype = EP_INT_TYPE,
2656 },
2657 .ep[11] = {
2658 .ep = {
2659 .name = "ep11-bulk",
2660 .ops = &lpc32xx_ep_ops,
2661 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2662 USB_EP_CAPS_DIR_ALL),
2663 },
2664 .maxpacket = 64,
2665 .hwep_num_base = 22,
2666 .hwep_num = 0,
2667 .lep = 11,
2668 .eptype = EP_BLK_TYPE,
2669 },
2670 .ep[12] = {
2671 .ep = {
2672 .name = "ep12-iso",
2673 .ops = &lpc32xx_ep_ops,
2674 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2675 USB_EP_CAPS_DIR_ALL),
2676 },
2677 .maxpacket = 1023,
2678 .hwep_num_base = 24,
2679 .hwep_num = 0,
2680 .lep = 12,
2681 .eptype = EP_ISO_TYPE,
2682 },
2683 .ep[13] = {
2684 .ep = {
2685 .name = "ep13-int",
2686 .ops = &lpc32xx_ep_ops,
2687 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2688 USB_EP_CAPS_DIR_ALL),
2689 },
2690 .maxpacket = 64,
2691 .hwep_num_base = 26,
2692 .hwep_num = 0,
2693 .lep = 13,
2694 .eptype = EP_INT_TYPE,
2695 },
2696 .ep[14] = {
2697 .ep = {
2698 .name = "ep14-bulk",
2699 .ops = &lpc32xx_ep_ops,
2700 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2701 USB_EP_CAPS_DIR_ALL),
2702 },
2703 .maxpacket = 64,
2704 .hwep_num_base = 28,
2705 .hwep_num = 0,
2706 .lep = 14,
2707 .eptype = EP_BLK_TYPE,
2708 },
2709 .ep[15] = {
2710 .ep = {
2711 .name = "ep15-bulk",
2712 .ops = &lpc32xx_ep_ops,
2713 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2714 USB_EP_CAPS_DIR_ALL),
2715 },
2716 .maxpacket = 1023,
2717 .hwep_num_base = 30,
2718 .hwep_num = 0,
2719 .lep = 15,
2720 .eptype = EP_BLK_TYPE,
2721 },
2722 };
2723
2724 /* ISO and status interrupts */
2725 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2726 {
2727 u32 tmp, devstat;
2728 struct lpc32xx_udc *udc = _udc;
2729
2730 spin_lock(&udc->lock);
2731
2732 /* Read the device status register */
2733 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2734
2735 devstat &= ~USBD_EP_FAST;
2736 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2737 devstat = devstat & udc->enabled_devints;
2738
2739 /* Device specific handling needed? */
2740 if (devstat & USBD_DEV_STAT)
2741 udc_handle_dev(udc);
2742
2743 /* Start of frame? (devstat & FRAME_INT):
2744 * The frame interrupt isn't really needed for ISO support,
2745 * as the driver will queue the necessary packets */
2746
2747 /* Error? */
2748 if (devstat & ERR_INT) {
2749 /* All types of errors, from cable removal during transfer to
2750 * misc protocol and bit errors. These are mostly for just info,
2751 * as the USB hardware will work around these. If these errors
2752 * happen alot, something is wrong. */
2753 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2754 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2755 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2756 }
2757
2758 spin_unlock(&udc->lock);
2759
2760 return IRQ_HANDLED;
2761 }
2762
2763 /* EP interrupts */
2764 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2765 {
2766 u32 tmp;
2767 struct lpc32xx_udc *udc = _udc;
2768
2769 spin_lock(&udc->lock);
2770
2771 /* Read the device status register */
2772 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2773
2774 /* Endpoints */
2775 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2776
2777 /* Special handling for EP0 */
2778 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2779 /* Handle EP0 IN */
2780 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2781 udc_handle_ep0_in(udc);
2782
2783 /* Handle EP0 OUT */
2784 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2785 udc_handle_ep0_out(udc);
2786 }
2787
2788 /* All other EPs */
2789 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2790 int i;
2791
2792 /* Handle other EP interrupts */
2793 for (i = 1; i < NUM_ENDPOINTS; i++) {
2794 if (tmp & (1 << udc->ep[i].hwep_num))
2795 udc_handle_eps(udc, &udc->ep[i]);
2796 }
2797 }
2798
2799 spin_unlock(&udc->lock);
2800
2801 return IRQ_HANDLED;
2802 }
2803
2804 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2805 {
2806 struct lpc32xx_udc *udc = _udc;
2807
2808 int i;
2809 u32 tmp;
2810
2811 spin_lock(&udc->lock);
2812
2813 /* Handle EP DMA EOT interrupts */
2814 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2815 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2816 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2817 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2818 for (i = 1; i < NUM_ENDPOINTS; i++) {
2819 if (tmp & (1 << udc->ep[i].hwep_num))
2820 udc_handle_dma_ep(udc, &udc->ep[i]);
2821 }
2822
2823 spin_unlock(&udc->lock);
2824
2825 return IRQ_HANDLED;
2826 }
2827
2828 /*
2829 *
2830 * VBUS detection, pullup handler, and Gadget cable state notification
2831 *
2832 */
2833 static void vbus_work(struct lpc32xx_udc *udc)
2834 {
2835 u8 value;
2836
2837 if (udc->enabled != 0) {
2838 /* Discharge VBUS real quick */
2839 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2840 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2841
2842 /* Give VBUS some time (100mS) to discharge */
2843 msleep(100);
2844
2845 /* Disable VBUS discharge resistor */
2846 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2847 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2848 OTG1_VBUS_DISCHRG);
2849
2850 /* Clear interrupt */
2851 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2852 ISP1301_I2C_INTERRUPT_LATCH |
2853 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2854
2855 /* Get the VBUS status from the transceiver */
2856 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2857 ISP1301_I2C_INTERRUPT_SOURCE);
2858
2859 /* VBUS on or off? */
2860 if (value & INT_SESS_VLD)
2861 udc->vbus = 1;
2862 else
2863 udc->vbus = 0;
2864
2865 /* VBUS changed? */
2866 if (udc->last_vbus != udc->vbus) {
2867 udc->last_vbus = udc->vbus;
2868 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2869 }
2870 }
2871 }
2872
2873 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2874 {
2875 struct lpc32xx_udc *udc = _udc;
2876
2877 vbus_work(udc);
2878
2879 return IRQ_HANDLED;
2880 }
2881
2882 static int lpc32xx_start(struct usb_gadget *gadget,
2883 struct usb_gadget_driver *driver)
2884 {
2885 struct lpc32xx_udc *udc = to_udc(gadget);
2886
2887 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2888 dev_err(udc->dev, "bad parameter.\n");
2889 return -EINVAL;
2890 }
2891
2892 if (udc->driver) {
2893 dev_err(udc->dev, "UDC already has a gadget driver\n");
2894 return -EBUSY;
2895 }
2896
2897 udc->driver = driver;
2898 udc->gadget.dev.of_node = udc->dev->of_node;
2899 udc->enabled = 1;
2900 udc->gadget.is_selfpowered = 1;
2901 udc->vbus = 0;
2902
2903 /* Force VBUS process once to check for cable insertion */
2904 udc->last_vbus = udc->vbus = 0;
2905 vbus_work(udc);
2906
2907 /* enable interrupts */
2908 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2909 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2910 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2911 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2912
2913 return 0;
2914 }
2915
2916 static int lpc32xx_stop(struct usb_gadget *gadget)
2917 {
2918 struct lpc32xx_udc *udc = to_udc(gadget);
2919
2920 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2921 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2922 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2923 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2924
2925 if (udc->clocked) {
2926 spin_lock(&udc->lock);
2927 stop_activity(udc);
2928 spin_unlock(&udc->lock);
2929
2930 /*
2931 * Wait for all the endpoints to disable,
2932 * before disabling clocks. Don't wait if
2933 * endpoints are not enabled.
2934 */
2935 if (atomic_read(&udc->enabled_ep_cnt))
2936 wait_event_interruptible(udc->ep_disable_wait_queue,
2937 (atomic_read(&udc->enabled_ep_cnt) == 0));
2938
2939 spin_lock(&udc->lock);
2940 udc_clk_set(udc, 0);
2941 spin_unlock(&udc->lock);
2942 }
2943
2944 udc->enabled = 0;
2945 udc->driver = NULL;
2946
2947 return 0;
2948 }
2949
2950 static void lpc32xx_udc_shutdown(struct platform_device *dev)
2951 {
2952 /* Force disconnect on reboot */
2953 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2954
2955 pullup(udc, 0);
2956 }
2957
2958 /*
2959 * Callbacks to be overridden by options passed via OF (TODO)
2960 */
2961
2962 static void lpc32xx_usbd_conn_chg(int conn)
2963 {
2964 /* Do nothing, it might be nice to enable an LED
2965 * based on conn state being !0 */
2966 }
2967
2968 static void lpc32xx_usbd_susp_chg(int susp)
2969 {
2970 /* Device suspend if susp != 0 */
2971 }
2972
2973 static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2974 {
2975 /* Enable or disable USB remote wakeup */
2976 }
2977
2978 static struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2979 .vbus_drv_pol = 0,
2980 .conn_chgb = &lpc32xx_usbd_conn_chg,
2981 .susp_chgb = &lpc32xx_usbd_susp_chg,
2982 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2983 };
2984
2985
2986 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2987
2988 static int lpc32xx_udc_probe(struct platform_device *pdev)
2989 {
2990 struct device *dev = &pdev->dev;
2991 struct lpc32xx_udc *udc;
2992 int retval, i;
2993 dma_addr_t dma_handle;
2994 struct device_node *isp1301_node;
2995
2996 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
2997 if (!udc)
2998 return -ENOMEM;
2999
3000 for (i = 0; i <= 15; i++)
3001 udc->ep[i].udc = udc;
3002 udc->gadget.ep0 = &udc->ep[0].ep;
3003
3004 /* init software state */
3005 udc->gadget.dev.parent = dev;
3006 udc->pdev = pdev;
3007 udc->dev = &pdev->dev;
3008 udc->enabled = 0;
3009
3010 if (pdev->dev.of_node) {
3011 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3012 "transceiver", 0);
3013 } else {
3014 isp1301_node = NULL;
3015 }
3016
3017 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3018 if (!udc->isp1301_i2c_client) {
3019 return -EPROBE_DEFER;
3020 }
3021
3022 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3023 udc->isp1301_i2c_client->addr);
3024
3025 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3026 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3027 if (retval)
3028 return retval;
3029
3030 udc->board = &lpc32xx_usbddata;
3031
3032 /*
3033 * Resources are mapped as follows:
3034 * IORESOURCE_MEM, base address and size of USB space
3035 * IORESOURCE_IRQ, USB device low priority interrupt number
3036 * IORESOURCE_IRQ, USB device high priority interrupt number
3037 * IORESOURCE_IRQ, USB device interrupt number
3038 * IORESOURCE_IRQ, USB transceiver interrupt number
3039 */
3040
3041 spin_lock_init(&udc->lock);
3042
3043 /* Get IRQs */
3044 for (i = 0; i < 4; i++) {
3045 udc->udp_irq[i] = platform_get_irq(pdev, i);
3046 if (udc->udp_irq[i] < 0)
3047 return udc->udp_irq[i];
3048 }
3049
3050 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0);
3051 if (IS_ERR(udc->udp_baseaddr)) {
3052 dev_err(udc->dev, "IO map failure\n");
3053 return PTR_ERR(udc->udp_baseaddr);
3054 }
3055
3056 /* Get USB device clock */
3057 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3058 if (IS_ERR(udc->usb_slv_clk)) {
3059 dev_err(udc->dev, "failed to acquire USB device clock\n");
3060 return PTR_ERR(udc->usb_slv_clk);
3061 }
3062
3063 /* Enable USB device clock */
3064 retval = clk_prepare_enable(udc->usb_slv_clk);
3065 if (retval < 0) {
3066 dev_err(udc->dev, "failed to start USB device clock\n");
3067 return retval;
3068 }
3069
3070 /* Setup deferred workqueue data */
3071 udc->poweron = udc->pullup = 0;
3072 INIT_WORK(&udc->pullup_job, pullup_work);
3073 #ifdef CONFIG_PM
3074 INIT_WORK(&udc->power_job, power_work);
3075 #endif
3076
3077 /* All clocks are now on */
3078 udc->clocked = 1;
3079
3080 isp1301_udc_configure(udc);
3081 /* Allocate memory for the UDCA */
3082 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3083 &dma_handle,
3084 (GFP_KERNEL | GFP_DMA));
3085 if (!udc->udca_v_base) {
3086 dev_err(udc->dev, "error getting UDCA region\n");
3087 retval = -ENOMEM;
3088 goto i2c_fail;
3089 }
3090 udc->udca_p_base = dma_handle;
3091 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3092 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3093
3094 /* Setup the DD DMA memory pool */
3095 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3096 sizeof(struct lpc32xx_usbd_dd_gad),
3097 sizeof(u32), 0);
3098 if (!udc->dd_cache) {
3099 dev_err(udc->dev, "error getting DD DMA region\n");
3100 retval = -ENOMEM;
3101 goto dma_alloc_fail;
3102 }
3103
3104 /* Clear USB peripheral and initialize gadget endpoints */
3105 udc_disable(udc);
3106 udc_reinit(udc);
3107
3108 /* Request IRQs - low and high priority USB device IRQs are routed to
3109 * the same handler, while the DMA interrupt is routed elsewhere */
3110 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3111 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3112 if (retval < 0) {
3113 dev_err(udc->dev, "LP request irq %d failed\n",
3114 udc->udp_irq[IRQ_USB_LP]);
3115 goto irq_req_fail;
3116 }
3117 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3118 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3119 if (retval < 0) {
3120 dev_err(udc->dev, "HP request irq %d failed\n",
3121 udc->udp_irq[IRQ_USB_HP]);
3122 goto irq_req_fail;
3123 }
3124
3125 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3126 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3127 if (retval < 0) {
3128 dev_err(udc->dev, "DEV request irq %d failed\n",
3129 udc->udp_irq[IRQ_USB_DEVDMA]);
3130 goto irq_req_fail;
3131 }
3132
3133 /* The transceiver interrupt is used for VBUS detection and will
3134 kick off the VBUS handler function */
3135 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3136 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3137 "udc_otg", udc);
3138 if (retval < 0) {
3139 dev_err(udc->dev, "VBUS request irq %d failed\n",
3140 udc->udp_irq[IRQ_USB_ATX]);
3141 goto irq_req_fail;
3142 }
3143
3144 /* Initialize wait queue */
3145 init_waitqueue_head(&udc->ep_disable_wait_queue);
3146 atomic_set(&udc->enabled_ep_cnt, 0);
3147
3148 retval = usb_add_gadget_udc(dev, &udc->gadget);
3149 if (retval < 0)
3150 goto add_gadget_fail;
3151
3152 dev_set_drvdata(dev, udc);
3153 device_init_wakeup(dev, 1);
3154 create_debug_file(udc);
3155
3156 /* Disable clocks for now */
3157 udc_clk_set(udc, 0);
3158
3159 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3160 return 0;
3161
3162 add_gadget_fail:
3163 irq_req_fail:
3164 dma_pool_destroy(udc->dd_cache);
3165 dma_alloc_fail:
3166 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3167 udc->udca_v_base, udc->udca_p_base);
3168 i2c_fail:
3169 clk_disable_unprepare(udc->usb_slv_clk);
3170 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3171
3172 return retval;
3173 }
3174
3175 static int lpc32xx_udc_remove(struct platform_device *pdev)
3176 {
3177 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3178
3179 usb_del_gadget_udc(&udc->gadget);
3180 if (udc->driver)
3181 return -EBUSY;
3182
3183 udc_clk_set(udc, 1);
3184 udc_disable(udc);
3185 pullup(udc, 0);
3186
3187 device_init_wakeup(&pdev->dev, 0);
3188 remove_debug_file(udc);
3189
3190 dma_pool_destroy(udc->dd_cache);
3191 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3192 udc->udca_v_base, udc->udca_p_base);
3193
3194 clk_disable_unprepare(udc->usb_slv_clk);
3195
3196 return 0;
3197 }
3198
3199 #ifdef CONFIG_PM
3200 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3201 {
3202 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3203
3204 if (udc->clocked) {
3205 /* Power down ISP */
3206 udc->poweron = 0;
3207 isp1301_set_powerstate(udc, 0);
3208
3209 /* Disable clocking */
3210 udc_clk_set(udc, 0);
3211
3212 /* Keep clock flag on, so we know to re-enable clocks
3213 on resume */
3214 udc->clocked = 1;
3215
3216 /* Kill global USB clock */
3217 clk_disable_unprepare(udc->usb_slv_clk);
3218 }
3219
3220 return 0;
3221 }
3222
3223 static int lpc32xx_udc_resume(struct platform_device *pdev)
3224 {
3225 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3226
3227 if (udc->clocked) {
3228 /* Enable global USB clock */
3229 clk_prepare_enable(udc->usb_slv_clk);
3230
3231 /* Enable clocking */
3232 udc_clk_set(udc, 1);
3233
3234 /* ISP back to normal power mode */
3235 udc->poweron = 1;
3236 isp1301_set_powerstate(udc, 1);
3237 }
3238
3239 return 0;
3240 }
3241 #else
3242 #define lpc32xx_udc_suspend NULL
3243 #define lpc32xx_udc_resume NULL
3244 #endif
3245
3246 #ifdef CONFIG_OF
3247 static const struct of_device_id lpc32xx_udc_of_match[] = {
3248 { .compatible = "nxp,lpc3220-udc", },
3249 { },
3250 };
3251 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3252 #endif
3253
3254 static struct platform_driver lpc32xx_udc_driver = {
3255 .remove = lpc32xx_udc_remove,
3256 .shutdown = lpc32xx_udc_shutdown,
3257 .suspend = lpc32xx_udc_suspend,
3258 .resume = lpc32xx_udc_resume,
3259 .driver = {
3260 .name = driver_name,
3261 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3262 },
3263 };
3264
3265 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3266
3267 MODULE_DESCRIPTION("LPC32XX udc driver");
3268 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3269 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3270 MODULE_LICENSE("GPL");
3271 MODULE_ALIAS("platform:lpc32xx_udc");
Linux with added FPC-III support