| blob | 6c726d2e1788e1d6045feb3c73ac8cc50dbf2169 |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
4 *
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
6 * Author: Thomas Dahlmann
7 */
9 /*
10 * This file does the core driver implementation for the UDC that is based
11 * on Synopsys device controller IP (different than HS OTG IP) that is either
12 * connected through PCI bus or integrated to SoC platforms.
13 */
15 /* Driver strings */
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/timer.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioctl.h>
31 #include <linux/fs.h>
32 #include <linux/dmapool.h>
33 #include <linux/prefetch.h>
34 #include <linux/moduleparam.h>
35 #include <asm/byteorder.h>
36 #include <asm/unaligned.h>
45 /* description */
49 /* structure to hold endpoint function pointers */
52 /* received setup data */
55 /* pointer to device object */
58 /* irq spin lock for soft reset */
60 /* stall spin lock */
63 /*
64 * slave mode: pending bytes in rx fifo after nyet,
65 * used if EPIN irq came but no req was available
66 */
69 /* count soft resets after suspend to avoid loop */
73 /* timer */
77 /* set_rde -- Is used to control enabling of RX DMA. Problem is
78 * that UDC has only one bit (RDE) to enable/disable RX DMA for
79 * all OUT endpoints. So we have to handle race conditions like
80 * when OUT data reaches the fifo but no request was queued yet.
81 * This cannot be solved by letting the RX DMA disabled until a
82 * request gets queued because there may be other OUT packets
83 * in the FIFO (important for not blocking control traffic).
84 * The value of set_rde controls the correspondig timer.
85 *
86 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 0 == do not touch RDE, do no start the RDE timer
88 * set_rde 1 == timer function will look whether FIFO has data
89 * set_rde 2 == set by timer function to enable RX DMA on next call
90 */
98 /* tasklet for usb disconnect */
101 /* endpoint names used for print */
107 #define EP_INFO(_name, _caps) \
108 { \
109 .name = _name, \
110 .caps = _caps, \
111 }
178 #undef EP_INFO
179 };
181 /* buffer fill mode */
183 /* tx buffer size for high speed */
186 /*---------------------------------------------------------------------------*/
187 /* Prints UDC device registers and endpoint irq registers */
189 {
210 }
214 }
218 }
220 /* Masks unused interrupts */
222 {
223 u32 tmp;
225 /* mask all dev interrupts */
236 /* mask all ep interrupts */
240 }
243 /* Enables endpoint 0 interrupts */
245 {
246 u32 tmp;
250 /* read irq mask */
252 /* enable ep0 irq's */
258 }
260 /* Enables device interrupts for SET_INTF and SET_CONFIG */
262 {
263 u32 tmp;
267 /* read irq mask */
270 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
279 }
282 /* Calculates fifo start of endpoint based on preceding endpoints */
284 {
286 u32 tmp;
295 /* traverse ep's */
298 /* read fifo size */
302 }
303 }
305 }
307 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
311 {
318 }
321 /* Enables endpoint, is called by gadget driver */
322 static int
324 {
327 u32 tmp;
329 u8 udc_csr_epix;
334 || !desc
351 /* set traffic type */
356 /* set max packet size */
363 /* IN ep */
366 /* ep ix in UDC CSR register space */
369 /* set buffer size (tx fifo entries) */
371 /* double buffering: fifo size = 2 x max packet size */
373 tmp,
374 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
376 UDC_EPIN_BUFF_SIZE);
379 /* calc. tx fifo base addr */
382 /* flush fifo */
387 /* OUT ep */
389 /* ep ix in UDC CSR register space */
392 /* set max packet size UDC CSR */
395 UDC_CSR_NE_MAX_PKT);
399 /* alloc and init BNA dummy request */
402 }
406 }
408 /* set ep values */
410 /* max packet */
412 /* ep number */
414 /* ep direction */
416 /* ep type */
418 /* ep config */
420 /* ep interface */
422 /* ep alt */
424 /* write reg */
427 /* enable ep irq */
432 /*
433 * clear NAK by writing CNAK
434 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
435 */
442 }
448 }
450 /* Resets endpoint */
452 {
453 u32 tmp;
461 /* set NAK */
467 /* disable interrupt */
473 /* unset P and IN bit of potential former DMA */
482 /* flush the fifo */
487 }
488 /* reset desc pointer */
490 }
492 /* Disables endpoint, is called by gadget driver */
494 {
514 }
516 /* Allocates request packet, called by gadget driver */
519 {
538 /* ep0 in requests are allocated from data pool here */
544 }
550 /* prevent from using desc. - set HOST BUSY */
552 UDC_DMA_STP_STS_BS_HOST_BUSY,
553 UDC_DMA_STP_STS_BS);
558 }
561 }
563 /* frees pci pool descriptors of a DMA chain */
565 {
574 /* do not free first desc., will be done by free for request */
580 }
581 }
583 /* Frees request packet, called by gadget driver */
584 static void
586 {
600 /* free dma chain if created */
606 }
608 }
610 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
612 {
614 /* set last bit */
616 /* set next pointer to itself */
618 /* set HOST BUSY */
621 UDC_DMA_STP_STS_BS_DMA_DONE,
622 UDC_DMA_STP_STS_BS);
623 #ifdef UDC_VERBOSE
626 #endif
627 }
628 }
630 /* Allocate BNA dummy descriptor */
632 {
636 /* alloc the dummy request */
642 }
644 }
646 /* Write data to TX fifo for IN packets */
647 static void
649 {
669 /* dwords first */
673 /* remaining bytes must be written by byte access */
677 }
679 /* dummy write confirm */
681 }
683 /* Read dwords from RX fifo for OUT transfers */
685 {
693 }
695 /* Read bytes from RX fifo for OUT transfers */
697 {
699 u32 tmp;
703 /* dwords first */
707 /* remaining bytes must be read by byte access */
713 }
714 }
717 }
719 /* Read data from RX fifo for OUT transfers */
720 static int
722 {
728 /* received number bytes */
740 }
742 }
745 /* last packet ? */
750 /* read rx fifo bytes */
755 }
757 /* Creates or re-inits a DMA chain */
762 )
763 {
766 dma_addr_t dma_addr;
777 /* unset L bit in first desc for OUT */
781 /* alloc only new desc's if not already available */
784 len++;
787 /* shorter chain already allocated before */
792 }
795 /* gen. required number of descriptors and buffers */
797 /* create or determine next desc. */
806 /* first td */
813 }
817 else
820 /* short packet ? */
824 /* short packet */
826 }
828 /* link td and assign tx bytes */
832 /*
833 * else
834 * req->td_data->next = virt_to_phys(td);
835 */
836 /* write tx bytes */
838 /* first desc */
842 UDC_DMA_IN_STS_TXBYTES);
843 /* second desc */
845 txbytes,
846 UDC_DMA_IN_STS_TXBYTES);
847 }
851 /*
852 * else
853 * last->next = virt_to_phys(td);
854 */
856 /* write tx bytes */
858 txbytes,
859 UDC_DMA_IN_STS_TXBYTES);
860 }
861 }
863 }
864 /* set last bit */
867 /* last desc. points to itself */
869 }
872 }
874 /* create/re-init a DMA descriptor or a DMA descriptor chain */
876 {
878 u32 tmp;
884 /* set buffer pointer */
887 /* set last bit */
890 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
898 }
901 /* write tx bytes */
905 UDC_DMA_IN_STS_TXBYTES);
907 }
908 }
910 }
917 /*
918 * if bytes < max packet then tx bytes must
919 * be written in packet per buffer mode
920 */
924 /* write tx bytes */
928 UDC_DMA_IN_STS_TXBYTES);
929 /* reset frame num */
933 UDC_DMA_IN_STS_FRAMENUM);
934 }
935 /* set HOST BUSY */
938 UDC_DMA_STP_STS_BS_HOST_BUSY,
939 UDC_DMA_STP_STS_BS);
942 /* set HOST READY */
945 UDC_DMA_STP_STS_BS_HOST_READY,
946 UDC_DMA_STP_STS_BS);
948 /* clear NAK by writing CNAK */
955 }
957 }
960 }
962 /* Completes request packet ... caller MUST hold lock */
963 static void
967 {
974 /* unmap DMA */
981 /* set new status if pending */
985 /* remove from ep queue */
995 }
997 /* Iterates to the end of a DMA chain and returns last descriptor */
999 {
1008 }
1010 /* Iterates to the end of a DMA chain and counts bytes received */
1012 {
1014 u32 count;
1017 /* received number bytes */
1022 /* received number bytes */
1025 UDC_DMA_OUT_STS_RXBYTES);
1026 }
1027 }
1031 }
1033 /* Enabling RX DMA */
1035 {
1036 u32 tmp;
1039 /* stop RDE timer */
1043 }
1044 /* set RDE */
1048 }
1050 /* Queues a request packet, called by gadget driver */
1051 static int
1053 {
1060 u32 tmp;
1062 /* check the inputs */
1079 /* map dma (usually done before) */
1085 }
1096 /* on empty queue just do first transfer */
1098 /* zlp */
1100 /* IN zlp's are handled by hardware */
1103 /*
1104 * if set_config or set_intf is waiting for ack by zlp
1105 * then set CSR_DONE
1106 */
1112 }
1113 /* setup command is ACK'ed now by zlp */
1115 /* clear NAK by writing CNAK in EP0_IN */
1121 UDC_EP0IN_IX);
1123 }
1125 }
1130 /* write desc pointer to enable DMA */
1132 /* set HOST READY */
1135 UDC_DMA_IN_STS_BS_HOST_READY,
1136 UDC_DMA_IN_STS_BS);
1137 }
1139 /* disabled rx dma while descriptor update */
1141 /* stop RDE timer */
1145 }
1146 /* clear RDE */
1152 /*
1153 * if BNA occurred then let BNA dummy desc.
1154 * point to current desc.
1155 */
1161 }
1162 }
1163 /* write desc pointer */
1166 /* clear NAK by writing CNAK */
1173 }
1176 /* enable ep irq */
1180 }
1182 /* enable ep irq */
1186 }
1190 /*
1191 * prep_dma not used for OUT ep's, this is not possible
1192 * for PPB modes, because of chain creation reasons
1193 */
1198 }
1199 }
1201 /* add request to ep queue */
1206 /* open rxfifo if out data queued */
1208 /* enable DMA */
1213 }
1214 /* stop OUT naking */
1219 /*
1220 * read pending bytes afer nyet:
1221 * referring to isr
1222 */
1224 /* finish */
1226 }
1229 }
1230 }
1231 }
1233 finished:
1236 }
1238 /* Empty request queue of an endpoint; caller holds spinlock */
1240 {
1247 queue);
1249 }
1250 }
1253 /* Dequeues a request packet, called by gadget driver */
1255 {
1271 /* request in processing or next one */
1277 u32 tmp;
1278 u32 dma_sts;
1279 /* stop potential receive DMA */
1283 /*
1284 * Cancel transfer later in ISR
1285 * if descriptor was touched.
1286 */
1288 UDC_DMA_OUT_STS_BS);
1295 }
1297 }
1298 }
1299 }
1305 }
1307 /* Halt or clear halt of endpoint */
1308 static int
1310 {
1312 u32 tmp;
1328 /* halt or clear halt */
1333 /*
1334 * set STALL
1335 * rxfifo empty not taken into acount
1336 */
1342 /* setup poll timer */
1345 HZ * UDC_POLLSTALL_TIMER_USECONDS
1350 }
1351 }
1352 }
1354 /* ep is halted by set_halt() before */
1357 /* clear stall bit */
1359 /* clear NAK by writing CNAK */
1364 }
1365 }
1368 }
1370 /* gadget interface */
1382 /* fifo ops not implemented */
1383 };
1385 /*-------------------------------------------------------------------------*/
1387 /* Get frame counter (not implemented) */
1389 {
1391 }
1393 /* Initiates a remote wakeup */
1395 {
1397 u32 tmp;
1411 }
1413 /* Remote wakeup gadget interface */
1415 {
1424 }
1435 };
1437 /* Setups endpoint parameters, adds endpoints to linked list */
1439 {
1440 /* make gadget ep lists */
1449 /* fifo config */
1456 }
1458 /* Inits UDC context */
1460 {
1461 u32 tmp;
1467 /* stop RDE timer */
1471 }
1472 /* stop poll stall timer */
1475 /* disable DMA */
1481 /* enable dynamic CSR programming */
1484 /* set self powered */
1486 /* set remote wakeupable */
1494 }
1497 /* init registers at driver load time */
1499 {
1500 u32 tmp;
1502 /* init controller by soft reset */
1505 /* mask not needed interrupts */
1508 /* put into initial config */
1510 /* link up all endpoints */
1513 /* program speed */
1517 else
1522 }
1524 /* Sets initial endpoint parameters */
1526 {
1528 u32 tmp;
1529 u32 reg;
1533 /* read enum speed */
1541 /* set basic ep parameters */
1548 /* txfifo size is calculated at enable time */
1551 /* fifo size */
1559 }
1561 /*
1562 * ep will be reset only if ep was not enabled before to avoid
1563 * disabling ep interrupts when ENUM interrupt occurs but ep is
1564 * not enabled by gadget driver
1565 */
1570 /*
1571 * ep->dma is not really used, just to indicate that
1572 * DMA is active: remove this
1573 * dma regs = dev control regs
1574 */
1577 /* nak OUT endpoints until enable - not for ep0 */
1580 /* set NAK */
1586 }
1587 }
1588 }
1589 /* EP0 max packet */
1592 UDC_FS_EP0IN_MAX_PKT_SIZE);
1594 UDC_FS_EP0OUT_MAX_PKT_SIZE);
1597 UDC_EP0IN_MAX_PKT_SIZE);
1599 UDC_EP0OUT_MAX_PKT_SIZE);
1600 }
1602 /*
1603 * with suspend bug workaround, ep0 params for gadget driver
1604 * are set at gadget driver bind() call
1605 */
1610 /* init cfg/alt/int */
1614 }
1616 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1618 {
1619 /* Return if already connected */
1627 /* put into initial config */
1630 /* enable device setup interrupts */
1632 }
1634 /*
1635 * Calls gadget with disconnect event and resets the UDC and makes
1636 * initial bringup to be ready for ep0 events
1637 */
1639 {
1640 /* Return if already disconnected */
1648 /* mask interrupts */
1651 /* REVISIT there doesn't seem to be a point to having this
1652 * talk to a tasklet ... do it directly, we already hold
1653 * the spinlock needed to process the disconnect.
1654 */
1657 }
1659 /* Tasklet for disconnect to be outside of interrupt context */
1661 {
1663 u32 tmp;
1673 /* empty queues */
1677 }
1679 /* disable ep0 */
1685 /* init controller by soft reset */
1687 soft_reset_occured++;
1688 }
1690 /* re-enable dev interrupts */
1692 /* back to full speed ? */
1697 }
1700 }
1702 /* Reset the UDC core */
1704 {
1708 /*
1709 * reset possible waiting interrupts, because int.
1710 * status is lost after soft reset,
1711 * ep int. status reset
1712 */
1714 /* device int. status reset */
1717 /* Don't do this for Broadcom UDC since this is a reserved
1718 * bit.
1719 */
1725 }
1726 }
1728 /* RDE timer callback to set RDE bit */
1730 {
1731 u32 tmp;
1736 /*
1737 * open the fifo if fifo was filled on last timer call
1738 * conditionally
1739 */
1741 /* set RDE to receive setup data */
1748 /*
1749 * if fifo empty setup polling, do not just
1750 * open the fifo
1751 */
1756 /*
1757 * fifo contains data now, setup timer for opening
1758 * the fifo when timer expires to be able to receive
1759 * setup packets, when data packets gets queued by
1760 * gadget layer then timer will forced to expire with
1761 * set_rde=0 (RDE is set in udc_queue())
1762 */
1763 set_rde++;
1764 /* debug: lhadmot_timer_start = 221070 */
1768 }
1776 }
1778 /* Handle halt state, used in stall poll timer */
1780 {
1781 u32 tmp;
1782 /* set stall as long not halted */
1785 /* STALL cleared ? */
1787 /*
1788 * FIXME: MSC spec requires that stall remains
1789 * even on receivng of CLEAR_FEATURE HALT. So
1790 * we would set STALL again here to be compliant.
1791 * But with current mass storage drivers this does
1792 * not work (would produce endless host retries).
1793 * So we clear halt on CLEAR_FEATURE.
1794 *
1795 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1796 tmp |= AMD_BIT(UDC_EPCTL_S);
1797 writel(tmp, &ep->regs->ctl);*/
1799 /* clear NAK by writing CNAK */
1804 }
1805 }
1806 }
1808 /* Stall timer callback to poll S bit and set it again after */
1810 {
1815 /*
1816 * only one IN and OUT endpoints are handled
1817 * IN poll stall
1818 */
1823 /* OUT poll stall */
1829 /* setup timer again when still halted */
1832 HZ * UDC_POLLSTALL_TIMER_USECONDS
1835 }
1840 }
1842 /* Inits endpoint 0 so that SETUP packets are processed */
1844 {
1845 u32 tmp;
1849 /* flush fifo */
1854 /* set ep0 directions */
1858 /* set buffer size (tx fifo entries) of EP0_IN */
1862 UDC_EPIN_BUFF_SIZE);
1865 UDC_EPIN_BUFF_SIZE);
1868 /* set max packet size of EP0_IN */
1872 UDC_EP_MAX_PKT_SIZE);
1875 UDC_EP_MAX_PKT_SIZE);
1878 /* set max packet size of EP0_OUT */
1882 UDC_EP_MAX_PKT_SIZE);
1885 UDC_EP_MAX_PKT_SIZE);
1888 /* set max packet size of EP0 in UDC CSR */
1892 UDC_CSR_NE_MAX_PKT);
1895 UDC_CSR_NE_MAX_PKT);
1901 /* write dma desc address */
1906 /* stop RDE timer */
1910 }
1911 /* stop pollstall timer */
1914 /* enable DMA */
1924 }
1926 /* clear NAK by writing CNAK for EP0IN */
1933 /* clear NAK by writing CNAK for EP0OUT */
1939 }
1941 /* Make endpoint 0 ready for control traffic */
1943 {
1945 /* enable ep0 interrupts */
1947 /* enable device setup interrupts */
1951 }
1953 /* Called by gadget driver to register itself */
1956 {
1958 u32 tmp;
1963 /* Some gadget drivers use both ep0 directions.
1964 * NOTE: to gadget driver, ep0 is just one endpoint...
1965 */
1969 /* get ready for ep0 traffic */
1972 /* clear SD */
1980 }
1982 /* shutdown requests and disconnect from gadget */
1983 static void
1987 {
1990 /* empty queues and init hardware */
1997 }
1999 /* Called by gadget driver to unregister itself */
2001 {
2004 u32 tmp;
2013 /* set SD */
2019 }
2021 /* Clear pending NAK bits */
2023 {
2024 u32 tmp;
2025 u32 reg;
2027 /* check epin's */
2032 /* clear NAK by writing CNAK */
2038 }
2039 }
2040 /* ... and ep0out */
2043 /* clear NAK by writing CNAK */
2050 }
2051 }
2053 /* Enabling RX DMA after setup packet */
2055 {
2057 /*
2058 * only enable RXDMA when no data endpoint enabled
2059 * or data is queued
2060 */
2064 /*
2065 * setup timer for enabling RDE (to not enable
2066 * RXFIFO DMA for data endpoints to early)
2067 */
2074 }
2075 }
2076 }
2077 }
2080 /* Interrupt handler for data OUT traffic */
2082 {
2084 u32 tmp;
2096 /* BNA event ? */
2100 /* clear BNA */
2104 else
2108 }
2109 }
2110 /* HE event ? */
2114 /* clear HE */
2118 }
2122 /* next request */
2128 }
2130 /* fifo mode */
2133 /* read fifo */
2137 /* finish */
2139 /* next request */
2145 }
2147 /* DMA */
2151 /* check for DMA done */
2154 UDC_DMA_OUT_STS_BS);
2155 /* packet per buffer mode - rx bytes */
2157 /*
2158 * if BNA occurred then recover desc. from
2159 * BNA dummy desc.
2160 */
2167 }
2170 }
2172 /* buffer fill mode - rx bytes */
2174 /* received number bytes */
2176 UDC_DMA_OUT_STS_RXBYTES);
2178 /* packet per buffer mode - rx bytes */
2182 /* received number bytes */
2184 /* every desc. counts bytes */
2187 /* last desc. counts bytes */
2189 UDC_DMA_OUT_STS_RXBYTES);
2192 /*
2193 * on 64k packets the RXBYTES
2194 * field is zero
2195 */
2197 }
2198 }
2200 }
2208 }
2210 }
2213 /* complete request */
2216 /* next request */
2220 queue);
2221 /*
2222 * DMA may be already started by udc_queue()
2223 * called by gadget drivers completion
2224 * routine. This happens when queue
2225 * holds one request only.
2226 */
2228 /* next dma */
2231 /* write desc pointer */
2235 /* enable DMA */
2237 }
2239 /*
2240 * implant BNA dummy descriptor to allow
2241 * RXFIFO opening by RDE
2242 */
2244 /* write desc pointer */
2248 }
2250 /*
2251 * schedule timer for setting RDE if queue
2252 * remains empty to allow ep0 packets pass
2253 * through
2254 */
2258 jiffies
2263 }
2266 }
2269 /*
2270 * RX DMA must be reenabled for each desc in PPBDU mode
2271 * and must be enabled for PPBNDU mode in case of BNA
2272 */
2274 }
2279 }
2281 /* check pending CNAKS */
2283 /* CNAk processing when rxfifo empty only */
2286 }
2288 /* clear OUT bits in ep status */
2290 finished:
2292 }
2294 /* Interrupt handler for data IN traffic */
2296 {
2298 u32 tmp;
2299 u32 epsts;
2309 /* BNA ? */
2316 /* clear BNA */
2320 }
2321 }
2322 /* HE event ? */
2328 /* clear HE */
2332 }
2334 /* DMA completion */
2341 /*
2342 * length bytes transferred
2343 * check dma done of last desc. in PPBDU mode
2344 */
2350 /* assume all bytes transferred */
2352 }
2355 /* complete req */
2358 /* further request available ? */
2360 /* disable interrupt */
2364 }
2365 }
2366 }
2369 }
2370 /*
2371 * status reg has IN bit set and TDC not set (if TDC was handled,
2372 * IN must not be handled (UDC defect) ?
2373 */
2378 /* next request */
2381 /* FIFO mode */
2383 /* write fifo */
2391 /* complete req */
2393 }
2394 /* DMA */
2402 /*
2403 * unset L bit of first desc.
2404 * for chain
2405 */
2410 UDC_DMA_IN_STS_L);
2411 }
2413 /* write desc pointer */
2416 /* set HOST READY */
2420 UDC_DMA_IN_STS_BS_HOST_READY,
2421 UDC_DMA_IN_STS_BS);
2423 /* set poll demand bit */
2427 }
2428 }
2431 /* disable interrupt */
2437 }
2438 }
2439 /* clear status bits */
2442 finished:
2445 }
2447 /* Interrupt handler for Control OUT traffic */
2451 {
2453 u32 tmp;
2455 u32 count;
2462 /* clear irq */
2466 /* check BNA and clear if set */
2474 }
2476 /* type of data: SETUP or DATA 0 bytes */
2480 /* setup data */
2487 /* set NAK for EP0_IN */
2492 /* get setup data */
2495 /* clear OUT bits in ep status */
2503 /* set HOST READY */
2505 UDC_DMA_STP_STS_BS_HOST_READY;
2507 /* read fifo */
2509 }
2511 /* determine direction of control data */
2514 /* enable RDE */
2519 /*
2520 * implant BNA dummy descriptor to allow RXFIFO opening
2521 * by RDE
2522 */
2524 /* write desc pointer */
2528 }
2532 /*
2533 * setup timer for enabling RDE (to not enable
2534 * RXFIFO DMA for data to early)
2535 */
2542 }
2543 }
2545 /*
2546 * mass storage reset must be processed here because
2547 * next packet may be a CLEAR_FEATURE HALT which would not
2548 * clear the stall bit when no STALL handshake was received
2549 * before (autostall can cause this)
2550 */
2554 /*
2555 * clear stall bits
2556 * only one IN and OUT endpoints are handled
2557 */
2562 }
2564 /* call gadget with setup data received */
2571 /* ep0 in returns data (not zlp) on IN phase */
2573 UDC_EP0IN_MAXPACKET) {
2574 /* clear NAK by writing CNAK in EP0_IN */
2580 /* if unsupported request then stall */
2588 /* clear NAK by writing CNAK in EP0_OUT */
2595 }
2598 /* clear OUT bits in ep status */
2601 }
2603 /* data packet 0 bytes */
2605 /* clear OUT bits in ep status */
2608 /* get setup data: only 0 packet */
2610 /* no req if 0 packet, just reactivate */
2614 /* set HOST READY */
2618 UDC_DMA_OUT_STS_BS_HOST_READY,
2619 UDC_DMA_OUT_STS_BS);
2620 /* enable RDE */
2625 /* control write */
2627 /* re-program desc. pointer for possible ZLPs */
2630 /* enable RDE */
2632 }
2635 /* received number bytes */
2638 /* out data for fifo mode not working */
2641 /* 0 packet or real data ? */
2645 /* dummy read confirm */
2648 }
2649 }
2650 }
2652 /* check pending CNAKS */
2654 /* CNAk processing when rxfifo empty only */
2657 }
2659 finished:
2661 }
2663 /* Interrupt handler for Control IN traffic */
2665 {
2667 u32 tmp;
2674 /* clear irq */
2678 /* DMA completion */
2683 /* clear TDC bit */
2687 /* status reg has IN bit set ? */
2692 /* clear IN bit */
2695 }
2698 /* halt ep0in */
2704 /* next request */
2709 /* write desc pointer */
2711 /* set HOST READY */
2715 UDC_DMA_STP_STS_BS_HOST_READY,
2716 UDC_DMA_STP_STS_BS);
2718 /* set poll demand bit */
2719 tmp =
2725 /* all bytes will be transferred */
2728 /* complete req */
2732 /* write fifo */
2735 /* lengh bytes transferred */
2743 /* complete req */
2745 }
2746 }
2748 }
2749 }
2753 /* clear IN bit */
2756 }
2757 }
2760 }
2763 /* Interrupt handler for global device events */
2767 {
2769 u32 tmp;
2770 u32 cfg;
2772 u16 i;
2773 u8 udc_csr_epix;
2775 /* SET_CONFIG irq ? */
2779 /* read config value */
2786 /* make usb request for gadget driver */
2791 /* programm the NE registers */
2796 /* ep ix in UDC CSR register space */
2800 /* OUT ep */
2802 /* ep ix in UDC CSR register space */
2804 }
2807 /* ep cfg */
2809 UDC_CSR_NE_CFG);
2810 /* write reg */
2813 /* clear stall bits */
2818 }
2819 /* call gadget zero with setup data received */
2829 /* read interface and alt setting values */
2834 /* make usb request for gadget driver */
2844 /* programm the NE registers */
2849 /* ep ix in UDC CSR register space */
2853 /* OUT ep */
2855 /* ep ix in UDC CSR register space */
2857 }
2859 /* UDC CSR reg */
2860 /* set ep values */
2862 /* ep interface */
2864 UDC_CSR_NE_INTF);
2865 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2866 /* ep alt */
2868 UDC_CSR_NE_ALT);
2869 /* write reg */
2872 /* clear stall bits */
2877 }
2879 /* call gadget zero with setup data received */
2889 /* allow soft reset when suspend occurs */
2895 /* mask not needed interrupts */
2898 /* call gadget to resume and reset configs etc. */
2903 }
2907 /* disable ep0 to empty req queue */
2911 /* soft reset when rxfifo not empty */
2916 soft_reset_after_usbreset_occured++;
2917 }
2919 /*
2920 * DMA reset to kill potential old DMA hw hang,
2921 * POLL bit is already reset by ep_init() through
2922 * disconnect()
2923 */
2929 /* put into initial config */
2932 /* enable device setup interrupts */
2935 /* enable suspend interrupt */
2949 }
2956 /* disable ep0 to empty req queue */
2960 /* link up all endpoints */
2965 /* init ep 0 */
2968 /* enable ep0 interrupts */
2970 }
2971 /* session valid change interrupt */
2976 /* check that session is not valid to detect disconnect */
2979 /* disable suspend interrupt */
2984 /* cleanup on disconnect */
2986 }
2988 }
2991 }
2993 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2995 {
2997 u32 reg;
2998 u16 i;
2999 u32 ep_irq;
3004 /* check for ep irq */
3012 /*
3013 * data endpoint
3014 * iterate ep's
3015 */
3021 /* clear irq status */
3024 /* irq for out ep ? */
3027 else
3029 }
3031 }
3034 /* check for dev irq */
3037 /* clear irq */
3040 }
3045 }
3048 /* Tears down device */
3050 {
3053 }
3056 /* Cleanup on device remove */
3058 {
3059 /* remove timer */
3060 stop_timer++;
3064 /* remove pollstall timer */
3065 stop_pollstall_timer++;
3070 }
3073 /* free all the dma pools */
3075 {
3082 }
3085 /* create dma pools on init */
3087 {
3092 /* consistent DMA mode setting ? */
3098 }
3100 /* DMA setup */
3106 }
3108 /* EP0 in dma regs = dev control regs */
3111 /* dma desc for setup data */
3118 }
3119 /* setup */
3125 }
3128 /* data: 0 packets !? */
3134 }
3138 err_alloc_phys:
3141 err_alloc_dma:
3144 err_create_dma_pool:
3148 }
3151 /* general probe */
3153 {
3155 u32 reg;
3158 /* device struct setup */
3165 /* init registers, interrupts, ... */
3172 /* Print this device info for AMD chips only*/
3184 }
3187 }
3192 gadget_release);
3196 /* timer init */
3200 /* set SD */
3205 /* print dev register info */
3210 finished:
3212 }