drivers/usb/host/ehci-fsl.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc.
   3  * Copyright (c) 2005 MontaVista Software
   4  */
   5 #ifndef _EHCI_FSL_H
   6 #define _EHCI_FSL_H
   7
   8 /* offsets for the non-ehci registers in the FSL SOC USB controller */
   9 #define FSL_SOC_USB_SBUSCFG     0x90
  10 #define SBUSCFG_INCR8           0x02    /* INCR8, specified */
  11 #define FSL_SOC_USB_ULPIVP      0x170
  12 #define FSL_SOC_USB_PORTSC1     0x184
  13 #define PORT_PTS_MSK            (3<<30)
  14 #define PORT_PTS_UTMI           (0<<30)
  15 #define PORT_PTS_ULPI           (2<<30)
  16 #define PORT_PTS_SERIAL         (3<<30)
  17 #define PORT_PTS_PTW            (1<<28)
  18 #define FSL_SOC_USB_PORTSC2     0x188
  19 #define FSL_SOC_USB_USBMODE     0x1a8
  20 #define USBMODE_CM_MASK         (3 << 0)        /* controller mode mask */
  21 #define USBMODE_CM_HOST         (3 << 0)        /* controller mode: host */
  22 #define USBMODE_ES              (1 << 2)        /* (Big) Endian Select */
  23
  24 #define FSL_SOC_USB_USBGENCTRL  0x200
  25 #define USBGENCTRL_PPP          (1 << 3)
  26 #define USBGENCTRL_PFP          (1 << 2)
  27 #define FSL_SOC_USB_ISIPHYCTRL  0x204
  28 #define ISIPHYCTRL_PXE          (1)
  29 #define ISIPHYCTRL_PHYE         (1 << 4)
  30
  31 #define FSL_SOC_USB_SNOOP1      0x400   /* NOTE: big-endian */
  32 #define FSL_SOC_USB_SNOOP2      0x404   /* NOTE: big-endian */
  33 #define FSL_SOC_USB_AGECNTTHRSH 0x408   /* NOTE: big-endian */
  34 #define FSL_SOC_USB_PRICTRL     0x40c   /* NOTE: big-endian */
  35 #define FSL_SOC_USB_SICTRL      0x410   /* NOTE: big-endian */
  36 #define FSL_SOC_USB_CTRL        0x500   /* NOTE: big-endian */
  37 #define CTRL_UTMI_PHY_EN        (1<<9)
  38 #define CTRL_PHY_CLK_VALID      (1 << 17)
  39 #define SNOOP_SIZE_2GB          0x1e
  40
  41 /* control Register Bit Masks */
  42 #define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */
  43 #define ULPI_INT_EN             (1<<0)
  44 #define WU_INT_EN               (1<<1)
  45 #define USB_CTRL_USB_EN         (1<<2)
  46 #define LINE_STATE_FILTER__EN   (1<<3)
  47 #define KEEP_OTG_ON             (1<<4)
  48 #define OTG_PORT                (1<<5)
  49 #define PLL_RESET               (1<<8)
  50 #define UTMI_PHY_EN             (1<<9)
  51 #define ULPI_PHY_CLK_SEL        (1<<10)
  52 #define PHY_CLK_VALID           (1<<17)
  53
  54 /* Retry count for checking UTMI PHY CLK validity */
  55 #define UTMI_PHY_CLK_VALID_CHK_RETRY 5
  56 #endif                          /* _EHCI_FSL_H */