drivers/video/fbdev/core/svgalib.c

   1 /*
   2  * Common utility functions for VGA-based graphics cards.
   3  *
   4  * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file COPYING in the main directory of this archive for
   8  * more details.
   9  *
  10  * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/string.h>
  16 #include <linux/fb.h>
  17 #include <linux/svga.h>
  18 #include <asm/types.h>
  19 #include <asm/io.h>
  20
  21
  22 /* Write a CRT register value spread across multiple registers */
  23 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
  24 {
  25         u8 regval, bitval, bitnum;
  26
  27         while (regset->regnum != VGA_REGSET_END_VAL) {
  28                 regval = vga_rcrt(regbase, regset->regnum);
  29                 bitnum = regset->lowbit;
  30                 while (bitnum <= regset->highbit) {
  31                         bitval = 1 << bitnum;
  32                         regval = regval & ~bitval;
  33                         if (value & 1) regval = regval | bitval;
  34                         bitnum ++;
  35                         value = value >> 1;
  36                 }
  37                 vga_wcrt(regbase, regset->regnum, regval);
  38                 regset ++;
  39         }
  40 }
  41
  42 /* Write a sequencer register value spread across multiple registers */
  43 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
  44 {
  45         u8 regval, bitval, bitnum;
  46
  47         while (regset->regnum != VGA_REGSET_END_VAL) {
  48                 regval = vga_rseq(regbase, regset->regnum);
  49                 bitnum = regset->lowbit;
  50                 while (bitnum <= regset->highbit) {
  51                         bitval = 1 << bitnum;
  52                         regval = regval & ~bitval;
  53                         if (value & 1) regval = regval | bitval;
  54                         bitnum ++;
  55                         value = value >> 1;
  56                 }
  57                 vga_wseq(regbase, regset->regnum, regval);
  58                 regset ++;
  59         }
  60 }
  61
  62 static unsigned int svga_regset_size(const struct vga_regset *regset)
  63 {
  64         u8 count = 0;
  65
  66         while (regset->regnum != VGA_REGSET_END_VAL) {
  67                 count += regset->highbit - regset->lowbit + 1;
  68                 regset ++;
  69         }
  70         return 1 << count;
  71 }
  72
  73
  74 /* ------------------------------------------------------------------------- */
  75
  76
  77 /* Set graphics controller registers to sane values */
  78 void svga_set_default_gfx_regs(void __iomem *regbase)
  79 {
  80         /* All standard GFX registers (GR00 - GR08) */
  81         vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00);
  82         vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00);
  83         vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00);
  84         vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00);
  85         vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00);
  86         vga_wgfx(regbase, VGA_GFX_MODE, 0x00);
  87 /*      vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */
  88 /*      vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */
  89         vga_wgfx(regbase, VGA_GFX_MISC, 0x05);
  90 /*      vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */
  91         vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F);
  92         vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF);
  93 }
  94
  95 /* Set attribute controller registers to sane values */
  96 void svga_set_default_atc_regs(void __iomem *regbase)
  97 {
  98         u8 count;
  99
 100         vga_r(regbase, 0x3DA);
 101         vga_w(regbase, VGA_ATT_W, 0x00);
 102
 103         /* All standard ATC registers (AR00 - AR14) */
 104         for (count = 0; count <= 0xF; count ++)
 105                 svga_wattr(regbase, count, count);
 106
 107         svga_wattr(regbase, VGA_ATC_MODE, 0x01);
 108 /*      svga_wattr(regbase, VGA_ATC_MODE, 0x41); */
 109         svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00);
 110         svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F);
 111         svga_wattr(regbase, VGA_ATC_PEL, 0x00);
 112         svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00);
 113
 114         vga_r(regbase, 0x3DA);
 115         vga_w(regbase, VGA_ATT_W, 0x20);
 116 }
 117
 118 /* Set sequencer registers to sane values */
 119 void svga_set_default_seq_regs(void __iomem *regbase)
 120 {
 121         /* Standard sequencer registers (SR01 - SR04), SR00 is not set */
 122         vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
 123         vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
 124         vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
 125 /*      vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
 126         vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
 127 }
 128
 129 /* Set CRTC registers to sane values */
 130 void svga_set_default_crt_regs(void __iomem *regbase)
 131 {
 132         /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
 133         svga_wcrt_mask(regbase, 0x03, 0x80, 0x80);      /* Enable vertical retrace EVRA */
 134         vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
 135         svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F);
 136         vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
 137         vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3);
 138 }
 139
 140 void svga_set_textmode_vga_regs(void __iomem *regbase)
 141 {
 142         /* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */   /* Switch 8/9 pixel per char */
 143         vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
 144         vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03);
 145
 146         vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
 147         vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f);
 148         svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f);
 149
 150         vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d);
 151         vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e);
 152         vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00);
 153         vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00);
 154
 155         vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
 156         vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
 157         vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00);
 158
 159         vga_r(regbase, 0x3DA);
 160         vga_w(regbase, VGA_ATT_W, 0x00);
 161
 162         svga_wattr(regbase, 0x10, 0x0C);                        /* Attribute Mode Control Register - text mode, blinking and line graphics */
 163         svga_wattr(regbase, 0x13, 0x08);                        /* Horizontal Pixel Panning Register  */
 164
 165         vga_r(regbase, 0x3DA);
 166         vga_w(regbase, VGA_ATT_W, 0x20);
 167 }
 168
 169 #if 0
 170 void svga_dump_var(struct fb_var_screeninfo *var, int node)
 171 {
 172         pr_debug("fb%d: var.vmode         : 0x%X\n", node, var->vmode);
 173         pr_debug("fb%d: var.xres          : %d\n", node, var->xres);
 174         pr_debug("fb%d: var.yres          : %d\n", node, var->yres);
 175         pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
 176         pr_debug("fb%d: var.xres_virtual  : %d\n", node, var->xres_virtual);
 177         pr_debug("fb%d: var.yres_virtual  : %d\n", node, var->yres_virtual);
 178         pr_debug("fb%d: var.left_margin   : %d\n", node, var->left_margin);
 179         pr_debug("fb%d: var.right_margin  : %d\n", node, var->right_margin);
 180         pr_debug("fb%d: var.upper_margin  : %d\n", node, var->upper_margin);
 181         pr_debug("fb%d: var.lower_margin  : %d\n", node, var->lower_margin);
 182         pr_debug("fb%d: var.hsync_len     : %d\n", node, var->hsync_len);
 183         pr_debug("fb%d: var.vsync_len     : %d\n", node, var->vsync_len);
 184         pr_debug("fb%d: var.sync          : 0x%X\n", node, var->sync);
 185         pr_debug("fb%d: var.pixclock      : %d\n\n", node, var->pixclock);
 186 }
 187 #endif  /*  0  */
 188
 189
 190 /* ------------------------------------------------------------------------- */
 191
 192
 193 void svga_settile(struct fb_info *info, struct fb_tilemap *map)
 194 {
 195         const u8 *font = map->data;
 196         u8 __iomem *fb = (u8 __iomem *)info->screen_base;
 197         int i, c;
 198
 199         if ((map->width != 8) || (map->height != 16) ||
 200             (map->depth != 1) || (map->length != 256)) {
 201                 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
 202                        map->width, map->height, map->depth, map->length);
 203                 return;
 204         }
 205
 206         fb += 2;
 207         for (c = 0; c < map->length; c++) {
 208                 for (i = 0; i < map->height; i++) {
 209                         fb_writeb(font[i], fb + i * 4);
 210 //                      fb[i * 4] = font[i];
 211                 }
 212                 fb += 128;
 213                 font += map->height;
 214         }
 215 }
 216
 217 /* Copy area in text (tileblit) mode */
 218 void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
 219 {
 220         int dx, dy;
 221         /*  colstride is halved in this function because u16 are used */
 222         int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
 223         int rowstride = colstride * (info->var.xres_virtual / 8);
 224         u16 __iomem *fb = (u16 __iomem *) info->screen_base;
 225         u16 __iomem *src, *dst;
 226
 227         if ((area->sy > area->dy) ||
 228             ((area->sy == area->dy) && (area->sx > area->dx))) {
 229                 src = fb + area->sx * colstride + area->sy * rowstride;
 230                 dst = fb + area->dx * colstride + area->dy * rowstride;
 231             } else {
 232                 src = fb + (area->sx + area->width - 1) * colstride
 233                          + (area->sy + area->height - 1) * rowstride;
 234                 dst = fb + (area->dx + area->width - 1) * colstride
 235                          + (area->dy + area->height - 1) * rowstride;
 236
 237                 colstride = -colstride;
 238                 rowstride = -rowstride;
 239             }
 240
 241         for (dy = 0; dy < area->height; dy++) {
 242                 u16 __iomem *src2 = src;
 243                 u16 __iomem *dst2 = dst;
 244                 for (dx = 0; dx < area->width; dx++) {
 245                         fb_writew(fb_readw(src2), dst2);
 246 //                      *dst2 = *src2;
 247                         src2 += colstride;
 248                         dst2 += colstride;
 249                 }
 250                 src += rowstride;
 251                 dst += rowstride;
 252         }
 253 }
 254
 255 /* Fill area in text (tileblit) mode */
 256 void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
 257 {
 258         int dx, dy;
 259         int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
 260         int rowstride = colstride * (info->var.xres_virtual / 8);
 261         int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
 262         u8 __iomem *fb = (u8 __iomem *)info->screen_base;
 263         fb += rect->sx * colstride + rect->sy * rowstride;
 264
 265         for (dy = 0; dy < rect->height; dy++) {
 266                 u8 __iomem *fb2 = fb;
 267                 for (dx = 0; dx < rect->width; dx++) {
 268                         fb_writeb(rect->index, fb2);
 269                         fb_writeb(attr, fb2 + 1);
 270                         fb2 += colstride;
 271                 }
 272                 fb += rowstride;
 273         }
 274 }
 275
 276 /* Write text in text (tileblit) mode */
 277 void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
 278 {
 279         int dx, dy, i;
 280         int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
 281         int rowstride = colstride * (info->var.xres_virtual / 8);
 282         int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
 283         u8 __iomem *fb = (u8 __iomem *)info->screen_base;
 284         fb += blit->sx * colstride + blit->sy * rowstride;
 285
 286         i=0;
 287         for (dy=0; dy < blit->height; dy ++) {
 288                 u8 __iomem *fb2 = fb;
 289                 for (dx = 0; dx < blit->width; dx ++) {
 290                         fb_writeb(blit->indices[i], fb2);
 291                         fb_writeb(attr, fb2 + 1);
 292                         fb2 += colstride;
 293                         i ++;
 294                         if (i == blit->length) return;
 295                 }
 296                 fb += rowstride;
 297         }
 298
 299 }
 300
 301 /* Set cursor in text (tileblit) mode */
 302 void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor)
 303 {
 304         u8 cs = 0x0d;
 305         u8 ce = 0x0e;
 306         u16 pos =  cursor->sx + (info->var.xoffset /  8)
 307                 + (cursor->sy + (info->var.yoffset / 16))
 308                    * (info->var.xres_virtual / 8);
 309
 310         if (! cursor -> mode)
 311                 return;
 312
 313         svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */
 314
 315         if (cursor -> shape == FB_TILE_CURSOR_NONE)
 316                 return;
 317
 318         switch (cursor -> shape) {
 319         case FB_TILE_CURSOR_UNDERLINE:
 320                 cs = 0x0d;
 321                 break;
 322         case FB_TILE_CURSOR_LOWER_THIRD:
 323                 cs = 0x09;
 324                 break;
 325         case FB_TILE_CURSOR_LOWER_HALF:
 326                 cs = 0x07;
 327                 break;
 328         case FB_TILE_CURSOR_TWO_THIRDS:
 329                 cs = 0x05;
 330                 break;
 331         case FB_TILE_CURSOR_BLOCK:
 332                 cs = 0x01;
 333                 break;
 334         }
 335
 336         /* set cursor position */
 337         vga_wcrt(regbase, 0x0E, pos >> 8);
 338         vga_wcrt(regbase, 0x0F, pos & 0xFF);
 339
 340         vga_wcrt(regbase, 0x0B, ce); /* set cursor end */
 341         vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */
 342 }
 343
 344 int svga_get_tilemax(struct fb_info *info)
 345 {
 346         return 256;
 347 }
 348
 349 /* Get capabilities of accelerator based on the mode */
 350
 351 void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps,
 352                    struct fb_var_screeninfo *var)
 353 {
 354         if (var->bits_per_pixel == 0) {
 355                 /* can only support 256 8x16 bitmap */
 356                 caps->x = 1 << (8 - 1);
 357                 caps->y = 1 << (16 - 1);
 358                 caps->len = 256;
 359         } else {
 360                 caps->x = (var->bits_per_pixel == 4) ? 1 << (8 - 1) : ~(u32)0;
 361                 caps->y = ~(u32)0;
 362                 caps->len = ~(u32)0;
 363         }
 364 }
 365 EXPORT_SYMBOL(svga_get_caps);
 366
 367 /* ------------------------------------------------------------------------- */
 368
 369
 370 /*
 371  *  Compute PLL settings (M, N, R)
 372  *  F_VCO = (F_BASE * M) / N
 373  *  F_OUT = F_VCO / (2^R)
 374  */
 375
 376 static inline u32 abs_diff(u32 a, u32 b)
 377 {
 378         return (a > b) ? (a - b) : (b - a);
 379 }
 380
 381 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
 382 {
 383         u16 am, an, ar;
 384         u32 f_vco, f_current, delta_current, delta_best;
 385
 386         pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted);
 387
 388         ar = pll->r_max;
 389         f_vco = f_wanted << ar;
 390
 391         /* overflow check */
 392         if ((f_vco >> ar) != f_wanted)
 393                 return -EINVAL;
 394
 395         /* It is usually better to have greater VCO clock
 396            because of better frequency stability.
 397            So first try r_max, then r smaller. */
 398         while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
 399                 ar--;
 400                 f_vco = f_vco >> 1;
 401         }
 402
 403         /* VCO bounds check */
 404         if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
 405                 return -EINVAL;
 406
 407         delta_best = 0xFFFFFFFF;
 408         *m = 0;
 409         *n = 0;
 410         *r = ar;
 411
 412         am = pll->m_min;
 413         an = pll->n_min;
 414
 415         while ((am <= pll->m_max) && (an <= pll->n_max)) {
 416                 f_current = (pll->f_base * am) / an;
 417                 delta_current = abs_diff (f_current, f_vco);
 418
 419                 if (delta_current < delta_best) {
 420                         delta_best = delta_current;
 421                         *m = am;
 422                         *n = an;
 423                 }
 424
 425                 if (f_current <= f_vco) {
 426                         am ++;
 427                 } else {
 428                         an ++;
 429                 }
 430         }
 431
 432         f_current = (pll->f_base * *m) / *n;
 433         pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current);
 434         pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r);
 435         return 0;
 436 }
 437
 438
 439 /* ------------------------------------------------------------------------- */
 440
 441
 442 /* Check CRT timing values */
 443 int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
 444 {
 445         u32 value;
 446
 447         var->xres         = (var->xres+7)&~7;
 448         var->left_margin  = (var->left_margin+7)&~7;
 449         var->right_margin = (var->right_margin+7)&~7;
 450         var->hsync_len    = (var->hsync_len+7)&~7;
 451
 452         /* Check horizontal total */
 453         value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
 454         if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs))
 455                 return -EINVAL;
 456
 457         /* Check horizontal display and blank start */
 458         value = var->xres;
 459         if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs))
 460                 return -EINVAL;
 461         if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs))
 462                 return -EINVAL;
 463
 464         /* Check horizontal sync start */
 465         value = var->xres + var->right_margin;
 466         if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs))
 467                 return -EINVAL;
 468
 469         /* Check horizontal blank end (or length) */
 470         value = var->left_margin + var->right_margin + var->hsync_len;
 471         if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs)))
 472                 return -EINVAL;
 473
 474         /* Check horizontal sync end (or length) */
 475         value = var->hsync_len;
 476         if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs)))
 477                 return -EINVAL;
 478
 479         /* Check vertical total */
 480         value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 481         if ((value - 1) >= svga_regset_size(tm->v_total_regs))
 482                 return -EINVAL;
 483
 484         /* Check vertical display and blank start */
 485         value = var->yres;
 486         if ((value - 1) >= svga_regset_size(tm->v_display_regs))
 487                 return -EINVAL;
 488         if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
 489                 return -EINVAL;
 490
 491         /* Check vertical sync start */
 492         value = var->yres + var->lower_margin;
 493         if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
 494                 return -EINVAL;
 495
 496         /* Check vertical blank end (or length) */
 497         value = var->upper_margin + var->lower_margin + var->vsync_len;
 498         if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs)))
 499                 return -EINVAL;
 500
 501         /* Check vertical sync end  (or length) */
 502         value = var->vsync_len;
 503         if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs)))
 504                 return -EINVAL;
 505
 506         return 0;
 507 }
 508
 509 /* Set CRT timing registers */
 510 void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm,
 511                       struct fb_var_screeninfo *var,
 512                       u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
 513 {
 514         u8 regval;
 515         u32 value;
 516
 517         value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
 518         value = (value * hmul) / hdiv;
 519         pr_debug("fb%d: horizontal total      : %d\n", node, value);
 520         svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5);
 521
 522         value = var->xres;
 523         value = (value * hmul) / hdiv;
 524         pr_debug("fb%d: horizontal display    : %d\n", node, value);
 525         svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1);
 526
 527         value = var->xres;
 528         value = (value * hmul) / hdiv;
 529         pr_debug("fb%d: horizontal blank start: %d\n", node, value);
 530         svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder);
 531
 532         value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
 533         value = (value * hmul) / hdiv;
 534         pr_debug("fb%d: horizontal blank end  : %d\n", node, value);
 535         svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder);
 536
 537         value = var->xres + var->right_margin;
 538         value = (value * hmul) / hdiv;
 539         pr_debug("fb%d: horizontal sync start : %d\n", node, value);
 540         svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8));
 541
 542         value = var->xres + var->right_margin + var->hsync_len;
 543         value = (value * hmul) / hdiv;
 544         pr_debug("fb%d: horizontal sync end   : %d\n", node, value);
 545         svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8));
 546
 547         value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 548         value = (value * vmul) / vdiv;
 549         pr_debug("fb%d: vertical total        : %d\n", node, value);
 550         svga_wcrt_multi(regbase, tm->v_total_regs, value - 2);
 551
 552         value = var->yres;
 553         value = (value * vmul) / vdiv;
 554         pr_debug("fb%d: vertical display      : %d\n", node, value);
 555         svga_wcrt_multi(regbase, tm->v_display_regs, value - 1);
 556
 557         value = var->yres;
 558         value = (value * vmul) / vdiv;
 559         pr_debug("fb%d: vertical blank start  : %d\n", node, value);
 560         svga_wcrt_multi(regbase, tm->v_blank_start_regs, value);
 561
 562         value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 563         value = (value * vmul) / vdiv;
 564         pr_debug("fb%d: vertical blank end    : %d\n", node, value);
 565         svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2);
 566
 567         value = var->yres + var->lower_margin;
 568         value = (value * vmul) / vdiv;
 569         pr_debug("fb%d: vertical sync start   : %d\n", node, value);
 570         svga_wcrt_multi(regbase, tm->v_sync_start_regs, value);
 571
 572         value = var->yres + var->lower_margin + var->vsync_len;
 573         value = (value * vmul) / vdiv;
 574         pr_debug("fb%d: vertical sync end     : %d\n", node, value);
 575         svga_wcrt_multi(regbase, tm->v_sync_end_regs, value);
 576
 577         /* Set horizontal and vertical sync pulse polarity in misc register */
 578
 579         regval = vga_r(regbase, VGA_MIS_R);
 580         if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
 581                 pr_debug("fb%d: positive horizontal sync\n", node);
 582                 regval = regval & ~0x80;
 583         } else {
 584                 pr_debug("fb%d: negative horizontal sync\n", node);
 585                 regval = regval | 0x80;
 586         }
 587         if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
 588                 pr_debug("fb%d: positive vertical sync\n", node);
 589                 regval = regval & ~0x40;
 590         } else {
 591                 pr_debug("fb%d: negative vertical sync\n\n", node);
 592                 regval = regval | 0x40;
 593         }
 594         vga_w(regbase, VGA_MIS_W, regval);
 595 }
 596
 597
 598 /* ------------------------------------------------------------------------- */
 599
 600
 601 static inline int match_format(const struct svga_fb_format *frm,
 602                                struct fb_var_screeninfo *var)
 603 {
 604         int i = 0;
 605         int stored = -EINVAL;
 606
 607         while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL)
 608         {
 609                 if ((var->bits_per_pixel == frm->bits_per_pixel) &&
 610                     (var->red.length     <= frm->red.length)     &&
 611                     (var->green.length   <= frm->green.length)   &&
 612                     (var->blue.length    <= frm->blue.length)    &&
 613                     (var->transp.length  <= frm->transp.length)  &&
 614                     (var->nonstd         == frm->nonstd))
 615                         return i;
 616                 if (var->bits_per_pixel == frm->bits_per_pixel)
 617                         stored = i;
 618                 i++;
 619                 frm++;
 620         }
 621         return stored;
 622 }
 623
 624 int svga_match_format(const struct svga_fb_format *frm,
 625                       struct fb_var_screeninfo *var,
 626                       struct fb_fix_screeninfo *fix)
 627 {
 628         int i = match_format(frm, var);
 629
 630         if (i >= 0) {
 631                 var->bits_per_pixel = frm[i].bits_per_pixel;
 632                 var->red            = frm[i].red;
 633                 var->green          = frm[i].green;
 634                 var->blue           = frm[i].blue;
 635                 var->transp         = frm[i].transp;
 636                 var->nonstd         = frm[i].nonstd;
 637                 if (fix != NULL) {
 638                         fix->type      = frm[i].type;
 639                         fix->type_aux  = frm[i].type_aux;
 640                         fix->visual    = frm[i].visual;
 641                         fix->xpanstep  = frm[i].xpanstep;
 642                 }
 643         }
 644
 645         return i;
 646 }
 647
 648
 649 EXPORT_SYMBOL(svga_wcrt_multi);
 650 EXPORT_SYMBOL(svga_wseq_multi);
 651
 652 EXPORT_SYMBOL(svga_set_default_gfx_regs);
 653 EXPORT_SYMBOL(svga_set_default_atc_regs);
 654 EXPORT_SYMBOL(svga_set_default_seq_regs);
 655 EXPORT_SYMBOL(svga_set_default_crt_regs);
 656 EXPORT_SYMBOL(svga_set_textmode_vga_regs);
 657
 658 EXPORT_SYMBOL(svga_settile);
 659 EXPORT_SYMBOL(svga_tilecopy);
 660 EXPORT_SYMBOL(svga_tilefill);
 661 EXPORT_SYMBOL(svga_tileblit);
 662 EXPORT_SYMBOL(svga_tilecursor);
 663 EXPORT_SYMBOL(svga_get_tilemax);
 664
 665 EXPORT_SYMBOL(svga_compute_pll);
 666 EXPORT_SYMBOL(svga_check_timings);
 667 EXPORT_SYMBOL(svga_set_timings);
 668 EXPORT_SYMBOL(svga_match_format);
 669
 670 MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>");
 671 MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
 672 MODULE_LICENSE("GPL");