| blob | e1374e180943e3b11bdc6df04552c07c52b5ef1b |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
5 */
7 #ifndef __DTS_HI3660_CLOCK_H
8 #define __DTS_HI3660_CLOCK_H
10 /* fixed rate clocks */
11 #define HI3660_CLKIN_SYS 0
12 #define HI3660_CLKIN_REF 1
13 #define HI3660_CLK_FLL_SRC 2
14 #define HI3660_CLK_PPLL0 3
15 #define HI3660_CLK_PPLL1 4
16 #define HI3660_CLK_PPLL2 5
17 #define HI3660_CLK_PPLL3 6
18 #define HI3660_CLK_SCPLL 7
19 #define HI3660_PCLK 8
20 #define HI3660_CLK_UART0_DBG 9
21 #define HI3660_CLK_UART6 10
22 #define HI3660_OSC32K 11
23 #define HI3660_OSC19M 12
24 #define HI3660_CLK_480M 13
25 #define HI3660_CLK_INV 14
27 /* clk in crgctrl */
28 #define HI3660_FACTOR_UART3 15
29 #define HI3660_CLK_FACTOR_MMC 16
30 #define HI3660_CLK_GATE_I2C0 17
31 #define HI3660_CLK_GATE_I2C1 18
32 #define HI3660_CLK_GATE_I2C2 19
33 #define HI3660_CLK_GATE_I2C6 20
34 #define HI3660_CLK_DIV_SYSBUS 21
35 #define HI3660_CLK_DIV_320M 22
36 #define HI3660_CLK_DIV_A53 23
37 #define HI3660_CLK_GATE_SPI0 24
38 #define HI3660_CLK_GATE_SPI2 25
39 #define HI3660_PCIEPHY_REF 26
40 #define HI3660_CLK_ABB_USB 27
41 #define HI3660_HCLK_GATE_SDIO0 28
42 #define HI3660_HCLK_GATE_SD 29
43 #define HI3660_CLK_GATE_AOMM 30
44 #define HI3660_PCLK_GPIO0 31
45 #define HI3660_PCLK_GPIO1 32
46 #define HI3660_PCLK_GPIO2 33
47 #define HI3660_PCLK_GPIO3 34
48 #define HI3660_PCLK_GPIO4 35
49 #define HI3660_PCLK_GPIO5 36
50 #define HI3660_PCLK_GPIO6 37
51 #define HI3660_PCLK_GPIO7 38
52 #define HI3660_PCLK_GPIO8 39
53 #define HI3660_PCLK_GPIO9 40
54 #define HI3660_PCLK_GPIO10 41
55 #define HI3660_PCLK_GPIO11 42
56 #define HI3660_PCLK_GPIO12 43
57 #define HI3660_PCLK_GPIO13 44
58 #define HI3660_PCLK_GPIO14 45
59 #define HI3660_PCLK_GPIO15 46
60 #define HI3660_PCLK_GPIO16 47
61 #define HI3660_PCLK_GPIO17 48
62 #define HI3660_PCLK_GPIO18 49
63 #define HI3660_PCLK_GPIO19 50
64 #define HI3660_PCLK_GPIO20 51
65 #define HI3660_PCLK_GPIO21 52
66 #define HI3660_CLK_GATE_SPI3 53
67 #define HI3660_CLK_GATE_I2C7 54
68 #define HI3660_CLK_GATE_I2C3 55
69 #define HI3660_CLK_GATE_SPI1 56
70 #define HI3660_CLK_GATE_UART1 57
71 #define HI3660_CLK_GATE_UART2 58
72 #define HI3660_CLK_GATE_UART4 59
73 #define HI3660_CLK_GATE_UART5 60
74 #define HI3660_CLK_GATE_I2C4 61
75 #define HI3660_CLK_GATE_DMAC 62
76 #define HI3660_PCLK_GATE_DSS 63
77 #define HI3660_ACLK_GATE_DSS 64
78 #define HI3660_CLK_GATE_LDI1 65
79 #define HI3660_CLK_GATE_LDI0 66
80 #define HI3660_CLK_GATE_VIVOBUS 67
81 #define HI3660_CLK_GATE_EDC0 68
82 #define HI3660_CLK_GATE_TXDPHY0_CFG 69
83 #define HI3660_CLK_GATE_TXDPHY0_REF 70
84 #define HI3660_CLK_GATE_TXDPHY1_CFG 71
85 #define HI3660_CLK_GATE_TXDPHY1_REF 72
86 #define HI3660_ACLK_GATE_USB3OTG 73
87 #define HI3660_CLK_GATE_SPI4 74
88 #define HI3660_CLK_GATE_SD 75
89 #define HI3660_CLK_GATE_SDIO0 76
90 #define HI3660_CLK_GATE_UFS_SUBSYS 77
91 #define HI3660_PCLK_GATE_DSI0 78
92 #define HI3660_PCLK_GATE_DSI1 79
93 #define HI3660_ACLK_GATE_PCIE 80
94 #define HI3660_PCLK_GATE_PCIE_SYS 81
95 #define HI3660_CLK_GATE_PCIEAUX 82
96 #define HI3660_PCLK_GATE_PCIE_PHY 83
97 #define HI3660_CLK_ANDGT_LDI0 84
98 #define HI3660_CLK_ANDGT_LDI1 85
99 #define HI3660_CLK_ANDGT_EDC0 86
100 #define HI3660_CLK_GATE_UFSPHY_GT 87
101 #define HI3660_CLK_ANDGT_MMC 88
102 #define HI3660_CLK_ANDGT_SD 89
103 #define HI3660_CLK_A53HPM_ANDGT 90
104 #define HI3660_CLK_ANDGT_SDIO 91
105 #define HI3660_CLK_ANDGT_UART0 92
106 #define HI3660_CLK_ANDGT_UART1 93
107 #define HI3660_CLK_ANDGT_UARTH 94
108 #define HI3660_CLK_ANDGT_SPI 95
109 #define HI3660_CLK_VIVOBUS_ANDGT 96
110 #define HI3660_CLK_AOMM_ANDGT 97
111 #define HI3660_CLK_320M_PLL_GT 98
112 #define HI3660_AUTODIV_EMMC0BUS 99
113 #define HI3660_AUTODIV_SYSBUS 100
114 #define HI3660_CLK_GATE_UFSPHY_CFG 101
115 #define HI3660_CLK_GATE_UFSIO_REF 102
116 #define HI3660_CLK_MUX_SYSBUS 103
117 #define HI3660_CLK_MUX_UART0 104
118 #define HI3660_CLK_MUX_UART1 105
119 #define HI3660_CLK_MUX_UARTH 106
120 #define HI3660_CLK_MUX_SPI 107
121 #define HI3660_CLK_MUX_I2C 108
122 #define HI3660_CLK_MUX_MMC_PLL 109
123 #define HI3660_CLK_MUX_LDI1 110
124 #define HI3660_CLK_MUX_LDI0 111
125 #define HI3660_CLK_MUX_SD_PLL 112
126 #define HI3660_CLK_MUX_SD_SYS 113
127 #define HI3660_CLK_MUX_EDC0 114
128 #define HI3660_CLK_MUX_SDIO_SYS 115
129 #define HI3660_CLK_MUX_SDIO_PLL 116
130 #define HI3660_CLK_MUX_VIVOBUS 117
131 #define HI3660_CLK_MUX_A53HPM 118
132 #define HI3660_CLK_MUX_320M 119
133 #define HI3660_CLK_MUX_IOPERI 120
134 #define HI3660_CLK_DIV_UART0 121
135 #define HI3660_CLK_DIV_UART1 122
136 #define HI3660_CLK_DIV_UARTH 123
137 #define HI3660_CLK_DIV_MMC 124
138 #define HI3660_CLK_DIV_SD 125
139 #define HI3660_CLK_DIV_EDC0 126
140 #define HI3660_CLK_DIV_LDI0 127
141 #define HI3660_CLK_DIV_SDIO 128
142 #define HI3660_CLK_DIV_LDI1 129
143 #define HI3660_CLK_DIV_SPI 130
144 #define HI3660_CLK_DIV_VIVOBUS 131
145 #define HI3660_CLK_DIV_I2C 132
146 #define HI3660_CLK_DIV_UFSPHY 133
147 #define HI3660_CLK_DIV_CFGBUS 134
148 #define HI3660_CLK_DIV_MMC0BUS 135
149 #define HI3660_CLK_DIV_MMC1BUS 136
150 #define HI3660_CLK_DIV_UFSPERI 137
151 #define HI3660_CLK_DIV_AOMM 138
152 #define HI3660_CLK_DIV_IOPERI 139
153 #define HI3660_VENC_VOLT_HOLD 140
154 #define HI3660_PERI_VOLT_HOLD 141
155 #define HI3660_CLK_GATE_VENC 142
156 #define HI3660_CLK_GATE_VDEC 143
157 #define HI3660_CLK_ANDGT_VENC 144
158 #define HI3660_CLK_ANDGT_VDEC 145
159 #define HI3660_CLK_MUX_VENC 146
160 #define HI3660_CLK_MUX_VDEC 147
161 #define HI3660_CLK_DIV_VENC 148
162 #define HI3660_CLK_DIV_VDEC 149
163 #define HI3660_CLK_FAC_ISP_SNCLK 150
164 #define HI3660_CLK_GATE_ISP_SNCLK0 151
165 #define HI3660_CLK_GATE_ISP_SNCLK1 152
166 #define HI3660_CLK_GATE_ISP_SNCLK2 153
167 #define HI3660_CLK_ANGT_ISP_SNCLK 154
168 #define HI3660_CLK_MUX_ISP_SNCLK 155
169 #define HI3660_CLK_DIV_ISP_SNCLK 156
171 /* clk in pmuctrl */
172 #define HI3660_GATE_ABB_192 0
174 /* clk in pctrl */
175 #define HI3660_GATE_UFS_TCXO_EN 0
176 #define HI3660_GATE_USB_TCXO_EN 1
178 /* clk in sctrl */
179 #define HI3660_PCLK_AO_GPIO0 0
180 #define HI3660_PCLK_AO_GPIO1 1
181 #define HI3660_PCLK_AO_GPIO2 2
182 #define HI3660_PCLK_AO_GPIO3 3
183 #define HI3660_PCLK_AO_GPIO4 4
184 #define HI3660_PCLK_AO_GPIO5 5
185 #define HI3660_PCLK_AO_GPIO6 6
186 #define HI3660_PCLK_GATE_MMBUF 7
187 #define HI3660_CLK_GATE_DSS_AXI_MM 8
188 #define HI3660_PCLK_MMBUF_ANDGT 9
189 #define HI3660_CLK_MMBUF_PLL_ANDGT 10
190 #define HI3660_CLK_FLL_MMBUF_ANDGT 11
191 #define HI3660_CLK_SYS_MMBUF_ANDGT 12
192 #define HI3660_CLK_GATE_PCIEPHY_GT 13
193 #define HI3660_ACLK_MUX_MMBUF 14
194 #define HI3660_CLK_SW_MMBUF 15
195 #define HI3660_CLK_DIV_AOBUS 16
196 #define HI3660_PCLK_DIV_MMBUF 17
197 #define HI3660_ACLK_DIV_MMBUF 18
198 #define HI3660_CLK_DIV_PCIEPHY 19
200 /* clk in iomcu */
201 #define HI3660_CLK_I2C0_IOMCU 0
202 #define HI3660_CLK_I2C1_IOMCU 1
203 #define HI3660_CLK_I2C2_IOMCU 2
204 #define HI3660_CLK_I2C6_IOMCU 3
205 #define HI3660_CLK_IOMCU_PERI0 4
207 /* clk in stub clock */
208 #define HI3660_CLK_STUB_CLUSTER0 0
209 #define HI3660_CLK_STUB_CLUSTER1 1
210 #define HI3660_CLK_STUB_GPU 2
211 #define HI3660_CLK_STUB_DDR 3
212 #define HI3660_CLK_STUB_NUM 4