| blob | 264d634d226e888157360e06ffb09474b1e40988 |
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2019 Xilinx Inc.
4 *
5 */
7 #ifndef _DT_BINDINGS_CLK_VERSAL_H
8 #define _DT_BINDINGS_CLK_VERSAL_H
10 #define PMC_PLL 1
11 #define APU_PLL 2
12 #define RPU_PLL 3
13 #define CPM_PLL 4
14 #define NOC_PLL 5
15 #define PLL_MAX 6
16 #define PMC_PRESRC 7
17 #define PMC_POSTCLK 8
18 #define PMC_PLL_OUT 9
19 #define PPLL 10
20 #define NOC_PRESRC 11
21 #define NOC_POSTCLK 12
22 #define NOC_PLL_OUT 13
23 #define NPLL 14
24 #define APU_PRESRC 15
25 #define APU_POSTCLK 16
26 #define APU_PLL_OUT 17
27 #define APLL 18
28 #define RPU_PRESRC 19
29 #define RPU_POSTCLK 20
30 #define RPU_PLL_OUT 21
31 #define RPLL 22
32 #define CPM_PRESRC 23
33 #define CPM_POSTCLK 24
34 #define CPM_PLL_OUT 25
35 #define CPLL 26
36 #define PPLL_TO_XPD 27
37 #define NPLL_TO_XPD 28
38 #define APLL_TO_XPD 29
39 #define RPLL_TO_XPD 30
40 #define EFUSE_REF 31
41 #define SYSMON_REF 32
42 #define IRO_SUSPEND_REF 33
43 #define USB_SUSPEND 34
44 #define SWITCH_TIMEOUT 35
45 #define RCLK_PMC 36
46 #define RCLK_LPD 37
47 #define WDT 38
48 #define TTC0 39
49 #define TTC1 40
50 #define TTC2 41
51 #define TTC3 42
52 #define GEM_TSU 43
53 #define GEM_TSU_LB 44
54 #define MUXED_IRO_DIV2 45
55 #define MUXED_IRO_DIV4 46
56 #define PSM_REF 47
57 #define GEM0_RX 48
58 #define GEM0_TX 49
59 #define GEM1_RX 50
60 #define GEM1_TX 51
61 #define CPM_CORE_REF 52
62 #define CPM_LSBUS_REF 53
63 #define CPM_DBG_REF 54
64 #define CPM_AUX0_REF 55
65 #define CPM_AUX1_REF 56
66 #define QSPI_REF 57
67 #define OSPI_REF 58
68 #define SDIO0_REF 59
69 #define SDIO1_REF 60
70 #define PMC_LSBUS_REF 61
71 #define I2C_REF 62
72 #define TEST_PATTERN_REF 63
73 #define DFT_OSC_REF 64
74 #define PMC_PL0_REF 65
75 #define PMC_PL1_REF 66
76 #define PMC_PL2_REF 67
77 #define PMC_PL3_REF 68
78 #define CFU_REF 69
79 #define SPARE_REF 70
80 #define NPI_REF 71
81 #define HSM0_REF 72
82 #define HSM1_REF 73
83 #define SD_DLL_REF 74
84 #define FPD_TOP_SWITCH 75
85 #define FPD_LSBUS 76
86 #define ACPU 77
87 #define DBG_TRACE 78
88 #define DBG_FPD 79
89 #define LPD_TOP_SWITCH 80
90 #define ADMA 81
91 #define LPD_LSBUS 82
92 #define CPU_R5 83
93 #define CPU_R5_CORE 84
94 #define CPU_R5_OCM 85
95 #define CPU_R5_OCM2 86
96 #define IOU_SWITCH 87
97 #define GEM0_REF 88
98 #define GEM1_REF 89
99 #define GEM_TSU_REF 90
100 #define USB0_BUS_REF 91
101 #define UART0_REF 92
102 #define UART1_REF 93
103 #define SPI0_REF 94
104 #define SPI1_REF 95
105 #define CAN0_REF 96
106 #define CAN1_REF 97
107 #define I2C0_REF 98
108 #define I2C1_REF 99
109 #define DBG_LPD 100
110 #define TIMESTAMP_REF 101
111 #define DBG_TSTMP 102
112 #define CPM_TOPSW_REF 103
113 #define USB3_DUAL_REF 104
114 #define OUTCLK_MAX 105
115 #define REF_CLK 106
116 #define PL_ALT_REF_CLK 107
117 #define MUXED_IRO 108
118 #define PL_EXT 109
119 #define PL_LB 110
120 #define MIO_50_OR_51 111
121 #define MIO_24_OR_25 112
123 #endif