include/kvm/arm_vgic.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2015, 2016 ARM Ltd.
   4  */
   5 #ifndef __KVM_ARM_VGIC_H
   6 #define __KVM_ARM_VGIC_H
   7
   8 #include <linux/kernel.h>
   9 #include <linux/kvm.h>
  10 #include <linux/irqreturn.h>
  11 #include <linux/spinlock.h>
  12 #include <linux/static_key.h>
  13 #include <linux/types.h>
  14 #include <kvm/iodev.h>
  15 #include <linux/list.h>
  16 #include <linux/jump_label.h>
  17
  18 #include <linux/irqchip/arm-gic-v4.h>
  19
  20 #define VGIC_V3_MAX_CPUS        512
  21 #define VGIC_V2_MAX_CPUS        8
  22 #define VGIC_NR_IRQS_LEGACY     256
  23 #define VGIC_NR_SGIS            16
  24 #define VGIC_NR_PPIS            16
  25 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  26 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  27 #define VGIC_MAX_SPI            1019
  28 #define VGIC_MAX_RESERVED       1023
  29 #define VGIC_MIN_LPI            8192
  30 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  31
  32 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
  33 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
  34                          (irq) <= VGIC_MAX_SPI)
  35
  36 enum vgic_type {
  37         VGIC_V2,                /* Good ol' GICv2 */
  38         VGIC_V3,                /* New fancy GICv3 */
  39 };
  40
  41 /* same for all guests, as depending only on the _host's_ GIC model */
  42 struct vgic_global {
  43         /* type of the host GIC */
  44         enum vgic_type          type;
  45
  46         /* Physical address of vgic virtual cpu interface */
  47         phys_addr_t             vcpu_base;
  48
  49         /* GICV mapping, kernel VA */
  50         void __iomem            *vcpu_base_va;
  51         /* GICV mapping, HYP VA */
  52         void __iomem            *vcpu_hyp_va;
  53
  54         /* virtual control interface mapping, kernel VA */
  55         void __iomem            *vctrl_base;
  56         /* virtual control interface mapping, HYP VA */
  57         void __iomem            *vctrl_hyp;
  58
  59         /* Number of implemented list registers */
  60         int                     nr_lr;
  61
  62         /* Maintenance IRQ number */
  63         unsigned int            maint_irq;
  64
  65         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  66         int                     max_gic_vcpus;
  67
  68         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  69         bool                    can_emulate_gicv2;
  70
  71         /* Hardware has GICv4? */
  72         bool                    has_gicv4;
  73         bool                    has_gicv4_1;
  74
  75         /* GIC system register CPU interface */
  76         struct static_key_false gicv3_cpuif;
  77
  78         u32                     ich_vtr_el2;
  79 };
  80
  81 extern struct vgic_global kvm_vgic_global_state;
  82
  83 #define VGIC_V2_MAX_LRS         (1 << 6)
  84 #define VGIC_V3_MAX_LRS         16
  85 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  86
  87 enum vgic_irq_config {
  88         VGIC_CONFIG_EDGE = 0,
  89         VGIC_CONFIG_LEVEL
  90 };
  91
  92 struct vgic_irq {
  93         raw_spinlock_t irq_lock;        /* Protects the content of the struct */
  94         struct list_head lpi_list;      /* Used to link all LPIs together */
  95         struct list_head ap_list;
  96
  97         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
  98                                          * SPIs and LPIs: The VCPU whose ap_list
  99                                          * this is queued on.
 100                                          */
 101
 102         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 103                                          * be sent to, as a result of the
 104                                          * targets reg (v2) or the
 105                                          * affinity reg (v3).
 106                                          */
 107
 108         u32 intid;                      /* Guest visible INTID */
 109         bool line_level;                /* Level only */
 110         bool pending_latch;             /* The pending latch state used to calculate
 111                                          * the pending state for both level
 112                                          * and edge triggered IRQs. */
 113         bool active;                    /* not used for LPIs */
 114         bool enabled;
 115         bool hw;                        /* Tied to HW IRQ */
 116         struct kref refcount;           /* Used for LPIs */
 117         u32 hwintid;                    /* HW INTID number */
 118         unsigned int host_irq;          /* linux irq corresponding to hwintid */
 119         union {
 120                 u8 targets;                     /* GICv2 target VCPUs mask */
 121                 u32 mpidr;                      /* GICv3 target VCPU */
 122         };
 123         u8 source;                      /* GICv2 SGIs only */
 124         u8 active_source;               /* GICv2 SGIs only */
 125         u8 priority;
 126         u8 group;                       /* 0 == group 0, 1 == group 1 */
 127         enum vgic_irq_config config;    /* Level or edge */
 128
 129         /*
 130          * Callback function pointer to in-kernel devices that can tell us the
 131          * state of the input level of mapped level-triggered IRQ faster than
 132          * peaking into the physical GIC.
 133          *
 134          * Always called in non-preemptible section and the functions can use
 135          * kvm_arm_get_running_vcpu() to get the vcpu pointer for private
 136          * IRQs.
 137          */
 138         bool (*get_input_level)(int vintid);
 139
 140         void *owner;                    /* Opaque pointer to reserve an interrupt
 141                                            for in-kernel devices. */
 142 };
 143
 144 struct vgic_register_region;
 145 struct vgic_its;
 146
 147 enum iodev_type {
 148         IODEV_CPUIF,
 149         IODEV_DIST,
 150         IODEV_REDIST,
 151         IODEV_ITS
 152 };
 153
 154 struct vgic_io_device {
 155         gpa_t base_addr;
 156         union {
 157                 struct kvm_vcpu *redist_vcpu;
 158                 struct vgic_its *its;
 159         };
 160         const struct vgic_register_region *regions;
 161         enum iodev_type iodev_type;
 162         int nr_regions;
 163         struct kvm_io_device dev;
 164 };
 165
 166 struct vgic_its {
 167         /* The base address of the ITS control register frame */
 168         gpa_t                   vgic_its_base;
 169
 170         bool                    enabled;
 171         struct vgic_io_device   iodev;
 172         struct kvm_device       *dev;
 173
 174         /* These registers correspond to GITS_BASER{0,1} */
 175         u64                     baser_device_table;
 176         u64                     baser_coll_table;
 177
 178         /* Protects the command queue */
 179         struct mutex            cmd_lock;
 180         u64                     cbaser;
 181         u32                     creadr;
 182         u32                     cwriter;
 183
 184         /* migration ABI revision in use */
 185         u32                     abi_rev;
 186
 187         /* Protects the device and collection lists */
 188         struct mutex            its_lock;
 189         struct list_head        device_list;
 190         struct list_head        collection_list;
 191 };
 192
 193 struct vgic_state_iter;
 194
 195 struct vgic_redist_region {
 196         u32 index;
 197         gpa_t base;
 198         u32 count; /* number of redistributors or 0 if single region */
 199         u32 free_index; /* index of the next free redistributor */
 200         struct list_head list;
 201 };
 202
 203 struct vgic_dist {
 204         bool                    in_kernel;
 205         bool                    ready;
 206         bool                    initialized;
 207
 208         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 209         u32                     vgic_model;
 210
 211         /* Implementation revision as reported in the GICD_IIDR */
 212         u32                     implementation_rev;
 213
 214         /* Userspace can write to GICv2 IGROUPR */
 215         bool                    v2_groups_user_writable;
 216
 217         /* Do injected MSIs require an additional device ID? */
 218         bool                    msis_require_devid;
 219
 220         int                     nr_spis;
 221
 222         /* base addresses in guest physical address space: */
 223         gpa_t                   vgic_dist_base;         /* distributor */
 224         union {
 225                 /* either a GICv2 CPU interface */
 226                 gpa_t                   vgic_cpu_base;
 227                 /* or a number of GICv3 redistributor regions */
 228                 struct list_head rd_regions;
 229         };
 230
 231         /* distributor enabled */
 232         bool                    enabled;
 233
 234         /* Wants SGIs without active state */
 235         bool                    nassgireq;
 236
 237         struct vgic_irq         *spis;
 238
 239         struct vgic_io_device   dist_iodev;
 240
 241         bool                    has_its;
 242
 243         /*
 244          * Contains the attributes and gpa of the LPI configuration table.
 245          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 246          * one address across all redistributors.
 247          * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
 248          */
 249         u64                     propbaser;
 250
 251         /* Protects the lpi_list and the count value below. */
 252         raw_spinlock_t          lpi_list_lock;
 253         struct list_head        lpi_list_head;
 254         int                     lpi_list_count;
 255
 256         /* LPI translation cache */
 257         struct list_head        lpi_translation_cache;
 258
 259         /* used by vgic-debug */
 260         struct vgic_state_iter *iter;
 261
 262         /*
 263          * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
 264          * array, the property table pointer as well as allocation
 265          * data. This essentially ties the Linux IRQ core and ITS
 266          * together, and avoids leaking KVM's data structures anywhere
 267          * else.
 268          */
 269         struct its_vm           its_vm;
 270 };
 271
 272 struct vgic_v2_cpu_if {
 273         u32             vgic_hcr;
 274         u32             vgic_vmcr;
 275         u32             vgic_apr;
 276         u32             vgic_lr[VGIC_V2_MAX_LRS];
 277
 278         unsigned int used_lrs;
 279 };
 280
 281 struct vgic_v3_cpu_if {
 282         u32             vgic_hcr;
 283         u32             vgic_vmcr;
 284         u32             vgic_sre;       /* Restored only, change ignored */
 285         u32             vgic_ap0r[4];
 286         u32             vgic_ap1r[4];
 287         u64             vgic_lr[VGIC_V3_MAX_LRS];
 288
 289         /*
 290          * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
 291          * pending table pointer, the its_vm pointer and a few other
 292          * HW specific things. As for the its_vm structure, this is
 293          * linking the Linux IRQ subsystem and the ITS together.
 294          */
 295         struct its_vpe  its_vpe;
 296
 297         unsigned int used_lrs;
 298 };
 299
 300 struct vgic_cpu {
 301         /* CPU vif control registers for world switch */
 302         union {
 303                 struct vgic_v2_cpu_if   vgic_v2;
 304                 struct vgic_v3_cpu_if   vgic_v3;
 305         };
 306
 307         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 308
 309         raw_spinlock_t ap_list_lock;    /* Protects the ap_list */
 310
 311         /*
 312          * List of IRQs that this VCPU should consider because they are either
 313          * Active or Pending (hence the name; AP list), or because they recently
 314          * were one of the two and need to be migrated off this list to another
 315          * VCPU.
 316          */
 317         struct list_head ap_list_head;
 318
 319         /*
 320          * Members below are used with GICv3 emulation only and represent
 321          * parts of the redistributor.
 322          */
 323         struct vgic_io_device   rd_iodev;
 324         struct vgic_redist_region *rdreg;
 325
 326         /* Contains the attributes and gpa of the LPI pending tables. */
 327         u64 pendbaser;
 328
 329         bool lpis_enabled;
 330
 331         /* Cache guest priority bits */
 332         u32 num_pri_bits;
 333
 334         /* Cache guest interrupt ID bits */
 335         u32 num_id_bits;
 336 };
 337
 338 extern struct static_key_false vgic_v2_cpuif_trap;
 339 extern struct static_key_false vgic_v3_cpuif_trap;
 340
 341 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 342 void kvm_vgic_early_init(struct kvm *kvm);
 343 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 344 int kvm_vgic_create(struct kvm *kvm, u32 type);
 345 void kvm_vgic_destroy(struct kvm *kvm);
 346 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 347 int kvm_vgic_map_resources(struct kvm *kvm);
 348 int kvm_vgic_hyp_init(void);
 349 void kvm_vgic_init_cpu_hardware(void);
 350
 351 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 352                         bool level, void *owner);
 353 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
 354                           u32 vintid, bool (*get_input_level)(int vindid));
 355 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
 356 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
 357
 358 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 359
 360 void kvm_vgic_load(struct kvm_vcpu *vcpu);
 361 void kvm_vgic_put(struct kvm_vcpu *vcpu);
 362 void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu);
 363
 364 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 365 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 366 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 367 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 368                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 369
 370 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 371 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 372 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 373 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
 374
 375 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1);
 376
 377 /**
 378  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 379  *
 380  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 381  * can use.
 382  */
 383 static inline int kvm_vgic_get_max_vcpus(void)
 384 {
 385         return kvm_vgic_global_state.max_gic_vcpus;
 386 }
 387
 388 /**
 389  * kvm_vgic_setup_default_irq_routing:
 390  * Setup a default flat gsi routing table mapping all SPIs
 391  */
 392 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 393
 394 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
 395
 396 struct kvm_kernel_irq_routing_entry;
 397
 398 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
 399                                struct kvm_kernel_irq_routing_entry *irq_entry);
 400
 401 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
 402                                  struct kvm_kernel_irq_routing_entry *irq_entry);
 403
 404 int vgic_v4_load(struct kvm_vcpu *vcpu);
 405 void vgic_v4_commit(struct kvm_vcpu *vcpu);
 406 int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db);
 407
 408 #endif /* __KVM_ARM_VGIC_H */