include/soc/mscc/ocelot.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2 /* Copyright (c) 2017 Microsemi Corporation
   3  */
   4
   5 #ifndef _SOC_MSCC_OCELOT_H
   6 #define _SOC_MSCC_OCELOT_H
   7
   8 #include <linux/ptp_clock_kernel.h>
   9 #include <linux/net_tstamp.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/regmap.h>
  12 #include <net/dsa.h>
  13
  14 /* Port Group IDs (PGID) are masks of destination ports.
  15  *
  16  * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
  17  * frame, and forwards the frame to the ports that are present in the logical
  18  * AND of all 3 PGIDs.
  19  *
  20  * These PGID lookups are:
  21  * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
  22  *   which the switch selects a destination PGID:
  23  *     - The {DMAC, VID} is present in the MAC table. In that case, the
  24  *       destination PGID is given by the DEST_IDX field of the MAC table entry
  25  *       that matched.
  26  *     - The {DMAC, VID} is not present in the MAC table (it is unknown). The
  27  *       frame is disseminated as being either unicast, multicast or broadcast,
  28  *       and according to that, the destination PGID is chosen as being the
  29  *       value contained by ANA_FLOODING_FLD_UNICAST,
  30  *       ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
  31  *   The destination PGID can be an unicast set: the first PGIDs, 0 to
  32  *   ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
  33  *   ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
  34  *   a physical port and has a single bit set in the destination ports mask:
  35  *   that corresponding to the port number itself. In contrast, a multicast
  36  *   PGID will have potentially more than one single bit set in the destination
  37  *   ports mask.
  38  * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
  39  *   dissects each frame and generates a 4-bit Link Aggregation Code which is
  40  *   used for this second PGID table lookup. The goal of link aggregation is to
  41  *   hash multiple flows within the same LAG on to different destination ports.
  42  *   The first lookup will result in a PGID with all the LAG members present in
  43  *   the destination ports mask, and the second lookup, by Link Aggregation
  44  *   Code, will ensure that each flow gets forwarded only to a single port out
  45  *   of that mask (there are no duplicates).
  46  * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
  47  *   is indexed with the ingress port (plus 80). These PGIDs answer the
  48  *   question "is port i allowed to forward traffic to port j?" If yes, then
  49  *   BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
  50  *   to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
  51  */
  52
  53 /* Reserve some destination PGIDs at the end of the range:
  54  * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
  55  *           of the switch port net devices, towards the CPU port module.
  56  * PGID_UC: the flooding destinations for unknown unicast traffic.
  57  * PGID_MC: the flooding destinations for broadcast and non-IP multicast
  58  *          traffic.
  59  * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
  60  * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
  61  */
  62 #define PGID_CPU                        59
  63 #define PGID_UC                         60
  64 #define PGID_MC                         61
  65 #define PGID_MCIPV4                     62
  66 #define PGID_MCIPV6                     63
  67
  68 #define for_each_unicast_dest_pgid(ocelot, pgid)                \
  69         for ((pgid) = 0;                                        \
  70              (pgid) < (ocelot)->num_phys_ports;                 \
  71              (pgid)++)
  72
  73 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid)  \
  74         for ((pgid) = (ocelot)->num_phys_ports + 1;             \
  75              (pgid) < PGID_CPU;                                 \
  76              (pgid)++)
  77
  78 #define for_each_aggr_pgid(ocelot, pgid)                        \
  79         for ((pgid) = PGID_AGGR;                                \
  80              (pgid) < PGID_SRC;                                 \
  81              (pgid)++)
  82
  83 /* Aggregation PGIDs, one per Link Aggregation Code */
  84 #define PGID_AGGR                       64
  85
  86 /* Source PGIDs, one per physical port */
  87 #define PGID_SRC                        80
  88
  89 #define IFH_INJ_BYPASS                  BIT(31)
  90 #define IFH_INJ_POP_CNT_DISABLE         (3 << 28)
  91
  92 #define IFH_TAG_TYPE_C                  0
  93 #define IFH_TAG_TYPE_S                  1
  94
  95 #define IFH_REW_OP_NOOP                 0x0
  96 #define IFH_REW_OP_DSCP                 0x1
  97 #define IFH_REW_OP_ONE_STEP_PTP         0x2
  98 #define IFH_REW_OP_TWO_STEP_PTP         0x3
  99 #define IFH_REW_OP_ORIGIN_PTP           0x5
 100
 101 #define OCELOT_TAG_LEN                  16
 102 #define OCELOT_SHORT_PREFIX_LEN         4
 103 #define OCELOT_LONG_PREFIX_LEN          16
 104 #define OCELOT_TOTAL_TAG_LEN    (OCELOT_SHORT_PREFIX_LEN + OCELOT_TAG_LEN)
 105
 106 #define OCELOT_SPEED_2500               0
 107 #define OCELOT_SPEED_1000               1
 108 #define OCELOT_SPEED_100                2
 109 #define OCELOT_SPEED_10                 3
 110
 111 #define OCELOT_PTP_PINS_NUM             4
 112
 113 #define TARGET_OFFSET                   24
 114 #define REG_MASK                        GENMASK(TARGET_OFFSET - 1, 0)
 115 #define REG(reg, offset)                [reg & REG_MASK] = offset
 116
 117 #define REG_RESERVED_ADDR               0xffffffff
 118 #define REG_RESERVED(reg)               REG(reg, REG_RESERVED_ADDR)
 119
 120 enum ocelot_target {
 121         ANA = 1,
 122         QS,
 123         QSYS,
 124         REW,
 125         SYS,
 126         S0,
 127         S1,
 128         S2,
 129         HSIO,
 130         PTP,
 131         GCB,
 132         DEV_GMII,
 133         TARGET_MAX,
 134 };
 135
 136 enum ocelot_reg {
 137         ANA_ADVLEARN = ANA << TARGET_OFFSET,
 138         ANA_VLANMASK,
 139         ANA_PORT_B_DOMAIN,
 140         ANA_ANAGEFIL,
 141         ANA_ANEVENTS,
 142         ANA_STORMLIMIT_BURST,
 143         ANA_STORMLIMIT_CFG,
 144         ANA_ISOLATED_PORTS,
 145         ANA_COMMUNITY_PORTS,
 146         ANA_AUTOAGE,
 147         ANA_MACTOPTIONS,
 148         ANA_LEARNDISC,
 149         ANA_AGENCTRL,
 150         ANA_MIRRORPORTS,
 151         ANA_EMIRRORPORTS,
 152         ANA_FLOODING,
 153         ANA_FLOODING_IPMC,
 154         ANA_SFLOW_CFG,
 155         ANA_PORT_MODE,
 156         ANA_CUT_THRU_CFG,
 157         ANA_PGID_PGID,
 158         ANA_TABLES_ANMOVED,
 159         ANA_TABLES_MACHDATA,
 160         ANA_TABLES_MACLDATA,
 161         ANA_TABLES_STREAMDATA,
 162         ANA_TABLES_MACACCESS,
 163         ANA_TABLES_MACTINDX,
 164         ANA_TABLES_VLANACCESS,
 165         ANA_TABLES_VLANTIDX,
 166         ANA_TABLES_ISDXACCESS,
 167         ANA_TABLES_ISDXTIDX,
 168         ANA_TABLES_ENTRYLIM,
 169         ANA_TABLES_PTP_ID_HIGH,
 170         ANA_TABLES_PTP_ID_LOW,
 171         ANA_TABLES_STREAMACCESS,
 172         ANA_TABLES_STREAMTIDX,
 173         ANA_TABLES_SEQ_HISTORY,
 174         ANA_TABLES_SEQ_MASK,
 175         ANA_TABLES_SFID_MASK,
 176         ANA_TABLES_SFIDACCESS,
 177         ANA_TABLES_SFIDTIDX,
 178         ANA_MSTI_STATE,
 179         ANA_OAM_UPM_LM_CNT,
 180         ANA_SG_ACCESS_CTRL,
 181         ANA_SG_CONFIG_REG_1,
 182         ANA_SG_CONFIG_REG_2,
 183         ANA_SG_CONFIG_REG_3,
 184         ANA_SG_CONFIG_REG_4,
 185         ANA_SG_CONFIG_REG_5,
 186         ANA_SG_GCL_GS_CONFIG,
 187         ANA_SG_GCL_TI_CONFIG,
 188         ANA_SG_STATUS_REG_1,
 189         ANA_SG_STATUS_REG_2,
 190         ANA_SG_STATUS_REG_3,
 191         ANA_PORT_VLAN_CFG,
 192         ANA_PORT_DROP_CFG,
 193         ANA_PORT_QOS_CFG,
 194         ANA_PORT_VCAP_CFG,
 195         ANA_PORT_VCAP_S1_KEY_CFG,
 196         ANA_PORT_VCAP_S2_CFG,
 197         ANA_PORT_PCP_DEI_MAP,
 198         ANA_PORT_CPU_FWD_CFG,
 199         ANA_PORT_CPU_FWD_BPDU_CFG,
 200         ANA_PORT_CPU_FWD_GARP_CFG,
 201         ANA_PORT_CPU_FWD_CCM_CFG,
 202         ANA_PORT_PORT_CFG,
 203         ANA_PORT_POL_CFG,
 204         ANA_PORT_PTP_CFG,
 205         ANA_PORT_PTP_DLY1_CFG,
 206         ANA_PORT_PTP_DLY2_CFG,
 207         ANA_PORT_SFID_CFG,
 208         ANA_PFC_PFC_CFG,
 209         ANA_PFC_PFC_TIMER,
 210         ANA_IPT_OAM_MEP_CFG,
 211         ANA_IPT_IPT,
 212         ANA_PPT_PPT,
 213         ANA_FID_MAP_FID_MAP,
 214         ANA_AGGR_CFG,
 215         ANA_CPUQ_CFG,
 216         ANA_CPUQ_CFG2,
 217         ANA_CPUQ_8021_CFG,
 218         ANA_DSCP_CFG,
 219         ANA_DSCP_REWR_CFG,
 220         ANA_VCAP_RNG_TYPE_CFG,
 221         ANA_VCAP_RNG_VAL_CFG,
 222         ANA_VRAP_CFG,
 223         ANA_VRAP_HDR_DATA,
 224         ANA_VRAP_HDR_MASK,
 225         ANA_DISCARD_CFG,
 226         ANA_FID_CFG,
 227         ANA_POL_PIR_CFG,
 228         ANA_POL_CIR_CFG,
 229         ANA_POL_MODE_CFG,
 230         ANA_POL_PIR_STATE,
 231         ANA_POL_CIR_STATE,
 232         ANA_POL_STATE,
 233         ANA_POL_FLOWC,
 234         ANA_POL_HYST,
 235         ANA_POL_MISC_CFG,
 236         QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
 237         QS_XTR_RD,
 238         QS_XTR_FRM_PRUNING,
 239         QS_XTR_FLUSH,
 240         QS_XTR_DATA_PRESENT,
 241         QS_XTR_CFG,
 242         QS_INJ_GRP_CFG,
 243         QS_INJ_WR,
 244         QS_INJ_CTRL,
 245         QS_INJ_STATUS,
 246         QS_INJ_ERR,
 247         QS_INH_DBG,
 248         QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
 249         QSYS_SWITCH_PORT_MODE,
 250         QSYS_STAT_CNT_CFG,
 251         QSYS_EEE_CFG,
 252         QSYS_EEE_THRES,
 253         QSYS_IGR_NO_SHARING,
 254         QSYS_EGR_NO_SHARING,
 255         QSYS_SW_STATUS,
 256         QSYS_EXT_CPU_CFG,
 257         QSYS_PAD_CFG,
 258         QSYS_CPU_GROUP_MAP,
 259         QSYS_QMAP,
 260         QSYS_ISDX_SGRP,
 261         QSYS_TIMED_FRAME_ENTRY,
 262         QSYS_TFRM_MISC,
 263         QSYS_TFRM_PORT_DLY,
 264         QSYS_TFRM_TIMER_CFG_1,
 265         QSYS_TFRM_TIMER_CFG_2,
 266         QSYS_TFRM_TIMER_CFG_3,
 267         QSYS_TFRM_TIMER_CFG_4,
 268         QSYS_TFRM_TIMER_CFG_5,
 269         QSYS_TFRM_TIMER_CFG_6,
 270         QSYS_TFRM_TIMER_CFG_7,
 271         QSYS_TFRM_TIMER_CFG_8,
 272         QSYS_RED_PROFILE,
 273         QSYS_RES_QOS_MODE,
 274         QSYS_RES_CFG,
 275         QSYS_RES_STAT,
 276         QSYS_EGR_DROP_MODE,
 277         QSYS_EQ_CTRL,
 278         QSYS_EVENTS_CORE,
 279         QSYS_QMAXSDU_CFG_0,
 280         QSYS_QMAXSDU_CFG_1,
 281         QSYS_QMAXSDU_CFG_2,
 282         QSYS_QMAXSDU_CFG_3,
 283         QSYS_QMAXSDU_CFG_4,
 284         QSYS_QMAXSDU_CFG_5,
 285         QSYS_QMAXSDU_CFG_6,
 286         QSYS_QMAXSDU_CFG_7,
 287         QSYS_PREEMPTION_CFG,
 288         QSYS_CIR_CFG,
 289         QSYS_EIR_CFG,
 290         QSYS_SE_CFG,
 291         QSYS_SE_DWRR_CFG,
 292         QSYS_SE_CONNECT,
 293         QSYS_SE_DLB_SENSE,
 294         QSYS_CIR_STATE,
 295         QSYS_EIR_STATE,
 296         QSYS_SE_STATE,
 297         QSYS_HSCH_MISC_CFG,
 298         QSYS_TAG_CONFIG,
 299         QSYS_TAS_PARAM_CFG_CTRL,
 300         QSYS_PORT_MAX_SDU,
 301         QSYS_PARAM_CFG_REG_1,
 302         QSYS_PARAM_CFG_REG_2,
 303         QSYS_PARAM_CFG_REG_3,
 304         QSYS_PARAM_CFG_REG_4,
 305         QSYS_PARAM_CFG_REG_5,
 306         QSYS_GCL_CFG_REG_1,
 307         QSYS_GCL_CFG_REG_2,
 308         QSYS_PARAM_STATUS_REG_1,
 309         QSYS_PARAM_STATUS_REG_2,
 310         QSYS_PARAM_STATUS_REG_3,
 311         QSYS_PARAM_STATUS_REG_4,
 312         QSYS_PARAM_STATUS_REG_5,
 313         QSYS_PARAM_STATUS_REG_6,
 314         QSYS_PARAM_STATUS_REG_7,
 315         QSYS_PARAM_STATUS_REG_8,
 316         QSYS_PARAM_STATUS_REG_9,
 317         QSYS_GCL_STATUS_REG_1,
 318         QSYS_GCL_STATUS_REG_2,
 319         REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
 320         REW_TAG_CFG,
 321         REW_PORT_CFG,
 322         REW_DSCP_CFG,
 323         REW_PCP_DEI_QOS_MAP_CFG,
 324         REW_PTP_CFG,
 325         REW_PTP_DLY1_CFG,
 326         REW_RED_TAG_CFG,
 327         REW_DSCP_REMAP_DP1_CFG,
 328         REW_DSCP_REMAP_CFG,
 329         REW_STAT_CFG,
 330         REW_REW_STICKY,
 331         REW_PPT,
 332         SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
 333         SYS_COUNT_RX_UNICAST,
 334         SYS_COUNT_RX_MULTICAST,
 335         SYS_COUNT_RX_BROADCAST,
 336         SYS_COUNT_RX_SHORTS,
 337         SYS_COUNT_RX_FRAGMENTS,
 338         SYS_COUNT_RX_JABBERS,
 339         SYS_COUNT_RX_CRC_ALIGN_ERRS,
 340         SYS_COUNT_RX_SYM_ERRS,
 341         SYS_COUNT_RX_64,
 342         SYS_COUNT_RX_65_127,
 343         SYS_COUNT_RX_128_255,
 344         SYS_COUNT_RX_256_1023,
 345         SYS_COUNT_RX_1024_1526,
 346         SYS_COUNT_RX_1527_MAX,
 347         SYS_COUNT_RX_PAUSE,
 348         SYS_COUNT_RX_CONTROL,
 349         SYS_COUNT_RX_LONGS,
 350         SYS_COUNT_RX_CLASSIFIED_DROPS,
 351         SYS_COUNT_TX_OCTETS,
 352         SYS_COUNT_TX_UNICAST,
 353         SYS_COUNT_TX_MULTICAST,
 354         SYS_COUNT_TX_BROADCAST,
 355         SYS_COUNT_TX_COLLISION,
 356         SYS_COUNT_TX_DROPS,
 357         SYS_COUNT_TX_PAUSE,
 358         SYS_COUNT_TX_64,
 359         SYS_COUNT_TX_65_127,
 360         SYS_COUNT_TX_128_511,
 361         SYS_COUNT_TX_512_1023,
 362         SYS_COUNT_TX_1024_1526,
 363         SYS_COUNT_TX_1527_MAX,
 364         SYS_COUNT_TX_AGING,
 365         SYS_RESET_CFG,
 366         SYS_SR_ETYPE_CFG,
 367         SYS_VLAN_ETYPE_CFG,
 368         SYS_PORT_MODE,
 369         SYS_FRONT_PORT_MODE,
 370         SYS_FRM_AGING,
 371         SYS_STAT_CFG,
 372         SYS_SW_STATUS,
 373         SYS_MISC_CFG,
 374         SYS_REW_MAC_HIGH_CFG,
 375         SYS_REW_MAC_LOW_CFG,
 376         SYS_TIMESTAMP_OFFSET,
 377         SYS_CMID,
 378         SYS_PAUSE_CFG,
 379         SYS_PAUSE_TOT_CFG,
 380         SYS_ATOP,
 381         SYS_ATOP_TOT_CFG,
 382         SYS_MAC_FC_CFG,
 383         SYS_MMGT,
 384         SYS_MMGT_FAST,
 385         SYS_EVENTS_DIF,
 386         SYS_EVENTS_CORE,
 387         SYS_CNT,
 388         SYS_PTP_STATUS,
 389         SYS_PTP_TXSTAMP,
 390         SYS_PTP_NXT,
 391         SYS_PTP_CFG,
 392         SYS_RAM_INIT,
 393         SYS_CM_ADDR,
 394         SYS_CM_DATA_WR,
 395         SYS_CM_DATA_RD,
 396         SYS_CM_OP,
 397         SYS_CM_DATA,
 398         PTP_PIN_CFG = PTP << TARGET_OFFSET,
 399         PTP_PIN_TOD_SEC_MSB,
 400         PTP_PIN_TOD_SEC_LSB,
 401         PTP_PIN_TOD_NSEC,
 402         PTP_PIN_WF_HIGH_PERIOD,
 403         PTP_PIN_WF_LOW_PERIOD,
 404         PTP_CFG_MISC,
 405         PTP_CLK_CFG_ADJ_CFG,
 406         PTP_CLK_CFG_ADJ_FREQ,
 407         GCB_SOFT_RST = GCB << TARGET_OFFSET,
 408         GCB_MIIM_MII_STATUS,
 409         GCB_MIIM_MII_CMD,
 410         GCB_MIIM_MII_DATA,
 411         DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
 412         DEV_PORT_MISC,
 413         DEV_EVENTS,
 414         DEV_EEE_CFG,
 415         DEV_RX_PATH_DELAY,
 416         DEV_TX_PATH_DELAY,
 417         DEV_PTP_PREDICT_CFG,
 418         DEV_MAC_ENA_CFG,
 419         DEV_MAC_MODE_CFG,
 420         DEV_MAC_MAXLEN_CFG,
 421         DEV_MAC_TAGS_CFG,
 422         DEV_MAC_ADV_CHK_CFG,
 423         DEV_MAC_IFG_CFG,
 424         DEV_MAC_HDX_CFG,
 425         DEV_MAC_DBG_CFG,
 426         DEV_MAC_FC_MAC_LOW_CFG,
 427         DEV_MAC_FC_MAC_HIGH_CFG,
 428         DEV_MAC_STICKY,
 429         PCS1G_CFG,
 430         PCS1G_MODE_CFG,
 431         PCS1G_SD_CFG,
 432         PCS1G_ANEG_CFG,
 433         PCS1G_ANEG_NP_CFG,
 434         PCS1G_LB_CFG,
 435         PCS1G_DBG_CFG,
 436         PCS1G_CDET_CFG,
 437         PCS1G_ANEG_STATUS,
 438         PCS1G_ANEG_NP_STATUS,
 439         PCS1G_LINK_STATUS,
 440         PCS1G_LINK_DOWN_CNT,
 441         PCS1G_STICKY,
 442         PCS1G_DEBUG_STATUS,
 443         PCS1G_LPI_CFG,
 444         PCS1G_LPI_WAKE_ERROR_CNT,
 445         PCS1G_LPI_STATUS,
 446         PCS1G_TSTPAT_MODE_CFG,
 447         PCS1G_TSTPAT_STATUS,
 448         DEV_PCS_FX100_CFG,
 449         DEV_PCS_FX100_STATUS,
 450 };
 451
 452 enum ocelot_regfield {
 453         ANA_ADVLEARN_VLAN_CHK,
 454         ANA_ADVLEARN_LEARN_MIRROR,
 455         ANA_ANEVENTS_FLOOD_DISCARD,
 456         ANA_ANEVENTS_MSTI_DROP,
 457         ANA_ANEVENTS_ACLKILL,
 458         ANA_ANEVENTS_ACLUSED,
 459         ANA_ANEVENTS_AUTOAGE,
 460         ANA_ANEVENTS_VS2TTL1,
 461         ANA_ANEVENTS_STORM_DROP,
 462         ANA_ANEVENTS_LEARN_DROP,
 463         ANA_ANEVENTS_AGED_ENTRY,
 464         ANA_ANEVENTS_CPU_LEARN_FAILED,
 465         ANA_ANEVENTS_AUTO_LEARN_FAILED,
 466         ANA_ANEVENTS_LEARN_REMOVE,
 467         ANA_ANEVENTS_AUTO_LEARNED,
 468         ANA_ANEVENTS_AUTO_MOVED,
 469         ANA_ANEVENTS_DROPPED,
 470         ANA_ANEVENTS_CLASSIFIED_DROP,
 471         ANA_ANEVENTS_CLASSIFIED_COPY,
 472         ANA_ANEVENTS_VLAN_DISCARD,
 473         ANA_ANEVENTS_FWD_DISCARD,
 474         ANA_ANEVENTS_MULTICAST_FLOOD,
 475         ANA_ANEVENTS_UNICAST_FLOOD,
 476         ANA_ANEVENTS_DEST_KNOWN,
 477         ANA_ANEVENTS_BUCKET3_MATCH,
 478         ANA_ANEVENTS_BUCKET2_MATCH,
 479         ANA_ANEVENTS_BUCKET1_MATCH,
 480         ANA_ANEVENTS_BUCKET0_MATCH,
 481         ANA_ANEVENTS_CPU_OPERATION,
 482         ANA_ANEVENTS_DMAC_LOOKUP,
 483         ANA_ANEVENTS_SMAC_LOOKUP,
 484         ANA_ANEVENTS_SEQ_GEN_ERR_0,
 485         ANA_ANEVENTS_SEQ_GEN_ERR_1,
 486         ANA_TABLES_MACACCESS_B_DOM,
 487         ANA_TABLES_MACTINDX_BUCKET,
 488         ANA_TABLES_MACTINDX_M_INDEX,
 489         QSYS_SWITCH_PORT_MODE_PORT_ENA,
 490         QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
 491         QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
 492         QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
 493         QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
 494         QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
 495         QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
 496         QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
 497         QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
 498         QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
 499         QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
 500         SYS_PORT_MODE_DATA_WO_TS,
 501         SYS_PORT_MODE_INCL_INJ_HDR,
 502         SYS_PORT_MODE_INCL_XTR_HDR,
 503         SYS_PORT_MODE_INCL_HDR_ERR,
 504         SYS_RESET_CFG_CORE_ENA,
 505         SYS_RESET_CFG_MEM_ENA,
 506         SYS_RESET_CFG_MEM_INIT,
 507         GCB_SOFT_RST_SWC_RST,
 508         GCB_MIIM_MII_STATUS_PENDING,
 509         GCB_MIIM_MII_STATUS_BUSY,
 510         SYS_PAUSE_CFG_PAUSE_START,
 511         SYS_PAUSE_CFG_PAUSE_STOP,
 512         SYS_PAUSE_CFG_PAUSE_ENA,
 513         REGFIELD_MAX
 514 };
 515
 516 enum {
 517         /* VCAP_CORE_CFG */
 518         VCAP_CORE_UPDATE_CTRL,
 519         VCAP_CORE_MV_CFG,
 520         /* VCAP_CORE_CACHE */
 521         VCAP_CACHE_ENTRY_DAT,
 522         VCAP_CACHE_MASK_DAT,
 523         VCAP_CACHE_ACTION_DAT,
 524         VCAP_CACHE_CNT_DAT,
 525         VCAP_CACHE_TG_DAT,
 526         /* VCAP_CONST */
 527         VCAP_CONST_VCAP_VER,
 528         VCAP_CONST_ENTRY_WIDTH,
 529         VCAP_CONST_ENTRY_CNT,
 530         VCAP_CONST_ENTRY_SWCNT,
 531         VCAP_CONST_ENTRY_TG_WIDTH,
 532         VCAP_CONST_ACTION_DEF_CNT,
 533         VCAP_CONST_ACTION_WIDTH,
 534         VCAP_CONST_CNT_WIDTH,
 535         VCAP_CONST_CORE_CNT,
 536         VCAP_CONST_IF_CNT,
 537 };
 538
 539 enum ocelot_ptp_pins {
 540         PTP_PIN_0,
 541         PTP_PIN_1,
 542         PTP_PIN_2,
 543         PTP_PIN_3,
 544         TOD_ACC_PIN
 545 };
 546
 547 struct ocelot_stat_layout {
 548         u32 offset;
 549         char name[ETH_GSTRING_LEN];
 550 };
 551
 552 enum ocelot_tag_prefix {
 553         OCELOT_TAG_PREFIX_DISABLED      = 0,
 554         OCELOT_TAG_PREFIX_NONE,
 555         OCELOT_TAG_PREFIX_SHORT,
 556         OCELOT_TAG_PREFIX_LONG,
 557 };
 558
 559 struct ocelot;
 560
 561 struct ocelot_ops {
 562         struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
 563         int (*netdev_to_port)(struct net_device *dev);
 564         int (*reset)(struct ocelot *ocelot);
 565         u16 (*wm_enc)(u16 value);
 566 };
 567
 568 struct ocelot_vcap_block {
 569         struct list_head rules;
 570         int count;
 571         int pol_lpr;
 572 };
 573
 574 struct ocelot_vlan {
 575         bool valid;
 576         u16 vid;
 577 };
 578
 579 struct ocelot_port {
 580         struct ocelot                   *ocelot;
 581
 582         struct regmap                   *target;
 583
 584         bool                            vlan_aware;
 585         /* VLAN that untagged frames are classified to, on ingress */
 586         struct ocelot_vlan              pvid_vlan;
 587         /* The VLAN ID that will be transmitted as untagged, on egress */
 588         struct ocelot_vlan              native_vlan;
 589
 590         u8                              ptp_cmd;
 591         struct sk_buff_head             tx_skbs;
 592         u8                              ts_id;
 593         spinlock_t                      ts_id_lock;
 594
 595         phy_interface_t                 phy_mode;
 596
 597         u8                              *xmit_template;
 598 };
 599
 600 struct ocelot {
 601         struct device                   *dev;
 602
 603         const struct ocelot_ops         *ops;
 604         struct regmap                   *targets[TARGET_MAX];
 605         struct regmap_field             *regfields[REGFIELD_MAX];
 606         const u32 *const                *map;
 607         const struct ocelot_stat_layout *stats_layout;
 608         unsigned int                    num_stats;
 609
 610         int                             shared_queue_sz;
 611         int                             num_mact_rows;
 612
 613         struct net_device               *hw_bridge_dev;
 614         u16                             bridge_mask;
 615         u16                             bridge_fwd_mask;
 616
 617         struct ocelot_port              **ports;
 618
 619         u8                              base_mac[ETH_ALEN];
 620
 621         /* Keep track of the vlan port masks */
 622         u32                             vlan_mask[VLAN_N_VID];
 623
 624         /* Switches like VSC9959 have flooding per traffic class */
 625         int                             num_flooding_pgids;
 626
 627         /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
 628          * the CPU is located after the physical ports (at the
 629          * num_phys_ports index).
 630          */
 631         u8                              num_phys_ports;
 632
 633         int                             npi;
 634
 635         enum ocelot_tag_prefix          inj_prefix;
 636         enum ocelot_tag_prefix          xtr_prefix;
 637
 638         u32                             *lags;
 639
 640         struct list_head                multicast;
 641         struct list_head                pgids;
 642
 643         struct list_head                dummy_rules;
 644         struct ocelot_vcap_block        block[3];
 645         struct vcap_props               *vcap;
 646
 647         /* Workqueue to check statistics for overflow with its lock */
 648         struct mutex                    stats_lock;
 649         u64                             *stats;
 650         struct delayed_work             stats_work;
 651         struct workqueue_struct         *stats_queue;
 652
 653         struct workqueue_struct         *owq;
 654
 655         u8                              ptp:1;
 656         struct ptp_clock                *ptp_clock;
 657         struct ptp_clock_info           ptp_info;
 658         struct hwtstamp_config          hwtstamp_config;
 659         /* Protects the PTP interface state */
 660         struct mutex                    ptp_lock;
 661         /* Protects the PTP clock */
 662         spinlock_t                      ptp_clock_lock;
 663         struct ptp_pin_desc             ptp_pins[OCELOT_PTP_PINS_NUM];
 664 };
 665
 666 struct ocelot_policer {
 667         u32 rate; /* kilobit per second */
 668         u32 burst; /* bytes */
 669 };
 670
 671 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 672 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
 673 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
 674 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
 675
 676 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 677 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
 678 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
 679 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
 680
 681 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 682 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
 683 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
 684 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
 685
 686 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
 687 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
 688 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
 689 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
 690
 691 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
 692         __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 693 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
 694         __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
 695 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
 696         __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
 697 #define ocelot_target_read(ocelot, target, reg) \
 698         __ocelot_target_read_ix(ocelot, target, reg, 0)
 699
 700 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
 701         __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 702 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
 703         __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
 704 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
 705         __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
 706 #define ocelot_target_write(ocelot, target, val, reg) \
 707         __ocelot_target_write_ix(ocelot, target, val, reg, 0)
 708
 709 /* I/O */
 710 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
 711 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
 712 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
 713 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
 714 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
 715                      u32 offset);
 716 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
 717                             u32 reg, u32 offset);
 718 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
 719                               u32 val, u32 reg, u32 offset);
 720
 721 /* Hardware initialization */
 722 int ocelot_regfields_init(struct ocelot *ocelot,
 723                           const struct reg_field *const regfields);
 724 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
 725 int ocelot_init(struct ocelot *ocelot);
 726 void ocelot_deinit(struct ocelot *ocelot);
 727 void ocelot_init_port(struct ocelot *ocelot, int port);
 728 void ocelot_deinit_port(struct ocelot *ocelot, int port);
 729
 730 /* DSA callbacks */
 731 void ocelot_port_enable(struct ocelot *ocelot, int port,
 732                         struct phy_device *phy);
 733 void ocelot_port_disable(struct ocelot *ocelot, int port);
 734 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
 735 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
 736 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
 737 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
 738                        struct ethtool_ts_info *info);
 739 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
 740 void ocelot_adjust_link(struct ocelot *ocelot, int port,
 741                         struct phy_device *phydev);
 742 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
 743                                struct switchdev_trans *trans);
 744 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
 745 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
 746                             struct net_device *bridge);
 747 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
 748                              struct net_device *bridge);
 749 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
 750                     dsa_fdb_dump_cb_t *cb, void *data);
 751 int ocelot_fdb_add(struct ocelot *ocelot, int port,
 752                    const unsigned char *addr, u16 vid);
 753 int ocelot_fdb_del(struct ocelot *ocelot, int port,
 754                    const unsigned char *addr, u16 vid);
 755 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
 756                         bool untagged);
 757 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
 758                     bool untagged);
 759 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
 760 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
 761 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
 762 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
 763                                   struct sk_buff *clone);
 764 void ocelot_get_txtstamp(struct ocelot *ocelot);
 765 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
 766 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
 767 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
 768                             struct ocelot_policer *pol);
 769 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
 770 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
 771                               struct flow_cls_offload *f, bool ingress);
 772 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
 773                               struct flow_cls_offload *f, bool ingress);
 774 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
 775                             struct flow_cls_offload *f, bool ingress);
 776 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
 777                         const struct switchdev_obj_port_mdb *mdb);
 778 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
 779                         const struct switchdev_obj_port_mdb *mdb);
 780
 781 #endif